jtag_cores.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
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    18 //      Lattice Semiconductor provides no warranty regarding the use or
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    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : jtag_cores.v
    40 // Title            : Instantiates all IP cores on JTAG chain.
    41 // Dependencies     : system_conf.v
    42 // Version          : 6.0.14
    43 //                  : modified to use jtagconn for LM32,
    44 //                  : all technologies 7/10/07
    45 // Version          : 7.0SP2, 3.0
    46 //                  : No Change
    47 // Version          : 3.1
    48 //                  : No Change
    49 // ============================================================================
    51 `include "system_conf.v"
    53 /////////////////////////////////////////////////////
    54 // jtagconn16 Module Definition
    55 /////////////////////////////////////////////////////
    57 module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    58     input  er2_tdo ; 
    59     output jtck ; 
    60     output jtdi ; 
    61     output jshift ; 
    62     output jupdate ; 
    63     output jrstn ; 
    64     output jce2 ; 
    65     output ip_enable ; 
    66 endmodule
    68 /////////////////////////////////////////////////////
    69 // Module interface
    70 /////////////////////////////////////////////////////
    72 (* syn_hier="hard" *) module jtag_cores (
    73     // ----- Inputs -------
    74     reg_d,
    75     reg_addr_d,
    76     // ----- Outputs -------    
    77     reg_update,
    78     reg_q,
    79     reg_addr_q,
    80     jtck,
    81     jrstn
    82     );
    84 /////////////////////////////////////////////////////
    85 // Inputs
    86 /////////////////////////////////////////////////////
    88 input [7:0] reg_d;
    89 input [2:0] reg_addr_d;
    91 /////////////////////////////////////////////////////
    92 // Outputs
    93 /////////////////////////////////////////////////////
    95 output reg_update;
    96 wire   reg_update;
    97 output [7:0] reg_q;
    98 wire   [7:0] reg_q;
    99 output [2:0] reg_addr_q;
   100 wire   [2:0] reg_addr_q;
   102 output jtck;
   103 wire   jtck; 	/* synthesis syn_keep=1 */
   104 output jrstn;
   105 wire   jrstn;  /* synthesis syn_keep=1 */	
   107 /////////////////////////////////////////////////////
   108 // Instantiations
   109 /////////////////////////////////////////////////////
   111 wire jtdi;          /* synthesis syn_keep=1 */
   112 wire er2_tdo2;      /* synthesis syn_keep=1 */
   113 wire jshift;        /* synthesis syn_keep=1 */
   114 wire jupdate;       /* synthesis syn_keep=1 */
   115 wire jce2;          /* synthesis syn_keep=1 */
   116 wire ip_enable;     /* synthesis syn_keep=1 */
   118 (* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   119     .er2_tdo        (er2_tdo2),
   120     .jtck           (jtck),
   121     .jtdi           (jtdi),
   122     .jshift         (jshift),
   123     .jupdate        (jupdate),
   124     .jrstn          (jrstn),
   125     .jce2           (jce2),
   126     .ip_enable      (ip_enable)
   127 );
   129 (* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   130     .JTCK           (jtck),
   131     .JTDI           (jtdi),
   132     .JTDO2          (er2_tdo2),
   133     .JSHIFT         (jshift),
   134     .JUPDATE        (jupdate),
   135     .JRSTN          (jrstn),
   136     .JCE2           (jce2),
   137     .JTAGREG_ENABLE (ip_enable),
   138     .CONTROL_DATAN  (),
   139     .REG_UPDATE     (reg_update),
   140     .REG_D          (reg_d),
   141     .REG_ADDR_D     (reg_addr_d),
   142     .REG_Q          (reg_q),
   143     .REG_ADDR_Q     (reg_addr_q)
   144     );
   146 endmodule