jtag_lm32.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
     6 //   ------------------------------------------------------------------
     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
    23 //   --------------------------------------------------------------------
    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
    27 //                  Hillsboro, OR 97214
    28 //                  U.S.A
    29 //
    30 //                  TEL: 1-800-Lattice (USA and Canada)
    31 //                         503-286-8001 (other locations)
    32 //
    33 //                  web: http://www.latticesemi.com/
    34 //                  email: techsupport@latticesemi.com
    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : jtag_lm32.v
    40 // Title            : JTAG data register for LM32 CPU debug interface
    41 // Version          : 6.0.13
    42 //                  : Initial Release
    43 // Version          : 7.0SP2, 3.0
    44 //                  : No Change
    45 // Version          : 3.1
    46 //                  : No Change
    47 // =============================================================================
    49 /////////////////////////////////////////////////////
    50 // Module interface
    51 /////////////////////////////////////////////////////
    53 module jtag_lm32 (
    54 	input JTCK,
    55 	input JTDI,
    56 	output JTDO2,
    57 	input JSHIFT,
    58 	input JUPDATE,
    59 	input JRSTN,
    60 	input JCE2,
    61 	input JTAGREG_ENABLE,
    62 	input CONTROL_DATAN,
    63 	output REG_UPDATE,
    64 	input [7:0] REG_D,
    65 	input [2:0] REG_ADDR_D,
    66 	output [7:0] REG_Q,
    67 	output [2:0] REG_ADDR_Q
    68 	);
    70 /////////////////////////////////////////////////////
    71 // Internal nets and registers 
    72 /////////////////////////////////////////////////////
    74 wire [9:0] tdibus;
    76 /////////////////////////////////////////////////////
    77 // Instantiations
    78 /////////////////////////////////////////////////////
    80 TYPEA DATA_BIT0 (
    81     .CLK(JTCK),
    82     .RESET_N(JRSTN),
    83     .CLKEN(clk_enable),
    84     .TDI(JTDI),
    85     .TDO(tdibus[0]),
    86     .DATA_OUT(REG_Q[0]),
    87     .DATA_IN(REG_D[0]),
    88     .CAPTURE_DR(captureDr),
    89     .UPDATE_DR(JUPDATE)
    90     );
    92 TYPEA DATA_BIT1 (
    93     .CLK(JTCK),
    94     .RESET_N(JRSTN),
    95     .CLKEN(clk_enable),
    96     .TDI(tdibus[0]),
    97     .TDO(tdibus[1]),
    98     .DATA_OUT(REG_Q[1]),
    99     .DATA_IN(REG_D[1]),
   100     .CAPTURE_DR(captureDr),
   101     .UPDATE_DR(JUPDATE)
   102     );
   104 TYPEA DATA_BIT2 (
   105     .CLK(JTCK),
   106     .RESET_N(JRSTN),
   107     .CLKEN(clk_enable),
   108     .TDI(tdibus[1]),
   109     .TDO(tdibus[2]),
   110     .DATA_OUT(REG_Q[2]),
   111     .DATA_IN(REG_D[2]),
   112     .CAPTURE_DR(captureDr),
   113     .UPDATE_DR(JUPDATE)
   114     );
   116 TYPEA DATA_BIT3 (
   117     .CLK(JTCK),
   118     .RESET_N(JRSTN),
   119     .CLKEN(clk_enable),
   120     .TDI(tdibus[2]),
   121     .TDO(tdibus[3]),
   122     .DATA_OUT(REG_Q[3]),
   123     .DATA_IN(REG_D[3]),
   124     .CAPTURE_DR(captureDr),
   125     .UPDATE_DR(JUPDATE)
   126     );
   128 TYPEA DATA_BIT4 (
   129     .CLK(JTCK),
   130     .RESET_N(JRSTN),
   131     .CLKEN(clk_enable),
   132     .TDI(tdibus[3]),
   133     .TDO(tdibus[4]),
   134     .DATA_OUT(REG_Q[4]),
   135     .DATA_IN(REG_D[4]),
   136     .CAPTURE_DR(captureDr),
   137     .UPDATE_DR(JUPDATE)
   138     );
   140 TYPEA DATA_BIT5 (
   141     .CLK(JTCK),
   142     .RESET_N(JRSTN),
   143     .CLKEN(clk_enable),
   144     .TDI(tdibus[4]),
   145     .TDO(tdibus[5]),
   146     .DATA_OUT(REG_Q[5]),
   147     .DATA_IN(REG_D[5]),
   148     .CAPTURE_DR(captureDr),
   149     .UPDATE_DR(JUPDATE)
   150     );
   152 TYPEA DATA_BIT6 (
   153     .CLK(JTCK),
   154     .RESET_N(JRSTN),
   155     .CLKEN(clk_enable),
   156     .TDI(tdibus[5]),
   157     .TDO(tdibus[6]),
   158     .DATA_OUT(REG_Q[6]),
   159     .DATA_IN(REG_D[6]),
   160     .CAPTURE_DR(captureDr),
   161     .UPDATE_DR(JUPDATE)
   162     );
   164 TYPEA DATA_BIT7 (
   165     .CLK(JTCK),
   166     .RESET_N(JRSTN),
   167     .CLKEN(clk_enable),
   168     .TDI(tdibus[6]),
   169     .TDO(tdibus[7]),
   170     .DATA_OUT(REG_Q[7]),
   171     .DATA_IN(REG_D[7]),
   172     .CAPTURE_DR(captureDr),
   173     .UPDATE_DR(JUPDATE)
   174     );
   176 TYPEA ADDR_BIT0 (
   177     .CLK(JTCK),
   178     .RESET_N(JRSTN),
   179     .CLKEN(clk_enable),
   180     .TDI(tdibus[7]),
   181     .TDO(tdibus[8]),
   182     .DATA_OUT(REG_ADDR_Q[0]),
   183     .DATA_IN(REG_ADDR_D[0]),
   184     .CAPTURE_DR(captureDr),
   185     .UPDATE_DR(JUPDATE)
   186     );
   188 TYPEA ADDR_BIT1 (
   189     .CLK(JTCK),
   190     .RESET_N(JRSTN),
   191     .CLKEN(clk_enable),
   192     .TDI(tdibus[8]),
   193     .TDO(tdibus[9]),
   194     .DATA_OUT(REG_ADDR_Q[1]),
   195     .DATA_IN(REG_ADDR_D[1]),
   196     .CAPTURE_DR(captureDr),
   197     .UPDATE_DR(JUPDATE)
   198     );
   200 TYPEA ADDR_BIT2 (
   201     .CLK(JTCK),
   202     .RESET_N(JRSTN),
   203     .CLKEN(clk_enable),
   204     .TDI(tdibus[9]),
   205     .TDO(JTDO2),
   206     .DATA_OUT(REG_ADDR_Q[2]),
   207     .DATA_IN(REG_ADDR_D[2]),
   208     .CAPTURE_DR(captureDr),
   209     .UPDATE_DR(JUPDATE)
   210     );
   212 /////////////////////////////////////////////////////
   213 // Combinational logic
   214 /////////////////////////////////////////////////////
   216 assign clk_enable = JTAGREG_ENABLE & JCE2;
   217 assign captureDr = !JSHIFT & JCE2;
   218 // JCE2 is only active during shift
   219 assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   221 endmodule