lm32_decoder.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
     6 //   ------------------------------------------------------------------
     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
    23 //   --------------------------------------------------------------------
    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
    27 //                  Hillsboro, OR 97214
    28 //                  U.S.A
    29 //
    30 //                  TEL: 1-800-Lattice (USA and Canada)
    31 //                         503-286-8001 (other locations)
    32 //
    33 //                  web: http://www.latticesemi.com/
    34 //                  email: techsupport@latticesemi.com
    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : lm32_decoder.v
    40 // Title            : Instruction decoder
    41 // Dependencies     : lm32_include.v
    42 // Version          : 6.1.17
    43 //                  : Initial Release
    44 // Version          : 7.0SP2, 3.0
    45 //                  : No Change
    46 // Version          : 3.1
    47 //                  : Support for static branch prediction. Information about
    48 //                  : branch type is generated and passed on to the predictor.
    49 // Version          : 3.2
    50 //                  : No change
    51 // Version          : 3.3
    52 //                  : Renamed port names that conflict with keywords reserved
    53 //                  : in System-Verilog.
    54 // =============================================================================
    56 `include "lm32_include.v"
    58 // Index of opcode field in an instruction
    59 `define LM32_OPCODE_RNG         31:26
    60 `define LM32_OP_RNG             30:26
    62 // Opcodes - Some are only listed as 5 bits as their MSB is a don't care
    63 `define LM32_OPCODE_ADD         5'b01101
    64 `define LM32_OPCODE_AND         5'b01000
    65 `define LM32_OPCODE_ANDHI       6'b011000
    66 `define LM32_OPCODE_B           6'b110000
    67 `define LM32_OPCODE_BI          6'b111000
    68 `define LM32_OPCODE_BE          6'b010001
    69 `define LM32_OPCODE_BG          6'b010010
    70 `define LM32_OPCODE_BGE         6'b010011
    71 `define LM32_OPCODE_BGEU        6'b010100
    72 `define LM32_OPCODE_BGU         6'b010101
    73 `define LM32_OPCODE_BNE         6'b010111
    74 `define LM32_OPCODE_CALL        6'b110110
    75 `define LM32_OPCODE_CALLI       6'b111110
    76 `define LM32_OPCODE_CMPE        5'b11001
    77 `define LM32_OPCODE_CMPG        5'b11010
    78 `define LM32_OPCODE_CMPGE       5'b11011
    79 `define LM32_OPCODE_CMPGEU      5'b11100
    80 `define LM32_OPCODE_CMPGU       5'b11101
    81 `define LM32_OPCODE_CMPNE       5'b11111
    82 `define LM32_OPCODE_DIVU        6'b100011
    83 `define LM32_OPCODE_LB          6'b000100
    84 `define LM32_OPCODE_LBU         6'b010000
    85 `define LM32_OPCODE_LH          6'b000111
    86 `define LM32_OPCODE_LHU         6'b001011
    87 `define LM32_OPCODE_LW          6'b001010
    88 `define LM32_OPCODE_MODU        6'b110001
    89 `define LM32_OPCODE_MUL         5'b00010
    90 `define LM32_OPCODE_NOR         5'b00001
    91 `define LM32_OPCODE_OR          5'b01110
    92 `define LM32_OPCODE_ORHI        6'b011110
    93 `define LM32_OPCODE_RAISE       6'b101011
    94 `define LM32_OPCODE_RCSR        6'b100100
    95 `define LM32_OPCODE_SB          6'b001100
    96 `define LM32_OPCODE_SEXTB       6'b101100
    97 `define LM32_OPCODE_SEXTH       6'b110111
    98 `define LM32_OPCODE_SH          6'b000011
    99 `define LM32_OPCODE_SL          5'b01111
   100 `define LM32_OPCODE_SR          5'b00101
   101 `define LM32_OPCODE_SRU         5'b00000
   102 `define LM32_OPCODE_SUB         6'b110010
   103 `define LM32_OPCODE_SW          6'b010110
   104 `define LM32_OPCODE_USER        6'b110011
   105 `define LM32_OPCODE_WCSR        6'b110100
   106 `define LM32_OPCODE_XNOR        5'b01001
   107 `define LM32_OPCODE_XOR         5'b00110
   109 /////////////////////////////////////////////////////
   110 // Module interface
   111 /////////////////////////////////////////////////////
   113 module lm32_decoder (
   114     // ----- Inputs -------
   115     instruction,
   116     // ----- Outputs -------
   117     d_result_sel_0,
   118     d_result_sel_1,        
   119     x_result_sel_csr,
   120 `ifdef LM32_MC_ARITHMETIC_ENABLED
   121     x_result_sel_mc_arith,
   122 `endif    
   123 `ifdef LM32_NO_BARREL_SHIFT    
   124     x_result_sel_shift,
   125 `endif
   126 `ifdef CFG_SIGN_EXTEND_ENABLED
   127     x_result_sel_sext,
   128 `endif    
   129     x_result_sel_logic,
   130 `ifdef CFG_USER_ENABLED
   131     x_result_sel_user,
   132 `endif
   133     x_result_sel_add,
   134     m_result_sel_compare,
   135 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   136     m_result_sel_shift,  
   137 `endif    
   138     w_result_sel_load,
   139 `ifdef CFG_PL_MULTIPLY_ENABLED
   140     w_result_sel_mul,
   141 `endif
   142     x_bypass_enable,
   143     m_bypass_enable,
   144     read_enable_0,
   145     read_idx_0,
   146     read_enable_1,
   147     read_idx_1,
   148     write_enable,
   149     write_idx,
   150     immediate,
   151     branch_offset,
   152     load,
   153     store,
   154     size,
   155     sign_extend,
   156     adder_op,
   157     logic_op,
   158 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   159     direction,
   160 `endif
   161 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   162     shift_left,
   163     shift_right,
   164 `endif
   165 `ifdef CFG_MC_MULTIPLY_ENABLED
   166     multiply,
   167 `endif
   168 `ifdef CFG_MC_DIVIDE_ENABLED
   169     divide,
   170     modulus,
   171 `endif
   172     branch,
   173     branch_reg,
   174     condition,
   175     bi_conditional,
   176     bi_unconditional,
   177 `ifdef CFG_DEBUG_ENABLED
   178     break_opcode,
   179 `endif
   180     scall,
   181     eret,
   182 `ifdef CFG_DEBUG_ENABLED
   183     bret,
   184 `endif
   185 `ifdef CFG_USER_ENABLED
   186     user_opcode,
   187 `endif
   188     csr_write_enable
   189     );
   191 /////////////////////////////////////////////////////
   192 // Inputs
   193 /////////////////////////////////////////////////////
   195 input [`LM32_INSTRUCTION_RNG] instruction;       // Instruction to decode
   197 /////////////////////////////////////////////////////
   198 // Outputs
   199 /////////////////////////////////////////////////////
   201 output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
   202 reg    [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
   203 output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
   204 reg    [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
   205 output x_result_sel_csr;
   206 reg    x_result_sel_csr;
   207 `ifdef LM32_MC_ARITHMETIC_ENABLED
   208 output x_result_sel_mc_arith;
   209 reg    x_result_sel_mc_arith;
   210 `endif
   211 `ifdef LM32_NO_BARREL_SHIFT    
   212 output x_result_sel_shift;
   213 reg    x_result_sel_shift;
   214 `endif
   215 `ifdef CFG_SIGN_EXTEND_ENABLED
   216 output x_result_sel_sext;
   217 reg    x_result_sel_sext;
   218 `endif
   219 output x_result_sel_logic;
   220 reg    x_result_sel_logic;
   221 `ifdef CFG_USER_ENABLED
   222 output x_result_sel_user;
   223 reg    x_result_sel_user;
   224 `endif
   225 output x_result_sel_add;
   226 reg    x_result_sel_add;
   227 output m_result_sel_compare;
   228 reg    m_result_sel_compare;
   229 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   230 output m_result_sel_shift;
   231 reg    m_result_sel_shift;
   232 `endif
   233 output w_result_sel_load;
   234 reg    w_result_sel_load;
   235 `ifdef CFG_PL_MULTIPLY_ENABLED
   236 output w_result_sel_mul;
   237 reg    w_result_sel_mul;
   238 `endif
   239 output x_bypass_enable;
   240 wire   x_bypass_enable;
   241 output m_bypass_enable;
   242 wire   m_bypass_enable;
   243 output read_enable_0;
   244 wire   read_enable_0;
   245 output [`LM32_REG_IDX_RNG] read_idx_0;
   246 wire   [`LM32_REG_IDX_RNG] read_idx_0;
   247 output read_enable_1;
   248 wire   read_enable_1;
   249 output [`LM32_REG_IDX_RNG] read_idx_1;
   250 wire   [`LM32_REG_IDX_RNG] read_idx_1;
   251 output write_enable;
   252 wire   write_enable;
   253 output [`LM32_REG_IDX_RNG] write_idx;
   254 wire   [`LM32_REG_IDX_RNG] write_idx;
   255 output [`LM32_WORD_RNG] immediate;
   256 wire   [`LM32_WORD_RNG] immediate;
   257 output [`LM32_PC_RNG] branch_offset;
   258 wire   [`LM32_PC_RNG] branch_offset;
   259 output load;
   260 wire   load;
   261 output store;
   262 wire   store;
   263 output [`LM32_SIZE_RNG] size;
   264 wire   [`LM32_SIZE_RNG] size;
   265 output sign_extend;
   266 wire   sign_extend;
   267 output adder_op;
   268 wire   adder_op;
   269 output [`LM32_LOGIC_OP_RNG] logic_op;
   270 wire   [`LM32_LOGIC_OP_RNG] logic_op;
   271 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   272 output direction;
   273 wire   direction;
   274 `endif
   275 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   276 output shift_left;
   277 wire   shift_left;
   278 output shift_right;
   279 wire   shift_right;
   280 `endif
   281 `ifdef CFG_MC_MULTIPLY_ENABLED
   282 output multiply;
   283 wire   multiply;
   284 `endif
   285 `ifdef CFG_MC_DIVIDE_ENABLED
   286 output divide;
   287 wire   divide;
   288 output modulus;
   289 wire   modulus;
   290 `endif
   291 output branch;
   292 wire   branch;
   293 output branch_reg;
   294 wire   branch_reg;
   295 output [`LM32_CONDITION_RNG] condition;
   296 wire   [`LM32_CONDITION_RNG] condition;
   297 output bi_conditional;
   298 wire bi_conditional;
   299 output bi_unconditional;
   300 wire bi_unconditional;
   301 `ifdef CFG_DEBUG_ENABLED
   302 output break_opcode;
   303 wire   break_opcode;
   304 `endif
   305 output scall;
   306 wire   scall;
   307 output eret;
   308 wire   eret;
   309 `ifdef CFG_DEBUG_ENABLED
   310 output bret;
   311 wire   bret;
   312 `endif
   313 `ifdef CFG_USER_ENABLED
   314 output [`LM32_USER_OPCODE_RNG] user_opcode;
   315 wire   [`LM32_USER_OPCODE_RNG] user_opcode;
   316 `endif
   317 output csr_write_enable;
   318 wire   csr_write_enable;
   320 /////////////////////////////////////////////////////
   321 // Internal nets and registers 
   322 /////////////////////////////////////////////////////
   324 wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
   325 wire [`LM32_WORD_RNG] high_immediate;           // Immediate as high 16 bits
   326 wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
   327 wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
   328 wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
   329 wire select_high_immediate;                     // Whether to select the high immediate  
   330 wire select_call_immediate;                     // Whether to select the call immediate 
   332 /////////////////////////////////////////////////////
   333 // Functions
   334 /////////////////////////////////////////////////////
   336 `include "lm32_functions.v"
   338 /////////////////////////////////////////////////////
   339 // Combinational logic
   340 /////////////////////////////////////////////////////
   342 // Determine opcode
   343 assign op_add    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
   344 assign op_and    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
   345 assign op_andhi  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
   346 assign op_b      = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
   347 assign op_bi     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
   348 assign op_be     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
   349 assign op_bg     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
   350 assign op_bge    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
   351 assign op_bgeu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
   352 assign op_bgu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
   353 assign op_bne    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
   354 assign op_call   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
   355 assign op_calli  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
   356 assign op_cmpe   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
   357 assign op_cmpg   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
   358 assign op_cmpge  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
   359 assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
   360 assign op_cmpgu  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
   361 assign op_cmpne  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
   362 `ifdef CFG_MC_DIVIDE_ENABLED
   363 assign op_divu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
   364 `endif
   365 assign op_lb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
   366 assign op_lbu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
   367 assign op_lh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
   368 assign op_lhu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
   369 assign op_lw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
   370 `ifdef CFG_MC_DIVIDE_ENABLED
   371 assign op_modu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
   372 `endif
   373 `ifdef LM32_MULTIPLY_ENABLED
   374 assign op_mul    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
   375 `endif
   376 assign op_nor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
   377 assign op_or     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
   378 assign op_orhi   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
   379 assign op_raise  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
   380 assign op_rcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
   381 assign op_sb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
   382 `ifdef CFG_SIGN_EXTEND_ENABLED
   383 assign op_sextb  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
   384 assign op_sexth  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
   385 `endif
   386 assign op_sh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
   387 `ifdef LM32_BARREL_SHIFT_ENABLED
   388 assign op_sl     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;      
   389 `endif
   390 assign op_sr     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
   391 assign op_sru    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
   392 assign op_sub    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
   393 assign op_sw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
   394 assign op_user   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
   395 assign op_wcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
   396 assign op_xnor   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
   397 assign op_xor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
   399 // Group opcodes by function
   400 assign arith = op_add | op_sub;
   401 assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
   402 assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
   403 assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
   404 assign bi_unconditional = op_bi;
   405 assign bra = op_b | bi_unconditional | bi_conditional;
   406 assign call = op_call | op_calli;
   407 `ifdef LM32_BARREL_SHIFT_ENABLED
   408 assign shift = op_sl | op_sr | op_sru;
   409 `endif
   410 `ifdef LM32_NO_BARREL_SHIFT
   411 assign shift = op_sr | op_sru;
   412 `endif
   413 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   414 assign shift_left = op_sl;
   415 assign shift_right = op_sr | op_sru;
   416 `endif
   417 `ifdef CFG_SIGN_EXTEND_ENABLED
   418 assign sext = op_sextb | op_sexth;
   419 `endif
   420 `ifdef LM32_MULTIPLY_ENABLED
   421 assign multiply = op_mul;
   422 `endif
   423 `ifdef CFG_MC_DIVIDE_ENABLED
   424 assign divide = op_divu; 
   425 assign modulus = op_modu;
   426 `endif
   427 assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
   428 assign store = op_sb | op_sh | op_sw;
   430 // Select pipeline multiplexor controls
   431 always @(*)
   432 begin
   433     // D stage
   434     if (call) 
   435         d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
   436     else 
   437         d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
   438     if (call) 
   439         d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;         
   440     else if ((instruction[31] == 1'b0) && !bra) 
   441         d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
   442     else
   443         d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 
   444     // X stage
   445     x_result_sel_csr = `FALSE;
   446 `ifdef LM32_MC_ARITHMETIC_ENABLED
   447     x_result_sel_mc_arith = `FALSE;
   448 `endif
   449 `ifdef LM32_NO_BARREL_SHIFT
   450     x_result_sel_shift = `FALSE;
   451 `endif
   452 `ifdef CFG_SIGN_EXTEND_ENABLED
   453     x_result_sel_sext = `FALSE;
   454 `endif
   455     x_result_sel_logic = `FALSE;
   456 `ifdef CFG_USER_ENABLED        
   457     x_result_sel_user = `FALSE;
   458 `endif
   459     x_result_sel_add = `FALSE;
   460     if (op_rcsr)
   461         x_result_sel_csr = `TRUE;
   462 `ifdef LM32_MC_ARITHMETIC_ENABLED    
   463 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   464     else if (shift_left | shift_right) 
   465         x_result_sel_mc_arith = `TRUE;
   466 `endif
   467 `ifdef CFG_MC_DIVIDE_ENABLED
   468     else if (divide | modulus)
   469         x_result_sel_mc_arith = `TRUE;        
   470 `endif
   471 `ifdef CFG_MC_MULTIPLY_ENABLED
   472     else if (multiply)
   473         x_result_sel_mc_arith = `TRUE;            
   474 `endif
   475 `endif
   476 `ifdef LM32_NO_BARREL_SHIFT
   477     else if (shift)
   478         x_result_sel_shift = `TRUE;        
   479 `endif
   480 `ifdef CFG_SIGN_EXTEND_ENABLED
   481     else if (sext)
   482         x_result_sel_sext = `TRUE;
   483 `endif        
   484     else if (logical) 
   485         x_result_sel_logic = `TRUE;
   486 `ifdef CFG_USER_ENABLED        
   487     else if (op_user)
   488         x_result_sel_user = `TRUE;
   489 `endif
   490     else 
   491         x_result_sel_add = `TRUE;        
   493     // M stage
   495     m_result_sel_compare = cmp;
   496 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   497     m_result_sel_shift = shift;
   498 `endif
   500     // W stage
   501     w_result_sel_load = load;
   502 `ifdef CFG_PL_MULTIPLY_ENABLED
   503     w_result_sel_mul = op_mul; 
   504 `endif
   505 end
   507 // Set if result is valid at end of X stage
   508 assign x_bypass_enable =  arith 
   509                         | logical
   510 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   511                         | shift_left
   512                         | shift_right
   513 `endif                        
   514 `ifdef CFG_MC_MULTIPLY_ENABLED
   515                         | multiply
   516 `endif
   517 `ifdef CFG_MC_DIVIDE_ENABLED
   518                         | divide
   519                         | modulus
   520 `endif
   521 `ifdef LM32_NO_BARREL_SHIFT
   522                         | shift
   523 `endif                  
   524 `ifdef CFG_SIGN_EXTEND_ENABLED
   525                         | sext 
   526 `endif                        
   527 `ifdef CFG_USER_ENABLED
   528                         | op_user
   529 `endif
   530                         | op_rcsr
   531                         ;
   532 // Set if result is valid at end of M stage                        
   533 assign m_bypass_enable = x_bypass_enable 
   534 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   535                         | shift
   536 `endif
   537                         | cmp
   538                         ;
   539 // Register file read port 0                        
   540 assign read_enable_0 = ~(op_bi | op_calli);
   541 assign read_idx_0 = instruction[25:21];
   542 // Register file read port 1 
   543 assign read_enable_1 = ~(op_bi | op_calli | load);
   544 assign read_idx_1 = instruction[20:16];
   545 // Register file write port
   546 assign write_enable = ~(bra | op_raise | store | op_wcsr);
   547 assign write_idx = call
   548                     ? 5'd29
   549                     : instruction[31] == 1'b0 
   550                         ? instruction[20:16] 
   551                         : instruction[15:11];
   553 // Size of load/stores                        
   554 assign size = instruction[27:26];
   555 // Whether to sign or zero extend
   556 assign sign_extend = instruction[28];                      
   557 // Set adder_op to 1 to perform a subtraction
   558 assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
   559 // Logic operation (and, or, etc)
   560 assign logic_op = instruction[29:26];
   561 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   562 // Shift direction
   563 assign direction = instruction[29];
   564 `endif
   565 // Control flow microcodes
   566 assign branch = bra | call;
   567 assign branch_reg = op_call | op_b;
   568 assign condition = instruction[28:26];      
   569 `ifdef CFG_DEBUG_ENABLED
   570 assign break_opcode = op_raise & ~instruction[2];
   571 `endif
   572 assign scall = op_raise & instruction[2];
   573 assign eret = op_b & (instruction[25:21] == 5'd30);
   574 `ifdef CFG_DEBUG_ENABLED
   575 assign bret = op_b & (instruction[25:21] == 5'd31);
   576 `endif
   577 `ifdef CFG_USER_ENABLED
   578 // Extract user opcode
   579 assign user_opcode = instruction[10:0];
   580 `endif
   581 // CSR read/write
   582 assign csr_write_enable = op_wcsr;
   584 // Extract immediate from instruction
   586 assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
   587 assign select_high_immediate = op_andhi | op_orhi;
   588 assign select_call_immediate = instruction[31];
   590 assign high_immediate = {instruction[15:0], 16'h0000};
   591 assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
   592 assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
   593 assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
   595 assign immediate = select_high_immediate == `TRUE 
   596                         ? high_immediate 
   597                         : extended_immediate;
   599 assign branch_offset = select_call_immediate == `TRUE   
   600                         ? call_immediate
   601                         : branch_immediate;
   603 endmodule