Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
1 // ==================================================================
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37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_icache.v
40 // Title : Instruction cache
41 // Dependencies : lm32_include.v
42 //
43 // Version 3.5
44 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
45 // cause segmentation fault due to incorrect fetches.
46 //
47 // Version 3.1
48 // 1. Feature: Support for user-selected resource usage when implementing
49 // cache memory. Additional parameters must be defined when invoking module
50 // lm32_ram. Instruction cache miss mechanism is dependent on branch
51 // prediction being performed in D stage of pipeline.
52 //
53 // Version 7.0SP2, 3.0
54 // No change
55 // =============================================================================
57 `include "lm32_include.v"
59 `ifdef CFG_ICACHE_ENABLED
61 `define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
62 `define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
63 `define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
64 `define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
66 `define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
67 `define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
68 `define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
69 `define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
71 `define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
72 `define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
73 `define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
74 `define LM32_IC_TAGS_VALID_RNG 0
76 `define LM32_IC_STATE_RNG 3:0
77 `define LM32_IC_STATE_FLUSH_INIT 4'b0001
78 `define LM32_IC_STATE_FLUSH 4'b0010
79 `define LM32_IC_STATE_CHECK 4'b0100
80 `define LM32_IC_STATE_REFILL 4'b1000
82 /////////////////////////////////////////////////////
83 // Module interface
84 /////////////////////////////////////////////////////
86 module lm32_icache (
87 // ----- Inputs -----
88 clk_i,
89 rst_i,
90 stall_a,
91 stall_f,
92 address_a,
93 address_f,
94 read_enable_f,
95 refill_ready,
96 refill_data,
97 iflush,
98 `ifdef CFG_IROM_ENABLED
99 select_f,
100 `endif
101 valid_d,
102 branch_predict_taken_d,
103 // ----- Outputs -----
104 stall_request,
105 restart_request,
106 refill_request,
107 refill_address,
108 refilling,
109 inst
110 );
112 /////////////////////////////////////////////////////
113 // Parameters
114 /////////////////////////////////////////////////////
116 parameter associativity = 1; // Associativity of the cache (Number of ways)
117 parameter sets = 512; // Number of sets
118 parameter bytes_per_line = 16; // Number of bytes per cache line
119 parameter base_address = 0; // Base address of cachable memory
120 parameter limit = 0; // Limit (highest address) of cachable memory
122 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
123 localparam addr_set_width = clogb2(sets)-1;
124 localparam addr_offset_lsb = 2;
125 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
126 localparam addr_set_lsb = (addr_offset_msb+1);
127 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
128 localparam addr_tag_lsb = (addr_set_msb+1);
129 localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
130 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
132 /////////////////////////////////////////////////////
133 // Inputs
134 /////////////////////////////////////////////////////
136 input clk_i; // Clock
137 input rst_i; // Reset
139 input stall_a; // Stall instruction in A stage
140 input stall_f; // Stall instruction in F stage
142 input valid_d; // Valid instruction in D stage
143 input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
145 input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
146 input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
147 input read_enable_f; // Indicates if cache access is valid
149 input refill_ready; // Next word of refill data is ready
150 input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
152 input iflush; // Flush the cache
153 `ifdef CFG_IROM_ENABLED
154 input select_f; // Instruction in F stage is mapped through instruction cache
155 `endif
157 /////////////////////////////////////////////////////
158 // Outputs
159 /////////////////////////////////////////////////////
161 output stall_request; // Request to stall the pipeline
162 wire stall_request;
163 output restart_request; // Request to restart instruction that caused the cache miss
164 reg restart_request;
165 output refill_request; // Request to refill a cache line
166 wire refill_request;
167 output [`LM32_PC_RNG] refill_address; // Base address of cache refill
168 reg [`LM32_PC_RNG] refill_address;
169 output refilling; // Indicates the instruction cache is currently refilling
170 reg refilling;
171 output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
172 wire [`LM32_INSTRUCTION_RNG] inst;
174 /////////////////////////////////////////////////////
175 // Internal nets and registers
176 /////////////////////////////////////////////////////
178 wire enable;
179 wire [0:associativity-1] way_mem_we;
180 wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
181 wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
182 wire [0:associativity-1] way_valid;
183 wire [0:associativity-1] way_match;
184 wire miss;
186 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
187 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
188 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
189 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
190 wire [`LM32_IC_TAGS_RNG] tmem_write_data;
192 reg [`LM32_IC_STATE_RNG] state;
193 wire flushing;
194 wire check;
195 wire refill;
197 reg [associativity-1:0] refill_way_select;
198 reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
199 wire last_refill;
200 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
202 genvar i;
204 /////////////////////////////////////////////////////
205 // Functions
206 /////////////////////////////////////////////////////
208 `include "lm32_functions.v"
210 /////////////////////////////////////////////////////
211 // Instantiations
212 /////////////////////////////////////////////////////
214 generate
215 for (i = 0; i < associativity; i = i + 1)
216 begin : memories
218 lm32_ram
219 #(
220 // ----- Parameters -------
221 .data_width (32),
222 .address_width (`LM32_IC_DMEM_ADDR_WIDTH),
223 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
224 .RAM_IMPLEMENTATION ("EBR"),
225 .RAM_TYPE ("RAM_DP_TRUE")
226 `else
227 `ifdef CFG_ICACHE_DAT_USE_DP
228 .RAM_IMPLEMENTATION ("EBR"),
229 .RAM_TYPE ("RAM_DP")
230 `else
231 `ifdef CFG_ICACHE_DAT_USE_SLICE
232 .RAM_IMPLEMENTATION ("SLICE")
233 `else
234 .RAM_IMPLEMENTATION ("AUTO")
235 `endif
236 `endif
237 `endif
238 )
239 way_0_data_ram
240 (
241 // ----- Inputs -------
242 .read_clk (clk_i),
243 .write_clk (clk_i),
244 .reset (rst_i),
245 .read_address (dmem_read_address),
246 .enable_read (enable),
247 .write_address (dmem_write_address),
248 .enable_write (`TRUE),
249 .write_enable (way_mem_we[i]),
250 .write_data (refill_data),
251 // ----- Outputs -------
252 .read_data (way_data[i])
253 );
255 lm32_ram
256 #(
257 // ----- Parameters -------
258 .data_width (`LM32_IC_TAGS_WIDTH),
259 .address_width (`LM32_IC_TMEM_ADDR_WIDTH),
260 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
261 .RAM_IMPLEMENTATION ("EBR"),
262 .RAM_TYPE ("RAM_DP_TRUE")
263 `else
264 `ifdef CFG_ICACHE_DAT_USE_DP
265 .RAM_IMPLEMENTATION ("EBR"),
266 .RAM_TYPE ("RAM_DP")
267 `else
268 `ifdef CFG_ICACHE_DAT_USE_SLICE
269 .RAM_IMPLEMENTATION ("SLICE")
270 `else
271 .RAM_IMPLEMENTATION ("AUTO")
272 `endif
273 `endif
274 `endif
275 )
276 way_0_tag_ram
277 (
278 // ----- Inputs -------
279 .read_clk (clk_i),
280 .write_clk (clk_i),
281 .reset (rst_i),
282 .read_address (tmem_read_address),
283 .enable_read (enable),
284 .write_address (tmem_write_address),
285 .enable_write (`TRUE),
286 .write_enable (way_mem_we[i] | flushing),
287 .write_data (tmem_write_data),
288 // ----- Outputs -------
289 .read_data ({way_tag[i], way_valid[i]})
290 );
292 end
293 endgenerate
295 /////////////////////////////////////////////////////
296 // Combinational logic
297 /////////////////////////////////////////////////////
299 // Compute which ways in the cache match the address address being read
300 generate
301 for (i = 0; i < associativity; i = i + 1)
302 begin : match
303 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
304 end
305 endgenerate
307 // Select data from way that matched the address being read
308 generate
309 if (associativity == 1)
310 begin : inst_1
311 assign inst = way_match[0] ? way_data[0] : 32'b0;
312 end
313 else if (associativity == 2)
314 begin : inst_2
315 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
316 end
317 endgenerate
319 // Compute address to use to index into the data memories
320 generate
321 if (bytes_per_line > 4)
322 assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
323 else
324 assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
325 endgenerate
327 assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
329 // Compute address to use to index into the tag memories
330 assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
331 assign tmem_write_address = flushing
332 ? flush_set
333 : refill_address[`LM32_IC_ADDR_SET_RNG];
335 // Compute signal to indicate when we are on the last refill accesses
336 generate
337 if (bytes_per_line > 4)
338 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
339 else
340 assign last_refill = `TRUE;
341 endgenerate
343 // Compute data and tag memory access enable
344 assign enable = (stall_a == `FALSE);
346 // Compute data and tag memory write enables
347 generate
348 if (associativity == 1)
349 begin : we_1
350 assign way_mem_we[0] = (refill_ready == `TRUE);
351 end
352 else
353 begin : we_2
354 assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
355 assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
356 end
357 endgenerate
359 // On the last refill cycle set the valid bit, for all other writes it should be cleared
360 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
361 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
363 // Signals that indicate which state we are in
364 assign flushing = |state[1:0];
365 assign check = state[2];
366 assign refill = state[3];
368 assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
369 assign stall_request = (check == `FALSE);
370 assign refill_request = (refill == `TRUE);
372 /////////////////////////////////////////////////////
373 // Sequential logic
374 /////////////////////////////////////////////////////
376 // Record way selected for replacement on a cache miss
377 generate
378 if (associativity >= 2)
379 begin : way_select
380 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
381 begin
382 if (rst_i == `TRUE)
383 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
384 else
385 begin
386 if (miss == `TRUE)
387 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
388 end
389 end
390 end
391 endgenerate
393 // Record whether we are refilling
394 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
395 begin
396 if (rst_i == `TRUE)
397 refilling <= `FALSE;
398 else
399 refilling <= refill;
400 end
402 // Instruction cache control FSM
403 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
404 begin
405 if (rst_i == `TRUE)
406 begin
407 state <= `LM32_IC_STATE_FLUSH_INIT;
408 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
409 refill_address <= {`LM32_PC_WIDTH{1'bx}};
410 restart_request <= `FALSE;
411 end
412 else
413 begin
414 case (state)
416 // Flush the cache for the first time after reset
417 `LM32_IC_STATE_FLUSH_INIT:
418 begin
419 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
420 state <= `LM32_IC_STATE_CHECK;
421 flush_set <= flush_set - 1'b1;
422 end
424 // Flush the cache in response to an write to the ICC CSR
425 `LM32_IC_STATE_FLUSH:
426 begin
427 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
428 `ifdef CFG_IROM_ENABLED
429 if (select_f)
430 state <= `LM32_IC_STATE_REFILL;
431 else
432 `endif
433 state <= `LM32_IC_STATE_CHECK;
435 flush_set <= flush_set - 1'b1;
436 end
438 // Check for cache misses
439 `LM32_IC_STATE_CHECK:
440 begin
441 if (stall_a == `FALSE)
442 restart_request <= `FALSE;
443 if (iflush == `TRUE)
444 begin
445 refill_address <= address_f;
446 state <= `LM32_IC_STATE_FLUSH;
447 end
448 else if (miss == `TRUE)
449 begin
450 refill_address <= address_f;
451 state <= `LM32_IC_STATE_REFILL;
452 end
453 end
455 // Refill a cache line
456 `LM32_IC_STATE_REFILL:
457 begin
458 if (refill_ready == `TRUE)
459 begin
460 if (last_refill == `TRUE)
461 begin
462 restart_request <= `TRUE;
463 state <= `LM32_IC_STATE_CHECK;
464 end
465 end
466 end
468 endcase
469 end
470 end
472 generate
473 if (bytes_per_line > 4)
474 begin
475 // Refill offset
476 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
477 begin
478 if (rst_i == `TRUE)
479 refill_offset <= {addr_offset_width{1'b0}};
480 else
481 begin
482 case (state)
484 // Check for cache misses
485 `LM32_IC_STATE_CHECK:
486 begin
487 if (iflush == `TRUE)
488 refill_offset <= {addr_offset_width{1'b0}};
489 else if (miss == `TRUE)
490 refill_offset <= {addr_offset_width{1'b0}};
491 end
493 // Refill a cache line
494 `LM32_IC_STATE_REFILL:
495 begin
496 if (refill_ready == `TRUE)
497 refill_offset <= refill_offset + 1'b1;
498 end
500 endcase
501 end
502 end
503 end
504 endgenerate
506 endmodule
508 `endif