lm32_include.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
     6 //   ------------------------------------------------------------------
     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
    23 //   --------------------------------------------------------------------
    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
    27 //                  Hillsboro, OR 97214
    28 //                  U.S.A
    29 //
    30 //                  TEL: 1-800-Lattice (USA and Canada)
    31 //                         503-286-8001 (other locations)
    32 //
    33 //                  web: http://www.latticesemi.com/
    34 //                  email: techsupport@latticesemi.com
    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : lm32_include.v
    40 // Title            : CPU global macros
    41 // Version          : 6.1.17
    42 //                  : Initial Release
    43 // Version          : 7.0SP2, 3.0
    44 //                  : No Change
    45 // Version          : 3.1
    46 //                  : No Change
    47 // Version          : 3.2
    48 //                  : No Change
    49 // Version          : 3.3
    50 //                  : Support for extended configuration register
    51 // =============================================================================
    53 `ifdef LM32_INCLUDE_V
    54 `else
    55 `define LM32_INCLUDE_V
    57 // Configuration options
    58 `include "system_conf.v"
    60 `ifdef TRUE
    61 `else
    62 `define TRUE    1'b1
    63 `define FALSE   1'b0
    64 `define TRUE_N  1'b0
    65 `define FALSE_N 1'b1
    66 `endif
    68 // Wishbone configuration
    69 `define CFG_IWB_ENABLED
    70 `define CFG_DWB_ENABLED
    72 // Data-path width
    73 `define LM32_WORD_WIDTH                 32
    74 `define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
    75 `define LM32_SHIFT_WIDTH                5
    76 `define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
    77 `define LM32_BYTE_SELECT_WIDTH          4
    78 `define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
    80 // Register file size
    81 `define LM32_REGISTERS                  32
    82 `define LM32_REG_IDX_WIDTH              5
    83 `define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
    85 // Standard register numbers
    86 `define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
    87 `define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
    88 `define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
    90 // Range of Program Counter. Two LSBs are always 0. 
    91 // `ifdef CFG_ICACHE_ENABLED
    92 // `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
    93 // `else
    94 // `ifdef CFG_IWB_ENABLED
    95 `define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
    96 // `else
    97 // `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
    98 // `endif
    99 // `endif
   100 `define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
   102 // Range of an instruction
   103 `define LM32_INSTRUCTION_WIDTH          32
   104 `define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
   106 // Adder operation
   107 `define LM32_ADDER_OP_ADD               1'b0
   108 `define LM32_ADDER_OP_SUBTRACT          1'b1
   110 // Shift direction
   111 `define LM32_SHIFT_OP_RIGHT             1'b0
   112 `define LM32_SHIFT_OP_LEFT              1'b1
   114 // Currently always enabled
   115 `define CFG_BUS_ERRORS_ENABLED
   117 // Derive macro that indicates whether we have single-stepping or not
   118 `ifdef CFG_ROM_DEBUG_ENABLED
   119 `define LM32_SINGLE_STEP_ENABLED
   120 `else
   121 `ifdef CFG_HW_DEBUG_ENABLED
   122 `define LM32_SINGLE_STEP_ENABLED
   123 `endif
   124 `endif
   126 // Derive macro that indicates whether JTAG interface is required
   127 `ifdef CFG_JTAG_UART_ENABLED
   128 `define LM32_JTAG_ENABLED
   129 `else
   130 `ifdef CFG_DEBUG_ENABLED
   131 `define LM32_JTAG_ENABLED
   132 `else
   133 `endif
   134 `endif
   136 // Derive macro that indicates whether we have a barrel-shifter or not
   137 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   138 `define LM32_BARREL_SHIFT_ENABLED
   139 `else // CFG_PL_BARREL_SHIFT_ENABLED
   140 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   141 `define LM32_BARREL_SHIFT_ENABLED
   142 `else
   143 `define LM32_NO_BARREL_SHIFT
   144 `endif
   145 `endif // CFG_PL_BARREL_SHIFT_ENABLED
   147 // Derive macro that indicates whether we have a multiplier or not
   148 `ifdef CFG_PL_MULTIPLY_ENABLED
   149 `define LM32_MULTIPLY_ENABLED
   150 `else
   151 `ifdef CFG_MC_MULTIPLY_ENABLED
   152 `define LM32_MULTIPLY_ENABLED
   153 `endif
   154 `endif
   156 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
   157 `ifdef CFG_MC_DIVIDE_ENABLED
   158 `define LM32_MC_ARITHMETIC_ENABLED
   159 `endif
   160 `ifdef CFG_MC_MULTIPLY_ENABLED
   161 `define LM32_MC_ARITHMETIC_ENABLED
   162 `endif
   163 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   164 `define LM32_MC_ARITHMETIC_ENABLED
   165 `endif
   167 // Derive macro that indicates if we are using an EBR register file
   168 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   169 `define LM32_EBR_REGISTER_FILE
   170 `endif
   171 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   172 `define LM32_EBR_REGISTER_FILE
   173 `endif
   175 // Revision number
   176 `define LM32_REVISION                   6'h02
   178 // Logical operations - Function encoded directly in instruction
   179 `define LM32_LOGIC_OP_RNG               3:0
   181 // Conditions for conditional branches
   182 `define LM32_CONDITION_WIDTH            3
   183 `define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
   184 `define LM32_CONDITION_E                3'b001
   185 `define LM32_CONDITION_G                3'b010
   186 `define LM32_CONDITION_GE               3'b011
   187 `define LM32_CONDITION_GEU              3'b100
   188 `define LM32_CONDITION_GU               3'b101
   189 `define LM32_CONDITION_NE               3'b111
   190 `define LM32_CONDITION_U1               3'b000
   191 `define LM32_CONDITION_U2               3'b110
   193 // Size of load or store instruction - Encoding corresponds to opcode
   194 `define LM32_SIZE_WIDTH                 2
   195 `define LM32_SIZE_RNG                   1:0
   196 `define LM32_SIZE_BYTE                  2'b00
   197 `define LM32_SIZE_HWORD                 2'b11
   198 `define LM32_SIZE_WORD                  2'b10
   199 `define LM32_ADDRESS_LSBS_WIDTH         2
   201 // Width and range of a CSR index
   202 `ifdef CFG_DEBUG_ENABLED
   203 `define LM32_CSR_WIDTH                  5
   204 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   205 `else
   206 `ifdef CFG_JTAG_ENABLED
   207 `define LM32_CSR_WIDTH                  4
   208 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   209 `else
   210 `define LM32_CSR_WIDTH                  3
   211 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   212 `endif
   213 `endif
   215 // CSR indices
   216 `define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
   217 `define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
   218 `define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
   219 `define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
   220 `define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
   221 `define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
   222 `define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
   223 `define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
   224 `ifdef CFG_DEBUG_ENABLED
   225 `define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
   226 `define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
   227 `endif
   228 `define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
   229 `ifdef CFG_JTAG_ENABLED
   230 `define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
   231 `define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
   232 `endif
   233 `ifdef CFG_DEBUG_ENABLED
   234 `define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
   235 `define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
   236 `define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
   237 `define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
   238 `define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
   239 `define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
   240 `define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
   241 `define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
   242 `endif 
   244 // Values for WPC CSR
   245 `define LM32_WPC_C_RNG                  1:0
   246 `define LM32_WPC_C_DISABLED             2'b00
   247 `define LM32_WPC_C_READ                 2'b01
   248 `define LM32_WPC_C_WRITE                2'b10
   249 `define LM32_WPC_C_READ_WRITE           2'b11
   251 // Exception IDs
   252 `define LM32_EID_WIDTH                  3
   253 `define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
   254 `define LM32_EID_RESET                  3'h0
   255 `define LM32_EID_BREAKPOINT             3'd1
   256 `define LM32_EID_INST_BUS_ERROR         3'h2
   257 `define LM32_EID_WATCHPOINT             3'd3
   258 `define LM32_EID_DATA_BUS_ERROR         3'h4
   259 `define LM32_EID_DIVIDE_BY_ZERO         3'h5
   260 `define LM32_EID_INTERRUPT              3'h6
   261 `define LM32_EID_SCALL                  3'h7
   263 // Pipeline result selection mux controls
   265 `define LM32_D_RESULT_SEL_0_RNG          0:0
   266 `define LM32_D_RESULT_SEL_0_REG_0        1'b0
   267 `define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
   269 `define LM32_D_RESULT_SEL_1_RNG          1:0
   270 `define LM32_D_RESULT_SEL_1_ZERO         2'b00
   271 `define LM32_D_RESULT_SEL_1_REG_1        2'b01
   272 `define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
   274 `define LM32_USER_OPCODE_WIDTH           11
   275 `define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
   277 // Derive a macro to indicate if either of the caches are implemented
   278 `ifdef CFG_ICACHE_ENABLED
   279 `define LM32_CACHE_ENABLED      
   280 `else
   281 `ifdef CFG_DCACHE_ENABLED
   282 `define LM32_CACHE_ENABLED
   283 `endif
   284 `endif
   286 /////////////////////////////////////////////////////
   287 // Interrupts
   288 /////////////////////////////////////////////////////
   290 // Always enable interrupts
   291 `define CFG_INTERRUPTS_ENABLED
   293 // Currently this is fixed to 32 and should not be changed
   294 `define CFG_INTERRUPTS                  32
   295 `define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
   296 `define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
   298 /////////////////////////////////////////////////////
   299 // General
   300 /////////////////////////////////////////////////////
   302 // Sub-word range types
   303 `define LM32_BYTE_WIDTH                 8
   304 `define LM32_BYTE_RNG                   7:0
   305 `define LM32_HWORD_WIDTH                16
   306 `define LM32_HWORD_RNG                  15:0
   308 // Word sub-byte indicies
   309 `define LM32_BYTE_0_RNG                  7:0
   310 `define LM32_BYTE_1_RNG                  15:8
   311 `define LM32_BYTE_2_RNG                  23:16
   312 `define LM32_BYTE_3_RNG                  31:24
   314 // Word sub-halfword indices
   315 `define LM32_HWORD_0_RNG                 15:0
   316 `define LM32_HWORD_1_RNG                 31:16
   318 // Use an asynchronous reset
   319 // To use a synchronous reset, define this macro as nothing
   320 `define CFG_RESET_SENSITIVITY or posedge rst_i
   322 // V.T. Srce
   323 `define SRCE
   325 // Whether to include context registers for debug exceptions
   326 // in addition to standard exception handling registers
   327 // Bizarre - Removing this increases LUT count!
   328 `define CFG_DEBUG_EXCEPTIONS_ENABLED
   330 // Wishbone defines 
   331 // Refer to Wishbone System-on-Chip Interconnection Architecture
   332 // These should probably be moved to a Wishbone common file
   334 // Wishbone cycle types
   335 `define LM32_CTYPE_WIDTH                3
   336 `define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
   337 `define LM32_CTYPE_CLASSIC              3'b000
   338 `define LM32_CTYPE_CONSTANT             3'b001
   339 `define LM32_CTYPE_INCREMENTING         3'b010
   340 `define LM32_CTYPE_END                  3'b111
   342 // Wishbone burst types
   343 `define LM32_BTYPE_WIDTH                2
   344 `define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
   345 `define LM32_BTYPE_LINEAR               2'b00
   346 `define LM32_BTYPE_4_BEAT               2'b01
   347 `define LM32_BTYPE_8_BEAT               2'b10
   348 `define LM32_BTYPE_16_BEAT              2'b11
   350 `endif