Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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6 // ------------------------------------------------------------------
7 //
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11 //
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14 // Open Source License Agreement.
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17 //
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21 // the use of formal verification methods.
22 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_jtag.v
40 // Title : JTAG interface
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : No Change
48 // =============================================================================
50 `include "lm32_include.v"
52 `ifdef CFG_JTAG_ENABLED
54 `define LM32_DP 3'b000
55 `define LM32_TX 3'b001
56 `define LM32_RX 3'b010
58 // LM32 Debug Protocol commands IDs
59 `define LM32_DP_RNG 3:0
60 `define LM32_DP_READ_MEMORY 4'b0001
61 `define LM32_DP_WRITE_MEMORY 4'b0010
62 `define LM32_DP_READ_SEQUENTIAL 4'b0011
63 `define LM32_DP_WRITE_SEQUENTIAL 4'b0100
64 `define LM32_DP_WRITE_CSR 4'b0101
65 `define LM32_DP_BREAK 4'b0110
66 `define LM32_DP_RESET 4'b0111
68 // States for FSM
69 `define LM32_JTAG_STATE_RNG 3:0
70 `define LM32_JTAG_STATE_READ_COMMAND 4'h0
71 `define LM32_JTAG_STATE_READ_BYTE_0 4'h1
72 `define LM32_JTAG_STATE_READ_BYTE_1 4'h2
73 `define LM32_JTAG_STATE_READ_BYTE_2 4'h3
74 `define LM32_JTAG_STATE_READ_BYTE_3 4'h4
75 `define LM32_JTAG_STATE_READ_BYTE_4 4'h5
76 `define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
77 `define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
78 `define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
80 /////////////////////////////////////////////////////
81 // Module interface
82 /////////////////////////////////////////////////////
84 module lm32_jtag (
85 // ----- Inputs -------
86 clk_i,
87 rst_i,
88 jtag_clk,
89 jtag_update,
90 jtag_reg_q,
91 jtag_reg_addr_q,
92 `ifdef CFG_JTAG_UART_ENABLED
93 csr,
94 csr_write_enable,
95 csr_write_data,
96 stall_x,
97 `endif
98 `ifdef CFG_HW_DEBUG_ENABLED
99 jtag_read_data,
100 jtag_access_complete,
101 `endif
102 `ifdef CFG_DEBUG_ENABLED
103 exception_q_w,
104 `endif
105 // ----- Outputs -------
106 `ifdef CFG_JTAG_UART_ENABLED
107 jtx_csr_read_data,
108 jrx_csr_read_data,
109 `endif
110 `ifdef CFG_HW_DEBUG_ENABLED
111 jtag_csr_write_enable,
112 jtag_csr_write_data,
113 jtag_csr,
114 jtag_read_enable,
115 jtag_write_enable,
116 jtag_write_data,
117 jtag_address,
118 `endif
119 `ifdef CFG_DEBUG_ENABLED
120 jtag_break,
121 jtag_reset,
122 `endif
123 jtag_reg_d,
124 jtag_reg_addr_d
125 );
127 parameter lat_family = `LATTICE_FAMILY;
129 /////////////////////////////////////////////////////
130 // Inputs
131 /////////////////////////////////////////////////////
133 input clk_i; // Clock
134 input rst_i; // Reset
136 input jtag_clk; // JTAG clock
137 input jtag_update; // JTAG data register has been updated
138 input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
139 input [2:0] jtag_reg_addr_q; // JTAG data register
141 `ifdef CFG_JTAG_UART_ENABLED
142 input [`LM32_CSR_RNG] csr; // CSR to write
143 input csr_write_enable; // CSR write enable
144 input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
145 input stall_x; // Stall instruction in X stage
146 `endif
147 `ifdef CFG_HW_DEBUG_ENABLED
148 input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
149 input jtag_access_complete; // Memory access if complete
150 `endif
151 `ifdef CFG_DEBUG_ENABLED
152 input exception_q_w; // Indicates an exception has occured in W stage
153 `endif
155 /////////////////////////////////////////////////////
156 // Outputs
157 /////////////////////////////////////////////////////
159 `ifdef CFG_JTAG_UART_ENABLED
160 output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
161 wire [`LM32_WORD_RNG] jtx_csr_read_data;
162 output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
163 wire [`LM32_WORD_RNG] jrx_csr_read_data;
164 `endif
165 `ifdef CFG_HW_DEBUG_ENABLED
166 output jtag_csr_write_enable; // CSR write enable
167 reg jtag_csr_write_enable;
168 output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
169 wire [`LM32_WORD_RNG] jtag_csr_write_data;
170 output [`LM32_CSR_RNG] jtag_csr; // CSR to write
171 wire [`LM32_CSR_RNG] jtag_csr;
172 output jtag_read_enable; // Memory read enable
173 reg jtag_read_enable;
174 output jtag_write_enable; // Memory write enable
175 reg jtag_write_enable;
176 output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
177 wire [`LM32_BYTE_RNG] jtag_write_data;
178 output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
179 wire [`LM32_WORD_RNG] jtag_address;
180 `endif
181 `ifdef CFG_DEBUG_ENABLED
182 output jtag_break; // Request to raise a breakpoint exception
183 reg jtag_break;
184 output jtag_reset; // Request to raise a reset exception
185 reg jtag_reset;
186 `endif
187 output [`LM32_BYTE_RNG] jtag_reg_d;
188 reg [`LM32_BYTE_RNG] jtag_reg_d;
189 output [2:0] jtag_reg_addr_d;
190 wire [2:0] jtag_reg_addr_d;
192 /////////////////////////////////////////////////////
193 // Internal nets and registers
194 /////////////////////////////////////////////////////
196 reg rx_toggle; // Clock-domain crossing registers
197 reg rx_toggle_r; // Registered version of rx_toggle
198 reg rx_toggle_r_r; // Registered version of rx_toggle_r
199 reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
201 reg [`LM32_BYTE_RNG] rx_byte;
202 reg [2:0] rx_addr;
204 `ifdef CFG_JTAG_UART_ENABLED
205 reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
206 reg uart_tx_valid; // TX data is valid
207 reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
208 reg uart_rx_valid; // RX data is valid
209 `endif
211 reg [`LM32_DP_RNG] command; // The last received command
212 `ifdef CFG_HW_DEBUG_ENABLED
213 reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
214 reg [`LM32_BYTE_RNG] jtag_byte_1;
215 reg [`LM32_BYTE_RNG] jtag_byte_2;
216 reg [`LM32_BYTE_RNG] jtag_byte_3;
217 reg [`LM32_BYTE_RNG] jtag_byte_4;
218 reg processing; // Indicates if we're still processing a memory read/write
219 `endif
221 reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
223 /////////////////////////////////////////////////////
224 // Combinational Logic
225 /////////////////////////////////////////////////////
227 `ifdef CFG_HW_DEBUG_ENABLED
228 assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
229 assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
230 assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
231 assign jtag_write_data = jtag_byte_4;
232 `endif
234 // Generate status flags for reading via the JTAG interface
235 `ifdef CFG_JTAG_UART_ENABLED
236 assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
237 `else
238 assign jtag_reg_addr_d[1:0] = 2'b00;
239 `endif
240 `ifdef CFG_HW_DEBUG_ENABLED
241 assign jtag_reg_addr_d[2] = processing;
242 `else
243 assign jtag_reg_addr_d[2] = 1'b0;
244 `endif
246 `ifdef CFG_JTAG_UART_ENABLED
247 assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
248 assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
249 `endif
251 /////////////////////////////////////////////////////
252 // Sequential Logic
253 /////////////////////////////////////////////////////
255 // Toggle a flag when a JTAG write occurs
257 always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
258 begin
259 if (rst_i == `TRUE)
260 rx_toggle <= 1'b0;
261 else
262 rx_toggle <= ~rx_toggle;
263 end
265 always @(*)
266 begin
267 rx_byte = jtag_reg_q;
268 rx_addr = jtag_reg_addr_q;
269 end
271 // Clock domain crossing from JTAG clock domain to CPU clock domain
272 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
273 begin
274 if (rst_i == `TRUE)
275 begin
276 rx_toggle_r <= 1'b0;
277 rx_toggle_r_r <= 1'b0;
278 rx_toggle_r_r_r <= 1'b0;
279 end
280 else
281 begin
282 rx_toggle_r <= rx_toggle;
283 rx_toggle_r_r <= rx_toggle_r;
284 rx_toggle_r_r_r <= rx_toggle_r_r;
285 end
286 end
288 // LM32 debug protocol state machine
289 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
290 begin
291 if (rst_i == `TRUE)
292 begin
293 state <= `LM32_JTAG_STATE_READ_COMMAND;
294 command <= 4'b0000;
295 jtag_reg_d <= 8'h00;
296 `ifdef CFG_HW_DEBUG_ENABLED
297 processing <= `FALSE;
298 jtag_csr_write_enable <= `FALSE;
299 jtag_read_enable <= `FALSE;
300 jtag_write_enable <= `FALSE;
301 `endif
302 `ifdef CFG_DEBUG_ENABLED
303 jtag_break <= `FALSE;
304 jtag_reset <= `FALSE;
305 `endif
306 `ifdef CFG_JTAG_UART_ENABLED
307 uart_tx_byte <= 8'h00;
308 uart_tx_valid <= `FALSE;
309 uart_rx_byte <= 8'h00;
310 uart_rx_valid <= `FALSE;
311 `endif
312 end
313 else
314 begin
315 `ifdef CFG_JTAG_UART_ENABLED
316 if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
317 begin
318 case (csr)
319 `LM32_CSR_JTX:
320 begin
321 // Set flag indicating data is available
322 uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
323 uart_tx_valid <= `TRUE;
324 end
325 `LM32_CSR_JRX:
326 begin
327 // Clear flag indidicating data has been received
328 uart_rx_valid <= `FALSE;
329 end
330 endcase
331 end
332 `endif
333 `ifdef CFG_DEBUG_ENABLED
334 // When an exception has occured, clear the requests
335 if (exception_q_w == `TRUE)
336 begin
337 jtag_break <= `FALSE;
338 jtag_reset <= `FALSE;
339 end
340 `endif
341 case (state)
342 `LM32_JTAG_STATE_READ_COMMAND:
343 begin
344 // Wait for rx register to toggle which indicates new data is available
345 if (rx_toggle_r_r != rx_toggle_r_r_r)
346 begin
347 command <= rx_byte[7:4];
348 case (rx_addr)
349 `ifdef CFG_DEBUG_ENABLED
350 `LM32_DP:
351 begin
352 case (rx_byte[7:4])
353 `ifdef CFG_HW_DEBUG_ENABLED
354 `LM32_DP_READ_MEMORY:
355 state <= `LM32_JTAG_STATE_READ_BYTE_0;
356 `LM32_DP_READ_SEQUENTIAL:
357 begin
358 {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
359 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
360 end
361 `LM32_DP_WRITE_MEMORY:
362 state <= `LM32_JTAG_STATE_READ_BYTE_0;
363 `LM32_DP_WRITE_SEQUENTIAL:
364 begin
365 {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
366 state <= 5;
367 end
368 `LM32_DP_WRITE_CSR:
369 state <= `LM32_JTAG_STATE_READ_BYTE_0;
370 `endif
371 `LM32_DP_BREAK:
372 begin
373 `ifdef CFG_JTAG_UART_ENABLED
374 uart_rx_valid <= `FALSE;
375 uart_tx_valid <= `FALSE;
376 `endif
377 jtag_break <= `TRUE;
378 end
379 `LM32_DP_RESET:
380 begin
381 `ifdef CFG_JTAG_UART_ENABLED
382 uart_rx_valid <= `FALSE;
383 uart_tx_valid <= `FALSE;
384 `endif
385 jtag_reset <= `TRUE;
386 end
387 endcase
388 end
389 `endif
390 `ifdef CFG_JTAG_UART_ENABLED
391 `LM32_TX:
392 begin
393 uart_rx_byte <= rx_byte;
394 uart_rx_valid <= `TRUE;
395 end
396 `LM32_RX:
397 begin
398 jtag_reg_d <= uart_tx_byte;
399 uart_tx_valid <= `FALSE;
400 end
401 `endif
402 default:
403 ;
404 endcase
405 end
406 end
407 `ifdef CFG_HW_DEBUG_ENABLED
408 `LM32_JTAG_STATE_READ_BYTE_0:
409 begin
410 if (rx_toggle_r_r != rx_toggle_r_r_r)
411 begin
412 jtag_byte_0 <= rx_byte;
413 state <= `LM32_JTAG_STATE_READ_BYTE_1;
414 end
415 end
416 `LM32_JTAG_STATE_READ_BYTE_1:
417 begin
418 if (rx_toggle_r_r != rx_toggle_r_r_r)
419 begin
420 jtag_byte_1 <= rx_byte;
421 state <= `LM32_JTAG_STATE_READ_BYTE_2;
422 end
423 end
424 `LM32_JTAG_STATE_READ_BYTE_2:
425 begin
426 if (rx_toggle_r_r != rx_toggle_r_r_r)
427 begin
428 jtag_byte_2 <= rx_byte;
429 state <= `LM32_JTAG_STATE_READ_BYTE_3;
430 end
431 end
432 `LM32_JTAG_STATE_READ_BYTE_3:
433 begin
434 if (rx_toggle_r_r != rx_toggle_r_r_r)
435 begin
436 jtag_byte_3 <= rx_byte;
437 if (command == `LM32_DP_READ_MEMORY)
438 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
439 else
440 state <= `LM32_JTAG_STATE_READ_BYTE_4;
441 end
442 end
443 `LM32_JTAG_STATE_READ_BYTE_4:
444 begin
445 if (rx_toggle_r_r != rx_toggle_r_r_r)
446 begin
447 jtag_byte_4 <= rx_byte;
448 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
449 end
450 end
451 `LM32_JTAG_STATE_PROCESS_COMMAND:
452 begin
453 case (command)
454 `LM32_DP_READ_MEMORY,
455 `LM32_DP_READ_SEQUENTIAL:
456 begin
457 jtag_read_enable <= `TRUE;
458 processing <= `TRUE;
459 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
460 end
461 `LM32_DP_WRITE_MEMORY,
462 `LM32_DP_WRITE_SEQUENTIAL:
463 begin
464 jtag_write_enable <= `TRUE;
465 processing <= `TRUE;
466 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
467 end
468 `LM32_DP_WRITE_CSR:
469 begin
470 jtag_csr_write_enable <= `TRUE;
471 processing <= `TRUE;
472 state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
473 end
474 endcase
475 end
476 `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
477 begin
478 if (jtag_access_complete == `TRUE)
479 begin
480 jtag_read_enable <= `FALSE;
481 jtag_reg_d <= jtag_read_data;
482 jtag_write_enable <= `FALSE;
483 processing <= `FALSE;
484 state <= `LM32_JTAG_STATE_READ_COMMAND;
485 end
486 end
487 `LM32_JTAG_STATE_WAIT_FOR_CSR:
488 begin
489 jtag_csr_write_enable <= `FALSE;
490 processing <= `FALSE;
491 state <= `LM32_JTAG_STATE_READ_COMMAND;
492 end
493 `endif
494 endcase
495 end
496 end
498 endmodule
500 `endif