lm32_load_store_unit.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
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     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
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    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
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    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project      : LatticeMico32
    39 // File         : lm32_load_store_unit.v
    40 // Title        : Load and store unit
    41 // Dependencies : lm32_include.v
    42 // Version      : 6.1.17
    43 //              : Initial Release
    44 // Version      : 7.0SP2, 3.0
    45 //              : No Change
    46 // Version      : 3.1
    47 //              : Instead of disallowing an instruction cache miss on a data cache 
    48 //              : miss, both can now occur at the same time. If both occur at same 
    49 //              : time, then restart address is the address of instruction that 
    50 //              : caused data cache miss.
    51 // Version      : 3.2
    52 //              : EBRs use SYNC resets instead of ASYNC resets.
    53 // Version      : 3.3
    54 //              : Support for new non-cacheable Data Memory that is accessible by 
    55 //              : the data port and has a one cycle access latency.
    56 // Version      : 3.4
    57 //              : No change
    58 // Version      : 3.5
    59 //              : Bug fix: Inline memory is correctly generated if it is not a
    60 //              : power-of-two
    61 // =============================================================================
    63 `include "lm32_include.v"
    65 /////////////////////////////////////////////////////
    66 // Module interface
    67 /////////////////////////////////////////////////////
    69 module lm32_load_store_unit (
    70     // ----- Inputs -------
    71     clk_i,
    72     rst_i,
    73     // From pipeline
    74     stall_a,
    75     stall_x,
    76     stall_m,
    77     kill_m,
    78     exception_m,
    79     store_operand_x,
    80     load_store_address_x,
    81     load_store_address_m,
    82     load_store_address_w,
    83     load_x,
    84     store_x,
    85     load_q_x,
    86     store_q_x,
    87     load_q_m,
    88     store_q_m,
    89     sign_extend_x,
    90     size_x,
    91 `ifdef CFG_DCACHE_ENABLED
    92     dflush,
    93 `endif
    94 `ifdef CFG_IROM_ENABLED
    95     irom_data_m,
    96 `endif
    97     // From Wishbone
    98     d_dat_i,
    99     d_ack_i,
   100     d_err_i,
   101     d_rty_i,
   102     // ----- Outputs -------
   103     // To pipeline
   104 `ifdef CFG_DCACHE_ENABLED
   105     dcache_refill_request,
   106     dcache_restart_request,
   107     dcache_stall_request,
   108     dcache_refilling,
   109 `endif    
   110 `ifdef CFG_IROM_ENABLED
   111     irom_store_data_m,
   112     irom_address_xm,
   113     irom_we_xm,
   114     irom_stall_request_x,
   115 `endif			     
   116     load_data_w,
   117     stall_wb_load,
   118     // To Wishbone
   119     d_dat_o,
   120     d_adr_o,
   121     d_cyc_o,
   122     d_sel_o,
   123     d_stb_o,
   124     d_we_o,
   125     d_cti_o,
   126     d_lock_o,
   127     d_bte_o
   128     );
   130 /////////////////////////////////////////////////////
   131 // Parameters
   132 /////////////////////////////////////////////////////
   134 parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   135 parameter sets = 512;                                   // Number of sets
   136 parameter bytes_per_line = 16;                          // Number of bytes per cache line
   137 parameter base_address = 0;                             // Base address of cachable memory
   138 parameter limit = 0;                                    // Limit (highest address) of cachable memory
   140 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
   141 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
   142 localparam addr_offset_lsb = 2;
   143 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
   145 /////////////////////////////////////////////////////
   146 // Inputs
   147 /////////////////////////////////////////////////////
   149 input clk_i;                                            // Clock 
   150 input rst_i;                                            // Reset
   152 input stall_a;                                          // A stage stall 
   153 input stall_x;                                          // X stage stall        
   154 input stall_m;                                          // M stage stall
   155 input kill_m;                                           // Kill instruction in M stage
   156 input exception_m;                                      // An exception occured in the M stage
   158 input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
   159 input [`LM32_WORD_RNG] load_store_address_x;            // X stage load/store address
   160 input [`LM32_WORD_RNG] load_store_address_m;            // M stage load/store address
   161 input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
   162 input load_x;                                           // Load instruction in X stage
   163 input store_x;                                          // Store instruction in X stage
   164 input load_q_x;                                         // Load instruction in X stage
   165 input store_q_x;                                        // Store instruction in X stage
   166 input load_q_m;                                         // Load instruction in M stage
   167 input store_q_m;                                        // Store instruction in M stage
   168 input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
   169 input [`LM32_SIZE_RNG] size_x;                          // Size of load or store (byte, hword, word)
   171 `ifdef CFG_DCACHE_ENABLED
   172 input dflush;                                           // Flush the data cache
   173 `endif
   175 `ifdef CFG_IROM_ENABLED   
   176 input [`LM32_WORD_RNG] irom_data_m;                     // Data from Instruction-ROM
   177 `endif
   179 input [`LM32_WORD_RNG] d_dat_i;                         // Data Wishbone interface read data
   180 input d_ack_i;                                          // Data Wishbone interface acknowledgement
   181 input d_err_i;                                          // Data Wishbone interface error
   182 input d_rty_i;                                          // Data Wishbone interface retry
   184 /////////////////////////////////////////////////////
   185 // Outputs
   186 /////////////////////////////////////////////////////
   188 `ifdef CFG_DCACHE_ENABLED
   189 output dcache_refill_request;                           // Request to refill data cache
   190 wire   dcache_refill_request;
   191 output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
   192 wire   dcache_restart_request;
   193 output dcache_stall_request;                            // Data cache stall request
   194 wire   dcache_stall_request;
   195 output dcache_refilling;
   196 wire   dcache_refilling;
   197 `endif
   199 `ifdef CFG_IROM_ENABLED   
   200 output irom_store_data_m;                               // Store data to Instruction ROM
   201 wire   [`LM32_WORD_RNG] irom_store_data_m;
   202 output [`LM32_WORD_RNG] irom_address_xm;                // Load/store address to Instruction ROM
   203 wire   [`LM32_WORD_RNG] irom_address_xm;
   204 output irom_we_xm;                                      // Write-enable of 2nd port of Instruction ROM
   205 wire   irom_we_xm;
   206 output irom_stall_request_x;                            // Stall instruction in D stage  
   207 wire   irom_stall_request_x;                            
   208 `endif
   210 output [`LM32_WORD_RNG] load_data_w;                    // Result of a load instruction
   211 reg    [`LM32_WORD_RNG] load_data_w;
   212 output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
   213 reg    stall_wb_load;
   215 output [`LM32_WORD_RNG] d_dat_o;                        // Data Wishbone interface write data
   216 reg    [`LM32_WORD_RNG] d_dat_o;
   217 output [`LM32_WORD_RNG] d_adr_o;                        // Data Wishbone interface address
   218 reg    [`LM32_WORD_RNG] d_adr_o;
   219 output d_cyc_o;                                         // Data Wishbone interface cycle
   220 reg    d_cyc_o;
   221 output [`LM32_BYTE_SELECT_RNG] d_sel_o;                 // Data Wishbone interface byte select
   222 reg    [`LM32_BYTE_SELECT_RNG] d_sel_o;
   223 output d_stb_o;                                         // Data Wishbone interface strobe
   224 reg    d_stb_o; 
   225 output d_we_o;                                          // Data Wishbone interface write enable
   226 reg    d_we_o;
   227 output [`LM32_CTYPE_RNG] d_cti_o;                       // Data Wishbone interface cycle type 
   228 reg    [`LM32_CTYPE_RNG] d_cti_o;
   229 output d_lock_o;                                        // Date Wishbone interface lock bus
   230 reg    d_lock_o;
   231 output [`LM32_BTYPE_RNG] d_bte_o;                       // Data Wishbone interface burst type 
   232 wire   [`LM32_BTYPE_RNG] d_bte_o;
   234 /////////////////////////////////////////////////////
   235 // Internal nets and registers 
   236 /////////////////////////////////////////////////////
   238 // Microcode pipeline registers - See inputs for description
   239 reg [`LM32_SIZE_RNG] size_m;
   240 reg [`LM32_SIZE_RNG] size_w;
   241 reg sign_extend_m;
   242 reg sign_extend_w;
   243 reg [`LM32_WORD_RNG] store_data_x;       
   244 reg [`LM32_WORD_RNG] store_data_m;       
   245 reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
   246 reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
   247 wire [`LM32_WORD_RNG] data_m;
   248 reg [`LM32_WORD_RNG] data_w;
   250 `ifdef CFG_DCACHE_ENABLED
   251 wire dcache_select_x;                                   // Select data cache to load from / store to
   252 reg dcache_select_m;
   253 wire [`LM32_WORD_RNG] dcache_data_m;                    // Data read from cache
   254 wire [`LM32_WORD_RNG] dcache_refill_address;            // Address to refill data cache from
   255 reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
   256 wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
   257 wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
   258 wire last_word;                                         // Indicates if this is the last word in the cache line
   259 wire [`LM32_WORD_RNG] first_address;                    // First cache refill address
   260 `endif
   261 `ifdef CFG_DRAM_ENABLED
   262 wire dram_select_x;                                     // Select data RAM to load from / store to
   263 reg dram_select_m;
   264 reg dram_bypass_en;                                     // RAW in data RAM; read latched (bypass) value rather than value from memory
   265 reg [`LM32_WORD_RNG] dram_bypass_data;                  // Latched value of store'd data to data RAM
   266 wire [`LM32_WORD_RNG] dram_data_out;                    // Data read from data RAM
   267 wire [`LM32_WORD_RNG] dram_data_m;                      // Data read from data RAM: bypass value or value from memory
   268 wire [`LM32_WORD_RNG] dram_store_data_m;                // Data to write to RAM
   269 `endif
   270 wire wb_select_x;                                       // Select Wishbone to load from / store to
   271 `ifdef CFG_IROM_ENABLED
   272 wire irom_select_x;                                     // Select instruction ROM to load from / store to
   273 reg  irom_select_m;
   274 `endif
   275 reg wb_select_m;
   276 reg [`LM32_WORD_RNG] wb_data_m;                         // Data read from Wishbone
   277 reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
   279 /////////////////////////////////////////////////////
   280 // Functions
   281 /////////////////////////////////////////////////////
   283 `include "lm32_functions.v"
   285 /////////////////////////////////////////////////////
   286 // Instantiations
   287 /////////////////////////////////////////////////////
   289 `ifdef CFG_DRAM_ENABLED
   290    // Data RAM
   291    pmi_ram_dp_true 
   292      #(
   293        // ----- Parameters -------
   294        .pmi_family             (`LATTICE_FAMILY),
   296        //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   297        //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   298        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
   299        //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   300        //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   301        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
   303        .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
   304        .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
   305        .pmi_data_width_a       (`LM32_WORD_WIDTH),
   306        .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
   307        .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
   308        .pmi_data_width_b       (`LM32_WORD_WIDTH),
   310        .pmi_regmode_a          ("noreg"),
   311        .pmi_regmode_b          ("noreg"),
   312        .pmi_gsr                ("enable"),
   313        .pmi_resetmode          ("sync"),
   314        .pmi_init_file          (`CFG_DRAM_INIT_FILE),
   315        .pmi_init_file_format   (`CFG_DRAM_INIT_FILE_FORMAT),
   316        .module_type            ("pmi_ram_dp_true")
   317        ) 
   318        ram (
   319 	    // ----- Inputs -------
   320 	    .ClockA                 (clk_i),
   321 	    .ClockB                 (clk_i),
   322 	    .ResetA                 (rst_i),
   323 	    .ResetB                 (rst_i),
   324 	    .DataInA                ({32{1'b0}}),
   325 	    .DataInB                (dram_store_data_m),
   326 	    .AddressA               (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
   327 	    .AddressB               (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
   328 	    // .ClockEnA               (!stall_x & (load_x | store_x)),
   329 	    .ClockEnA               (!stall_x),
   330 	    .ClockEnB               (!stall_m),
   331 	    .WrA                    (`FALSE),
   332 	    .WrB                    (store_q_m & dram_select_m), 
   333 	    // ----- Outputs -------
   334 	    .QA                     (dram_data_out),
   335 	    .QB                     ()
   336 	    );
   338    /*----------------------------------------------------------------------
   339     EBRs cannot perform reads from location 'written to' on the same clock
   340     edge. Therefore bypass logic is required to latch the store'd value
   341     and use it for the load (instead of value from memory).
   342     ----------------------------------------------------------------------*/
   343    always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   344      if (rst_i == `TRUE)
   345        begin
   346 	  dram_bypass_en <= `FALSE;
   347 	  dram_bypass_data <= 0;
   348        end
   349      else
   350        begin
   351 	  if (stall_x == `FALSE)
   352 	    dram_bypass_data <= dram_store_data_m;
   354 	  if (   (stall_m == `FALSE) 
   355               && (stall_x == `FALSE)
   356 	      && (store_q_m == `TRUE)
   357 	      && (   (load_x == `TRUE)
   358 	          || (store_x == `TRUE)
   359 		 )
   360 	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
   361 	     )
   362 	    dram_bypass_en <= `TRUE;
   363 	  else
   364 	    if (   (dram_bypass_en == `TRUE)
   365 		&& (stall_x == `FALSE)
   366 	       )
   367 	      dram_bypass_en <= `FALSE;
   368        end
   370    assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
   371 `endif
   373 `ifdef CFG_DCACHE_ENABLED
   374 // Data cache
   375 lm32_dcache #(
   376     .associativity          (associativity),
   377     .sets                   (sets),
   378     .bytes_per_line         (bytes_per_line),
   379     .base_address           (base_address),
   380     .limit                  (limit)
   381     ) dcache ( 
   382     // ----- Inputs -----
   383     .clk_i                  (clk_i),
   384     .rst_i                  (rst_i),      
   385     .stall_a                (stall_a),
   386     .stall_x                (stall_x),
   387     .stall_m                (stall_m),
   388     .address_x              (load_store_address_x),
   389     .address_m              (load_store_address_m),
   390     .load_q_m               (load_q_m & dcache_select_m),
   391     .store_q_m              (store_q_m & dcache_select_m),
   392     .store_data             (store_data_m),
   393     .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
   394     .refill_ready           (dcache_refill_ready),
   395     .refill_data            (wb_data_m),
   396     .dflush                 (dflush),
   397     // ----- Outputs -----
   398     .stall_request          (dcache_stall_request),
   399     .restart_request        (dcache_restart_request),
   400     .refill_request         (dcache_refill_request),
   401     .refill_address         (dcache_refill_address),
   402     .refilling              (dcache_refilling),
   403     .load_data              (dcache_data_m)
   404     );
   405 `endif
   407 /////////////////////////////////////////////////////
   408 // Combinational Logic
   409 /////////////////////////////////////////////////////
   411 // Select where data should be loaded from / stored to
   412 `ifdef CFG_DRAM_ENABLED
   413    assign dram_select_x =    (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 
   414                           && (load_store_address_x <= `CFG_DRAM_LIMIT);
   415 `endif
   417 `ifdef CFG_IROM_ENABLED
   418    assign irom_select_x =    (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 
   419                           && (load_store_address_x <= `CFG_IROM_LIMIT);
   420 `endif
   422 `ifdef CFG_DCACHE_ENABLED
   423    assign dcache_select_x =    (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 
   424                             && (load_store_address_x <= `CFG_DCACHE_LIMIT)
   425 `ifdef CFG_DRAM_ENABLED
   426                             && (dram_select_x == `FALSE)
   427 `endif
   428 `ifdef CFG_IROM_ENABLED
   429                             && (irom_select_x == `FALSE)
   430 `endif
   431                      ;
   432 `endif
   434    assign wb_select_x =    `TRUE
   435 `ifdef CFG_DCACHE_ENABLED
   436                         && !dcache_select_x 
   437 `endif
   438 `ifdef CFG_DRAM_ENABLED
   439                         && !dram_select_x
   440 `endif
   441 `ifdef CFG_IROM_ENABLED
   442                         && !irom_select_x
   443 `endif
   444                      ;
   446 // Make sure data to store is in correct byte lane
   447 always @(*)
   448 begin
   449     case (size_x)
   450     `LM32_SIZE_BYTE:  store_data_x = {4{store_operand_x[7:0]}};
   451     `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
   452     `LM32_SIZE_WORD:  store_data_x = store_operand_x;    
   453     default:          store_data_x = {`LM32_WORD_WIDTH{1'bx}};
   454     endcase
   455 end
   457 // Generate byte enable accoring to size of load or store and address being accessed
   458 always @(*)
   459 begin
   460     casez ({size_x, load_store_address_x[1:0]})
   461     {`LM32_SIZE_BYTE, 2'b11}:  byte_enable_x = 4'b0001;
   462     {`LM32_SIZE_BYTE, 2'b10}:  byte_enable_x = 4'b0010;
   463     {`LM32_SIZE_BYTE, 2'b01}:  byte_enable_x = 4'b0100;
   464     {`LM32_SIZE_BYTE, 2'b00}:  byte_enable_x = 4'b1000;
   465     {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
   466     {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
   467     {`LM32_SIZE_WORD, 2'b??}:  byte_enable_x = 4'b1111;
   468     default:                   byte_enable_x = 4'bxxxx;
   469     endcase
   470 end
   472 `ifdef CFG_DRAM_ENABLED
   473 // Only replace selected bytes
   474 assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
   475 assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
   476 assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
   477 assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
   478 `endif
   480 `ifdef CFG_IROM_ENABLED
   481 // Only replace selected bytes
   482 assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
   483 assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
   484 assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
   485 assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
   486 `endif
   488 `ifdef CFG_IROM_ENABLED
   489    // Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
   490    // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
   491    // byte is replaced, and the whole 32-bit value is written back
   493    assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
   494 	                    ? load_store_address_m
   495 	                    : load_store_address_x;
   497    // All store instructions perform a write operation in the M stage
   498    assign irom_we_xm =    (irom_select_m == `TRUE)
   499 	               && (store_q_m == `TRUE);
   501    // A single port in instruction ROM is available to load-store unit for doing loads/stores.
   502    // Since every store requires a load (in X stage) and then a store (in M stage), we cannot
   503    // allow load (or store) instructions sequentially after the store instructions to proceed 
   504    // until the store instruction has vacated M stage (i.e., completed the store operation)
   505    assign irom_stall_request_x =    (irom_select_x == `TRUE)
   506 	                         && (store_q_x == `TRUE);
   507 `endif
   509 `ifdef CFG_DCACHE_ENABLED
   510  `ifdef CFG_DRAM_ENABLED
   511   `ifdef CFG_IROM_ENABLED
   512    // WB + DC + DRAM + IROM
   513    assign data_m = wb_select_m == `TRUE 
   514                    ? wb_data_m
   515                    : dram_select_m == `TRUE 
   516                      ? dram_data_m
   517                      : irom_select_m == `TRUE
   518                        ? irom_data_m 
   519                        : dcache_data_m;
   520   `else
   521    // WB + DC + DRAM
   522    assign data_m = wb_select_m == `TRUE 
   523                    ? wb_data_m
   524                    : dram_select_m == `TRUE 
   525                      ? dram_data_m
   526                      : dcache_data_m;
   527   `endif
   528  `else
   529   `ifdef CFG_IROM_ENABLED
   530    // WB + DC + IROM
   531    assign data_m = wb_select_m == `TRUE 
   532                    ? wb_data_m
   533                    : irom_select_m == `TRUE 
   534                      ? irom_data_m
   535                      : dcache_data_m;
   536   `else
   537    // WB + DC
   538    assign data_m = wb_select_m == `TRUE 
   539                    ? wb_data_m 
   540                    : dcache_data_m;
   541   `endif
   542  `endif
   543 `else
   544  `ifdef CFG_DRAM_ENABLED
   545   `ifdef CFG_IROM_ENABLED
   546    // WB + DRAM + IROM
   547    assign data_m = wb_select_m == `TRUE 
   548                    ? wb_data_m 
   549                    : dram_select_m == `TRUE
   550                      ? dram_data_m
   551                      : irom_data_m;
   552   `else
   553    // WB + DRAM
   554    assign data_m = wb_select_m == `TRUE 
   555                    ? wb_data_m 
   556                    : dram_data_m;
   557   `endif
   558  `else
   559   `ifdef CFG_IROM_ENABLED
   560    // WB + IROM
   561    assign data_m = wb_select_m == `TRUE 
   562                    ? wb_data_m 
   563                    : irom_data_m;
   564   `else
   565    // WB
   566    assign data_m = wb_data_m;
   567   `endif
   568  `endif
   569 `endif
   571 // Sub-word selection and sign/zero-extension for loads
   572 always @(*)
   573 begin
   574     casez ({size_w, load_store_address_w[1:0]})
   575     {`LM32_SIZE_BYTE, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
   576     {`LM32_SIZE_BYTE, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
   577     {`LM32_SIZE_BYTE, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
   578     {`LM32_SIZE_BYTE, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
   579     {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
   580     {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
   581     {`LM32_SIZE_WORD, 2'b??}:  load_data_w = data_w;
   582     default:                   load_data_w = {`LM32_WORD_WIDTH{1'bx}};
   583     endcase
   584 end
   586 // Unused/constant Wishbone signals
   587 assign d_bte_o = `LM32_BTYPE_LINEAR;
   589 `ifdef CFG_DCACHE_ENABLED                
   590 // Generate signal to indicate last word in cache line
   591 generate 
   592     case (bytes_per_line)
   593     4:
   594     begin
   595 assign first_cycle_type = `LM32_CTYPE_END;
   596 assign next_cycle_type = `LM32_CTYPE_END;
   597 assign last_word = `TRUE;
   598 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
   599     end
   600     8:
   601     begin
   602 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   603 assign next_cycle_type = `LM32_CTYPE_END;
   604 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
   605 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
   606     end
   607     16:
   608     begin
   609 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   610 assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
   611 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
   612 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
   613     end
   614     endcase
   615 endgenerate
   616 `endif
   618 /////////////////////////////////////////////////////
   619 // Sequential Logic
   620 /////////////////////////////////////////////////////
   622 // Data Wishbone interface
   623 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   624 begin
   625     if (rst_i == `TRUE)
   626     begin
   627         d_cyc_o <= `FALSE;
   628         d_stb_o <= `FALSE;
   629         d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
   630         d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   631         d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   632         d_we_o <= `FALSE;
   633         d_cti_o <= `LM32_CTYPE_END;
   634         d_lock_o <= `FALSE;
   635         wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   636         wb_load_complete <= `FALSE;
   637         stall_wb_load <= `FALSE;
   638 `ifdef CFG_DCACHE_ENABLED                
   639         dcache_refill_ready <= `FALSE;
   640 `endif                
   641     end
   642     else
   643     begin
   644 `ifdef CFG_DCACHE_ENABLED 
   645         // Refill ready should only be asserted for a single cycle               
   646         dcache_refill_ready <= `FALSE;
   647 `endif                
   648         // Is a Wishbone cycle already in progress?
   649         if (d_cyc_o == `TRUE)
   650         begin
   651             // Is the cycle complete?
   652             if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
   653             begin
   654 `ifdef CFG_DCACHE_ENABLED                
   655                 if ((dcache_refilling == `TRUE) && (!last_word))
   656                 begin
   657                     // Fetch next word of cache line    
   658                     d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   659                 end
   660                 else
   661 `endif                
   662                 begin
   663                     // Refill/access complete
   664                     d_cyc_o <= `FALSE;
   665                     d_stb_o <= `FALSE;
   666                     d_lock_o <= `FALSE;
   667                 end
   668 `ifdef CFG_DCACHE_ENABLED    
   669                 d_cti_o <= next_cycle_type;
   670                 // If we are performing a refill, indicate to cache next word of data is ready            
   671                 dcache_refill_ready <= dcache_refilling;
   672 `endif
   673                 // Register data read from Wishbone interface
   674                 wb_data_m <= d_dat_i;
   675                 // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   676                 wb_load_complete <= !d_we_o;
   677             end
   678             // synthesis translate_off            
   679             if (d_err_i == `TRUE)
   680                 $display ("Data bus error. Address: %x", d_adr_o);
   681             // synthesis translate_on
   682         end
   683         else
   684         begin
   685 `ifdef CFG_DCACHE_ENABLED                
   686             if (dcache_refill_request == `TRUE)
   687             begin
   688                 // Start cache refill
   689                 d_adr_o <= first_address;
   690                 d_cyc_o <= `TRUE;
   691                 d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   692                 d_stb_o <= `TRUE;                
   693                 d_we_o <= `FALSE;
   694                 d_cti_o <= first_cycle_type;
   695                 //d_lock_o <= `TRUE;
   696             end
   697             else 
   698 `endif            
   699                  if (   (store_q_m == `TRUE)
   700                      && (stall_m == `FALSE)
   701 `ifdef CFG_DRAM_ENABLED
   702                      && (dram_select_m == `FALSE)
   703 `endif
   704 `ifdef CFG_IROM_ENABLED
   705 		     && (irom_select_m == `FALSE)
   706 `endif			
   707                     )
   708             begin
   709                 // Data cache is write through, so all stores go to memory
   710                 d_dat_o <= store_data_m;
   711                 d_adr_o <= load_store_address_m;
   712                 d_cyc_o <= `TRUE;
   713                 d_sel_o <= byte_enable_m;
   714                 d_stb_o <= `TRUE;
   715                 d_we_o <= `TRUE;
   716                 d_cti_o <= `LM32_CTYPE_END;
   717             end        
   718             else if (   (load_q_m == `TRUE) 
   719                      && (wb_select_m == `TRUE) 
   720                      && (wb_load_complete == `FALSE)
   721                      // stall_m will be TRUE, because stall_wb_load will be TRUE 
   722                     )
   723             begin
   724                 // Read requested address
   725                 stall_wb_load <= `FALSE;
   726                 d_adr_o <= load_store_address_m;
   727                 d_cyc_o <= `TRUE;
   728                 d_sel_o <= byte_enable_m;
   729                 d_stb_o <= `TRUE;
   730                 d_we_o <= `FALSE;
   731                 d_cti_o <= `LM32_CTYPE_END;
   732             end
   733         end
   734         // Clear load/store complete flag when instruction leaves M stage
   735         if (stall_m == `FALSE)
   736             wb_load_complete <= `FALSE;
   737         // When a Wishbone load first enters the M stage, we need to stall it
   738         if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   739             stall_wb_load <= `TRUE;
   740         // Clear stall request if load instruction is killed
   741         if ((kill_m == `TRUE) || (exception_m == `TRUE))
   742             stall_wb_load <= `FALSE;
   743     end
   744 end
   746 // Pipeline registers  
   748 // X/M stage pipeline registers
   749 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   750 begin
   751     if (rst_i == `TRUE)
   752     begin
   753         sign_extend_m <= `FALSE;
   754         size_m <= 2'b00;
   755         byte_enable_m <= `FALSE;
   756         store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   757 `ifdef CFG_DCACHE_ENABLED
   758         dcache_select_m <= `FALSE;
   759 `endif
   760 `ifdef CFG_DRAM_ENABLED
   761         dram_select_m <= `FALSE;
   762 `endif
   763 `ifdef CFG_IROM_ENABLED
   764         irom_select_m <= `FALSE;
   765 `endif
   766         wb_select_m <= `FALSE;        
   767     end
   768     else
   769     begin
   770         if (stall_m == `FALSE)
   771         begin
   772             sign_extend_m <= sign_extend_x;
   773             size_m <= size_x;
   774             byte_enable_m <= byte_enable_x;    
   775             store_data_m <= store_data_x;
   776 `ifdef CFG_DCACHE_ENABLED
   777             dcache_select_m <= dcache_select_x;
   778 `endif
   779 `ifdef CFG_DRAM_ENABLED
   780             dram_select_m <= dram_select_x;
   781 `endif
   782 `ifdef CFG_IROM_ENABLED
   783             irom_select_m <= irom_select_x;
   784 `endif
   785             wb_select_m <= wb_select_x;
   786         end
   787     end
   788 end
   790 // M/W stage pipeline registers
   791 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   792 begin
   793     if (rst_i == `TRUE)
   794     begin
   795         size_w <= 2'b00;
   796         data_w <= {`LM32_WORD_WIDTH{1'b0}};
   797         sign_extend_w <= `FALSE;
   798     end
   799     else
   800     begin
   801         size_w <= size_m;
   802         data_w <= data_m;
   803         sign_extend_w <= sign_extend_m;
   804     end
   805 end
   807 /////////////////////////////////////////////////////
   808 // Behavioural Logic
   809 /////////////////////////////////////////////////////
   811 // synthesis translate_off
   813 // Check for non-aligned loads or stores
   814 always @(posedge clk_i)
   815 begin
   816     if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 
   817     begin
   818         if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
   819             $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
   820         if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
   821             $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
   822     end
   823 end
   825 // synthesis translate_on
   827 endmodule