spiprog.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
     6 //   ------------------------------------------------------------------
     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
    23 //   --------------------------------------------------------------------
    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
    27 //                  Hillsboro, OR 97214
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    29 //
    30 //                  TEL: 1-800-Lattice (USA and Canada)
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    32 //
    33 //                  web: http://www.latticesemi.com/
    34 //                  email: techsupport@latticesemi.com
    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : SPIPROG.v
    40 //   This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
    41 //   core.  There are only three ER2 registers, one control register and two
    42 //   data registers, in this IP core.  The control register is a 8-bit wide
    43 //   register for selecting which data register will be accessed when the
    44 //   Control/Data# bit in ER1 register is low.  Data register 0 is a readonly
    45 //   ID register.  It is composed of three register fields -- an 8-bit
    46 //   "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
    47 //   Data register 1 is a variable length register for sending commands to or
    48 //   receiving readback data from the SPI Serial FLASH device.
    49 // Dependencies     : None
    50 // Version          : 6.1.17
    51 //        1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
    52 //        2. Same as TYPEA and TYPEB modules, use falling edge clock
    53 //           for all TCK Flip-Flops.
    54 //        3. Added 7 delay Flip-Flops so that the DR1 readback data from 
    55 //           SPI Serial FLASH is in the byte boundary.
    56 // Version          : 7.0SP2, 3.0
    57 //                  : No Change
    58 // Version          : 3.1
    59 //                  : No Change
    60 // =============================================================================
    61 //---------------------------------------------------------------------------
    62 //
    63 //Name : SPIPROG.v
    64 //
    65 //Description:
    66 //
    67 //   This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
    68 //   core.  There are only three ER2 registers, one control register and two
    69 //   data registers, in this IP core.  The control register is a 8-bit wide
    70 //   register for selecting which data register will be accessed when the
    71 //   Control/Data# bit in ER1 register is low.  Data register 0 is a readonly
    72 //   ID register.  It is composed of three register fields -- an 8-bit
    73 //   "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
    74 //   Data register 1 is a variable length register for sending commands to or
    75 //   receiving readback data from the SPI Serial FLASH device.
    76 //
    77 //$Log: spiprog.vhd,v $
    78 //Revision 1.2  2004-09-09 11:43:26-07  jhsin
    79 //1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
    80 //2. Same as TYPEA and TYPEB modules, use falling edge clock
    81 //   for all TCK Flip-Flops.
    82 //
    83 //Revision 1.1  2004-08-12 13:22:05-07  jhsin
    84 //Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
    85 //
    86 //Revision 1.0  2004-08-03 18:35:56-07  jhsin
    87 //Initial revision
    88 //
    89 //
    91 module SPIPROG (input 	JTCK           ,
    92 		input 	JTDI           ,
    93 		output 	JTDO2          ,
    94 		input 	JSHIFT         ,
    95 		input 	JUPDATE        ,
    96 		input 	JRSTN          ,
    97 		input 	JCE2           ,
    98 		input 	SPIPROG_ENABLE ,
    99 		input 	CONTROL_DATAN  ,
   100 		output 	SPI_C          ,
   101 		output 	SPI_D          ,
   102 		output 	SPI_SN         ,
   103 		input 	SPI_Q);
   105    wire 		er2Cr_enable ;
   106    wire 		er2Dr0_enable;
   107    wire 		er2Dr1_enable;
   109    wire 		tdo_er2Cr ;
   110    wire 		tdo_er2Dr0;
   111    wire 		tdo_er2Dr1;
   113    wire [7:0] 		encodedDrSelBits ;
   114    wire [8:0] 		er2CrTdiBit      ;
   115    wire [8:0] 		er2Dr0TdiBit     ;
   117    wire 		captureDrER2;
   118    reg 			spi_s       ;
   119    reg [6:0] 		spi_q_dly;
   121    wire [7:0] 		ip_functionality_id;
   123    genvar 		i;
   125    //   ------ Control Register 0 ------
   127    assign 		er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
   129    assign 		tdo_er2Cr = er2CrTdiBit[0];
   131    //   CR_BIT0_BIT7 
   132    generate
   133       for(i=0; i<=7; i=i+1)
   134 	begin:CR_BIT0_BIT7
   135 	   TYPEA BIT_N (.CLK        (JTCK),
   136 			.RESET_N    (JRSTN),
   137 			.CLKEN      (er2Cr_enable),
   138 			.TDI        (er2CrTdiBit[i + 1]),
   139 			.TDO        (er2CrTdiBit[i]),
   140 			.DATA_OUT   (encodedDrSelBits[i]),
   141 			.DATA_IN    (encodedDrSelBits[i]),
   142 			.CAPTURE_DR (captureDrER2),
   143 			.UPDATE_DR  (JUPDATE));
   144 	end
   145    endgenerate // CR_BIT0_BIT7
   147    assign er2CrTdiBit[8] = JTDI;
   149 //   ------ Data Register 0 ------
   150    assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
   152    assign tdo_er2Dr0 = er2Dr0TdiBit[0];
   154    assign ip_functionality_id = 8'b00000001;  //-- SPI Serial FLASH Programmer (0x01)
   156 //   DR0_BIT0_BIT7 
   157    generate
   158       for(i=0; i<=7; i=i+1)
   159 	begin:DR0_BIT0_BIT7
   160 	   TYPEB BIT_N (.CLK        (JTCK),
   161 			.RESET_N    (JRSTN),
   162 			.CLKEN      (er2Dr0_enable),
   163 			.TDI        (er2Dr0TdiBit[i + 1]),
   164 			.TDO        (er2Dr0TdiBit[i]),
   165 			.DATA_IN    (ip_functionality_id[i]),
   166 			.CAPTURE_DR (captureDrER2));
   167 	end
   168    endgenerate // DR0_BIT0_BIT7
   170    assign er2Dr0TdiBit[8] = JTDI;
   172 //   ------ Data Register 1 ------
   174    assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ?  1'b1 : 1'b0;
   176    assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
   178    assign SPI_D = JTDI & er2Dr1_enable;
   180    //   SPI_S_Proc
   181    always @(negedge JTCK or negedge JRSTN)
   182      begin
   183 	if (~JRSTN)
   184           spi_s <= 1'b0;
   185 	else
   186           if (JUPDATE)
   187             spi_s <= 1'b0;
   188           else
   189             spi_s <= er2Dr1_enable;
   190      end
   192    assign SPI_SN = ~spi_s;
   194    //   SPI_Q_Proc
   195    always @(negedge JTCK or negedge JRSTN)
   196      begin
   197 	if (~JRSTN)
   198           spi_q_dly <= 'b0;
   199 	else
   200           if (er2Dr1_enable)
   201             spi_q_dly  <= {spi_q_dly[5:0],SPI_Q};
   202      end
   204    assign tdo_er2Dr1 = spi_q_dly[6];
   206    //   ------ JTDO2 MUX ------
   208    assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
   209 	  (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
   210 	  (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
   212    assign captureDrER2  = ~JSHIFT & JCE2;
   214 endmodule