typeb.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
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    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : TYPEB.v
    40 // Description:
    41 //    This is one of the two types of cells that are used to create ER1/ER2
    42 //    register bits.
    43 // Dependencies     : None
    44 // Version          : 6.1.17
    45 //   Modified typeb module to remove redundant DATA_OUT port.
    46 // Version          : 7.0SP2, 3.0
    47 //                  : No Change
    48 // Version          : 3.1
    49 //                  : No Change
    50 // =============================================================================
    51 module TYPEB
    52    (
    53       input CLK,
    54       input RESET_N,
    55       input CLKEN,
    56       input TDI,
    57       output TDO,
    58       input DATA_IN,
    59       input CAPTURE_DR
    60    );
    62    reg tdoInt;
    64    always @ (negedge CLK or negedge RESET_N)
    65    begin
    66       if (RESET_N== 1'b0)
    67          tdoInt <= 1'b0;
    68       else if (CLK == 1'b0)
    69          if (CLKEN==1'b1)
    70             if (CAPTURE_DR==1'b0)
    71                tdoInt <= TDI;
    72             else
    73                tdoInt <= DATA_IN;
    74    end
    76    assign TDO = tdoInt;
    78 endmodule