Sun, 06 Mar 2011 19:22:27 +0000
Make interrupts active high
Original-Author: lekernel
Original-Source: milkymist 5e8c03b53aaa820f3b43
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : er1.v
19 // Description:
20 // This module is where the ER1 register implemented. ER1 and ER2 registers
21 // can be registers implemented in Lattice FPGAs using normal FPGA's
22 // programmable logic resources. Once they are implemented, they can be
23 // accessed as if they are JTAG data registers through the FPGA JTAG port.
24 // In order to accessing these registers, JTAG instructions ER1(0x32) or
25 // ER2(0x38) needs to be written to the JTAG IR register for enabling the
26 // ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
27 // enabled one at a time. Once they are enabled, they will be disabled if
28 // another JTAG instruction is written into the JTAG instruction register.
29 // The registers allow dynamically accessing the FPGA internal information
30 // even when the device is running. Therefore, they are very useful for some
31 // of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
32 // cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
33 // The ER1/ER2 structure allows only one ER1 register but more than one ER2
34 // registers in an FPGA device. Please refer to the related document for
35 // this patterned ER1/ER2 structure.
36 // Dependencies : None
37 // Version : 6.0.14
38 // : Initial Version
39 // Version : 7.0SP2, 3.0
40 // : No Change
41 // Version : 3.1
42 // : No Change
43 // =============================================================================
44 module ER1 (input JTCK,
45 input JTDI,
46 output JTDO1,
47 output reg JTDO2,
48 input JSHIFT,
49 input JUPDATE,
50 input JRSTN,
51 input JCE1,
52 input [14:0] ER2_TDO,
53 output reg [14:0] IP_ENABLE,
54 input ISPTRACY_ER2_TDO,
55 output ISPTRACY_ENABLE,
56 output CONTROL_DATAN)/* synthesis syn_hier = hard */;
59 wire controlDataNBit;
60 wire ispTracyEnableBit;
61 wire [3:0] encodedIpEnableBits;
62 wire [9:0] er1TdiBit;
63 wire captureDrER1;
66 assign JTDO1 = er1TdiBit[0];
68 TYPEB BIT0 (.CLK(JTCK),
69 .RESET_N(JRSTN),
70 .CLKEN(JCE1),
71 .TDI(er1TdiBit[1]),
72 .TDO(er1TdiBit[0]),
73 .DATA_IN(1'b0),
74 .CAPTURE_DR(captureDrER1));
76 TYPEB BIT1 (.CLK(JTCK),
77 .RESET_N(JRSTN),
78 .CLKEN(JCE1),
79 .TDI(er1TdiBit[2]),
80 .TDO(er1TdiBit[1]),
81 .DATA_IN(1'b0),
82 .CAPTURE_DR(captureDrER1));
84 TYPEB BIT2 (.CLK(JTCK),
85 .RESET_N(JRSTN),
86 .CLKEN(JCE1),
87 .TDI(er1TdiBit[3]),
88 .TDO(er1TdiBit[2]),
89 .DATA_IN(1'b1),
90 .CAPTURE_DR(captureDrER1));
92 TYPEA BIT3 (.CLK(JTCK),
93 .RESET_N(JRSTN),
94 .CLKEN(JCE1),
95 .TDI(er1TdiBit[4]),
96 .TDO(er1TdiBit[3]),
97 .DATA_OUT(controlDataNBit),
98 .DATA_IN(controlDataNBit),
99 .CAPTURE_DR(captureDrER1),
100 .UPDATE_DR(JUPDATE));
102 assign CONTROL_DATAN = controlDataNBit;
104 TYPEA BIT4 (.CLK(JTCK),
105 .RESET_N(JRSTN),
106 .CLKEN(JCE1),
107 .TDI(er1TdiBit[5]),
108 .TDO(er1TdiBit[4]),
109 .DATA_OUT(ispTracyEnableBit),
110 .DATA_IN(ispTracyEnableBit),
111 .CAPTURE_DR(captureDrER1),
112 .UPDATE_DR(JUPDATE)
113 );
115 assign ISPTRACY_ENABLE = ispTracyEnableBit;
117 TYPEA BIT5 (.CLK(JTCK),
118 .RESET_N(JRSTN),
119 .CLKEN(JCE1),
120 .TDI(er1TdiBit[6]),
121 .TDO(er1TdiBit[5]),
122 .DATA_OUT(encodedIpEnableBits[0]),
123 .DATA_IN(encodedIpEnableBits[0]),
124 .CAPTURE_DR(captureDrER1),
125 .UPDATE_DR(JUPDATE));
127 TYPEA BIT6 (.CLK(JTCK),
128 .RESET_N(JRSTN),
129 .CLKEN(JCE1),
130 .TDI(er1TdiBit[7]),
131 .TDO(er1TdiBit[6]),
132 .DATA_OUT(encodedIpEnableBits[1]),
133 .DATA_IN(encodedIpEnableBits[1]),
134 .CAPTURE_DR(captureDrER1),
135 .UPDATE_DR(JUPDATE));
137 TYPEA BIT7 (.CLK(JTCK),
138 .RESET_N(JRSTN),
139 .CLKEN(JCE1),
140 .TDI(er1TdiBit[8]),
141 .TDO(er1TdiBit[7]),
142 .DATA_OUT(encodedIpEnableBits[2]),
143 .DATA_IN(encodedIpEnableBits[2]),
144 .CAPTURE_DR(captureDrER1),
145 .UPDATE_DR(JUPDATE));
147 TYPEA BIT8 (.CLK(JTCK),
148 .RESET_N(JRSTN),
149 .CLKEN(JCE1),
150 .TDI(er1TdiBit[9]),
151 .TDO(er1TdiBit[8]),
152 .DATA_OUT(encodedIpEnableBits[3]),
153 .DATA_IN(encodedIpEnableBits[3]),
154 .CAPTURE_DR(captureDrER1),
155 .UPDATE_DR(JUPDATE)
156 );
158 assign er1TdiBit[9] = JTDI;
159 assign captureDrER1 = !JSHIFT & JCE1;
161 always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
162 begin
163 case (encodedIpEnableBits)
164 4'h0: begin
165 IP_ENABLE <= 15'b000000000000000;
166 JTDO2 <= ISPTRACY_ER2_TDO;
167 end
168 4'h1: begin
169 IP_ENABLE <= 15'b000000000000001;
170 JTDO2 <= ER2_TDO[0];
171 end
172 4'h2: begin
173 IP_ENABLE <= 15'b000000000000010;
174 JTDO2 <= ER2_TDO[1];
175 end
176 4'h3: begin
177 IP_ENABLE <= 15'b000000000000100;
178 JTDO2 <= ER2_TDO[2];
179 end
180 4'h4: begin
181 IP_ENABLE <= 15'b000000000001000;
182 JTDO2 <= ER2_TDO[3];
183 end
184 4'h5: begin
185 IP_ENABLE <= 15'b000000000010000;
186 JTDO2 <= ER2_TDO[4];
187 end
188 4'h6: begin
189 IP_ENABLE <= 15'b000000000100000;
190 JTDO2 <= ER2_TDO[5];
191 end
192 4'h7: begin
193 IP_ENABLE <= 15'b000000001000000;
194 JTDO2 <= ER2_TDO[6];
195 end
196 4'h8: begin
197 IP_ENABLE <= 15'b000000010000000;
198 JTDO2 <= ER2_TDO[7];
199 end
200 4'h9: begin
201 IP_ENABLE <= 15'b000000100000000;
202 JTDO2 <= ER2_TDO[8];
203 end
204 4'hA: begin
205 IP_ENABLE <= 15'b000001000000000;
206 JTDO2 <= ER2_TDO[9];
207 end
208 4'hB: begin
209 IP_ENABLE <= 15'b000010000000000;
210 JTDO2 <= ER2_TDO[10];
211 end
212 4'hC: begin
213 IP_ENABLE <= 15'b000100000000000;
214 JTDO2 <= ER2_TDO[11];
215 end
216 4'hD: begin
217 IP_ENABLE <= 15'b001000000000000;
218 JTDO2 <= ER2_TDO[12];
219 end
220 4'hE: begin
221 IP_ENABLE <= 15'b010000000000000;
222 JTDO2 <= ER2_TDO[13];
223 end
224 4'hF: begin
225 IP_ENABLE <= 15'b100000000000000;
226 JTDO2 <= ER2_TDO[14];
227 end
228 endcase
229 end
230 endmodule