IPCores/lm32_cpu / annotate

lm32_top.v@cc945f778cd7 (annotated)

lm32_top.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
parent 16
5fb37de64edc
permissions
-rwxr-xr-x

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

philpem@0 1 // =============================================================================
philpem@0 2 // COPYRIGHT NOTICE
philpem@0 3 // Copyright 2006 (c) Lattice Semiconductor Corporation
philpem@0 4 // ALL RIGHTS RESERVED
philpem@0 5 // This confidential and proprietary software may be used only as authorised by
philpem@0 6 // a licensing agreement from Lattice Semiconductor Corporation.
philpem@0 7 // The entire notice above must be reproduced on all authorized copies and
philpem@0 8 // copies may only be made to the extent permitted by a licensing agreement from
philpem@0 9 // Lattice Semiconductor Corporation.
philpem@0 10 //
philpem@0 11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
philpem@0 12 // 5555 NE Moore Court 408-826-6000 (other locations)
philpem@0 13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
philpem@0 14 // U.S.A email: techsupport@latticesemi.com
philpem@0 15 // =============================================================================/
philpem@0 16 // FILE DETAILS
philpem@0 17 // Project : LatticeMico32
philpem@0 18 // File : lm32_top.v
philpem@0 19 // Title : Top-level of CPU.
philpem@0 20 // Dependencies : lm32_include.v
philpem@0 21 // Version : 6.1.17
philpem@0 22 // : removed SPI - 04/12/07
philpem@0 23 // Version : 7.0SP2, 3.0
philpem@0 24 // : No Change
philpem@0 25 // Version : 3.1
philpem@0 26 // : No Change
philpem@0 27 // =============================================================================
philpem@0 28
philpem@0 29 `include "lm32_include.v"
philpem@0 30
philpem@0 31 /////////////////////////////////////////////////////
philpem@0 32 // Module interface
philpem@0 33 /////////////////////////////////////////////////////
philpem@0 34
philpem@0 35 module lm32_top (
philpem@0 36 // ----- Inputs -------
philpem@0 37 clk_i,
philpem@0 38 rst_i,
philpem@0 39 // From external devices
philpem@0 40 `ifdef CFG_INTERRUPTS_ENABLED
philpem@12 41 interrupt,
philpem@0 42 `endif
philpem@0 43 // From user logic
philpem@0 44 `ifdef CFG_USER_ENABLED
philpem@0 45 user_result,
philpem@0 46 user_complete,
philpem@0 47 `endif
philpem@0 48 `ifdef CFG_IWB_ENABLED
philpem@0 49 // Instruction Wishbone master
philpem@0 50 I_DAT_I,
philpem@0 51 I_ACK_I,
philpem@0 52 I_ERR_I,
philpem@0 53 I_RTY_I,
philpem@0 54 `endif
philpem@0 55 // Data Wishbone master
philpem@0 56 D_DAT_I,
philpem@0 57 D_ACK_I,
philpem@0 58 D_ERR_I,
philpem@0 59 D_RTY_I,
philpem@0 60 // ----- Outputs -------
philpem@0 61 `ifdef CFG_USER_ENABLED
philpem@0 62 user_valid,
philpem@0 63 user_opcode,
philpem@0 64 user_operand_0,
philpem@0 65 user_operand_1,
philpem@0 66 `endif
philpem@0 67 `ifdef CFG_IWB_ENABLED
philpem@0 68 // Instruction Wishbone master
philpem@0 69 I_DAT_O,
philpem@0 70 I_ADR_O,
philpem@0 71 I_CYC_O,
philpem@0 72 I_SEL_O,
philpem@0 73 I_STB_O,
philpem@0 74 I_WE_O,
philpem@0 75 I_CTI_O,
philpem@0 76 I_LOCK_O,
philpem@0 77 I_BTE_O,
philpem@0 78 `endif
philpem@0 79 // Data Wishbone master
philpem@0 80 D_DAT_O,
philpem@0 81 D_ADR_O,
philpem@0 82 D_CYC_O,
philpem@0 83 D_SEL_O,
philpem@0 84 D_STB_O,
philpem@0 85 D_WE_O,
philpem@0 86 D_CTI_O,
philpem@0 87 D_LOCK_O,
philpem@14 88 D_BTE_O
philpem@0 89 );
philpem@0 90
philpem@0 91 /////////////////////////////////////////////////////
philpem@0 92 // Inputs
philpem@0 93 /////////////////////////////////////////////////////
philpem@0 94
philpem@0 95 input clk_i; // Clock
philpem@0 96 input rst_i; // Reset
philpem@0 97
philpem@0 98 `ifdef CFG_INTERRUPTS_ENABLED
philpem@12 99 input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
philpem@0 100 `endif
philpem@0 101
philpem@0 102 `ifdef CFG_USER_ENABLED
philpem@0 103 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
philpem@0 104 input user_complete; // Indicates the user-defined instruction result is valid
philpem@0 105 `endif
philpem@0 106
philpem@0 107 `ifdef CFG_IWB_ENABLED
philpem@0 108 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
philpem@0 109 input I_ACK_I; // Instruction Wishbone interface acknowledgement
philpem@0 110 input I_ERR_I; // Instruction Wishbone interface error
philpem@0 111 input I_RTY_I; // Instruction Wishbone interface retry
philpem@0 112 `endif
philpem@0 113
philpem@0 114 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
philpem@0 115 input D_ACK_I; // Data Wishbone interface acknowledgement
philpem@0 116 input D_ERR_I; // Data Wishbone interface error
philpem@0 117 input D_RTY_I; // Data Wishbone interface retry
philpem@0 118
philpem@0 119 /////////////////////////////////////////////////////
philpem@0 120 // Outputs
philpem@0 121 /////////////////////////////////////////////////////
philpem@0 122
philpem@0 123 `ifdef CFG_USER_ENABLED
philpem@0 124 output user_valid; // Indicates that user_opcode and user_operand_* are valid
philpem@0 125 wire user_valid;
philpem@0 126 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
philpem@0 127 reg [`LM32_USER_OPCODE_RNG] user_opcode;
philpem@0 128 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
philpem@0 129 wire [`LM32_WORD_RNG] user_operand_0;
philpem@0 130 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
philpem@0 131 wire [`LM32_WORD_RNG] user_operand_1;
philpem@0 132 `endif
philpem@0 133
philpem@0 134 `ifdef CFG_IWB_ENABLED
philpem@0 135 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
philpem@0 136 wire [`LM32_WORD_RNG] I_DAT_O;
philpem@0 137 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
philpem@0 138 wire [`LM32_WORD_RNG] I_ADR_O;
philpem@0 139 output I_CYC_O; // Instruction Wishbone interface cycle
philpem@0 140 wire I_CYC_O;
philpem@0 141 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
philpem@0 142 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
philpem@0 143 output I_STB_O; // Instruction Wishbone interface strobe
philpem@0 144 wire I_STB_O;
philpem@0 145 output I_WE_O; // Instruction Wishbone interface write enable
philpem@0 146 wire I_WE_O;
philpem@0 147 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
philpem@0 148 wire [`LM32_CTYPE_RNG] I_CTI_O;
philpem@0 149 output I_LOCK_O; // Instruction Wishbone interface lock bus
philpem@0 150 wire I_LOCK_O;
philpem@0 151 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
philpem@0 152 wire [`LM32_BTYPE_RNG] I_BTE_O;
philpem@0 153 `endif
philpem@0 154
philpem@0 155 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
philpem@0 156 wire [`LM32_WORD_RNG] D_DAT_O;
philpem@0 157 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
philpem@0 158 wire [`LM32_WORD_RNG] D_ADR_O;
philpem@0 159 output D_CYC_O; // Data Wishbone interface cycle
philpem@0 160 wire D_CYC_O;
philpem@0 161 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
philpem@0 162 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
philpem@0 163 output D_STB_O; // Data Wishbone interface strobe
philpem@0 164 wire D_STB_O;
philpem@0 165 output D_WE_O; // Data Wishbone interface write enable
philpem@0 166 wire D_WE_O;
philpem@0 167 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
philpem@0 168 wire [`LM32_CTYPE_RNG] D_CTI_O;
philpem@0 169 output D_LOCK_O; // Date Wishbone interface lock bus
philpem@0 170 wire D_LOCK_O;
philpem@0 171 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
philpem@0 172 wire [`LM32_BTYPE_RNG] D_BTE_O;
philpem@0 173
philpem@0 174 /////////////////////////////////////////////////////
philpem@0 175 // Internal nets and registers
philpem@0 176 /////////////////////////////////////////////////////
philpem@0 177
philpem@0 178 `ifdef CFG_JTAG_ENABLED
philpem@0 179 // Signals between JTAG interface and CPU
philpem@0 180 wire [`LM32_BYTE_RNG] jtag_reg_d;
philpem@0 181 wire [`LM32_BYTE_RNG] jtag_reg_q;
philpem@0 182 wire jtag_update;
philpem@0 183 wire [2:0] jtag_reg_addr_d;
philpem@0 184 wire [2:0] jtag_reg_addr_q;
philpem@0 185 wire jtck;
philpem@0 186 wire jrstn;
philpem@0 187 `endif
philpem@0 188
philpem@14 189 // TODO: get the trace signals out
philpem@0 190 `ifdef CFG_TRACE_ENABLED
philpem@0 191 // PC trace signals
philpem@0 192 wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
philpem@0 193 wire trace_pc_valid; // Indicates that a new trace PC is valid
philpem@0 194 wire trace_exception; // Indicates an exception has occured
philpem@0 195 wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
philpem@0 196 wire trace_eret; // Indicates an eret instruction has been executed
philpem@0 197 `ifdef CFG_DEBUG_ENABLED
philpem@0 198 wire trace_bret; // Indicates a bret instruction has been executed
philpem@0 199 `endif
philpem@0 200 `endif
philpem@0 201
philpem@0 202 /////////////////////////////////////////////////////
philpem@0 203 // Functions
philpem@0 204 /////////////////////////////////////////////////////
philpem@0 205
philpem@0 206 `include "lm32_functions.v"
philpem@0 207 /////////////////////////////////////////////////////
philpem@0 208 // Instantiations
philpem@0 209 /////////////////////////////////////////////////////
philpem@12 210
philpem@12 211 // LM32 CPU
philpem@0 212 lm32_cpu cpu (
philpem@0 213 // ----- Inputs -------
philpem@0 214 .clk_i (clk_i),
philpem@0 215 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
philpem@0 216 .clk_n_i (clk_n),
philpem@0 217 `endif
philpem@0 218 .rst_i (rst_i),
philpem@0 219 // From external devices
philpem@0 220 `ifdef CFG_INTERRUPTS_ENABLED
philpem@12 221 .interrupt (interrupt),
philpem@0 222 `endif
philpem@0 223 // From user logic
philpem@0 224 `ifdef CFG_USER_ENABLED
philpem@0 225 .user_result (user_result),
philpem@0 226 .user_complete (user_complete),
philpem@0 227 `endif
philpem@0 228 `ifdef CFG_JTAG_ENABLED
philpem@0 229 // From JTAG
philpem@0 230 .jtag_clk (jtck),
philpem@0 231 .jtag_update (jtag_update),
philpem@0 232 .jtag_reg_q (jtag_reg_q),
philpem@0 233 .jtag_reg_addr_q (jtag_reg_addr_q),
philpem@0 234 `endif
philpem@0 235 `ifdef CFG_IWB_ENABLED
philpem@0 236 // Instruction Wishbone master
philpem@0 237 .I_DAT_I (I_DAT_I),
philpem@0 238 .I_ACK_I (I_ACK_I),
philpem@0 239 .I_ERR_I (I_ERR_I),
philpem@0 240 .I_RTY_I (I_RTY_I),
philpem@0 241 `endif
philpem@0 242 // Data Wishbone master
philpem@0 243 .D_DAT_I (D_DAT_I),
philpem@0 244 .D_ACK_I (D_ACK_I),
philpem@0 245 .D_ERR_I (D_ERR_I),
philpem@0 246 .D_RTY_I (D_RTY_I),
philpem@0 247 // ----- Outputs -------
philpem@0 248 `ifdef CFG_TRACE_ENABLED
philpem@0 249 .trace_pc (trace_pc),
philpem@0 250 .trace_pc_valid (trace_pc_valid),
philpem@0 251 .trace_exception (trace_exception),
philpem@0 252 .trace_eid (trace_eid),
philpem@0 253 .trace_eret (trace_eret),
philpem@0 254 `ifdef CFG_DEBUG_ENABLED
philpem@0 255 .trace_bret (trace_bret),
philpem@0 256 `endif
philpem@0 257 `endif
philpem@0 258 `ifdef CFG_JTAG_ENABLED
philpem@0 259 .jtag_reg_d (jtag_reg_d),
philpem@0 260 .jtag_reg_addr_d (jtag_reg_addr_d),
philpem@0 261 `endif
philpem@0 262 `ifdef CFG_USER_ENABLED
philpem@0 263 .user_valid (user_valid),
philpem@0 264 .user_opcode (user_opcode),
philpem@0 265 .user_operand_0 (user_operand_0),
philpem@0 266 .user_operand_1 (user_operand_1),
philpem@0 267 `endif
philpem@0 268 `ifdef CFG_IWB_ENABLED
philpem@0 269 // Instruction Wishbone master
philpem@0 270 .I_DAT_O (I_DAT_O),
philpem@0 271 .I_ADR_O (I_ADR_O),
philpem@0 272 .I_CYC_O (I_CYC_O),
philpem@0 273 .I_SEL_O (I_SEL_O),
philpem@0 274 .I_STB_O (I_STB_O),
philpem@0 275 .I_WE_O (I_WE_O),
philpem@0 276 .I_CTI_O (I_CTI_O),
philpem@0 277 .I_LOCK_O (I_LOCK_O),
philpem@0 278 .I_BTE_O (I_BTE_O),
philpem@0 279 `endif
philpem@0 280 // Data Wishbone master
philpem@0 281 .D_DAT_O (D_DAT_O),
philpem@0 282 .D_ADR_O (D_ADR_O),
philpem@0 283 .D_CYC_O (D_CYC_O),
philpem@0 284 .D_SEL_O (D_SEL_O),
philpem@0 285 .D_STB_O (D_STB_O),
philpem@0 286 .D_WE_O (D_WE_O),
philpem@0 287 .D_CTI_O (D_CTI_O),
philpem@0 288 .D_LOCK_O (D_LOCK_O),
philpem@0 289 .D_BTE_O (D_BTE_O)
philpem@0 290 );
philpem@0 291
philpem@0 292 wire TRACE_ACK_O;
philpem@0 293 wire [`LM32_WORD_RNG] TRACE_DAT_O;
philpem@0 294 `ifdef CFG_TRACE_ENABLED
philpem@0 295 lm32_trace trace_module (.clk_i (clk_i),
philpem@0 296 .rst_i (rst_i),
philpem@0 297 .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
philpem@0 298 .we_i (DEBUG_WE_I),
philpem@0 299 .sel_i (DEBUG_SEL_I),
philpem@0 300 .dat_i (DEBUG_DAT_I),
philpem@0 301 .adr_i (DEBUG_ADR_I),
philpem@0 302 .trace_pc (trace_pc),
philpem@0 303 .trace_eid (trace_eid),
philpem@0 304 .trace_eret (trace_eret),
philpem@0 305 .trace_bret (trace_bret),
philpem@0 306 .trace_pc_valid (trace_pc_valid),
philpem@0 307 .trace_exception (trace_exception),
philpem@0 308 .ack_o (TRACE_ACK_O),
philpem@0 309 .dat_o (TRACE_DAT_O));
philpem@0 310 `else
philpem@0 311 assign TRACE_ACK_O = 0;
philpem@0 312 assign TRACE_DAT_O = 0;
philpem@0 313 `endif
philpem@0 314 `ifdef DEBUG_ROM
philpem@0 315 wire ROM_ACK_O;
philpem@0 316 wire [`LM32_WORD_RNG] ROM_DAT_O;
philpem@0 317
philpem@0 318 assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
philpem@0 319 assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
philpem@0 320
philpem@0 321 // ROM monitor
philpem@0 322 lm32_monitor debug_rom (
philpem@0 323 // ----- Inputs -------
philpem@0 324 .clk_i (clk_i),
philpem@0 325 .rst_i (rst_i),
philpem@8 326 .MON_ADR_I (DEBUG_ADR_I[10:2]),
philpem@0 327 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
philpem@0 328 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
philpem@0 329 .MON_WE_I (DEBUG_WE_I),
philpem@0 330 .MON_SEL_I (DEBUG_SEL_I),
philpem@0 331 .MON_DAT_I (DEBUG_DAT_I),
philpem@0 332 // ----- Outputs ------
philpem@0 333 .MON_RTY_O (DEBUG_RTY_O),
philpem@0 334 .MON_ERR_O (DEBUG_ERR_O),
philpem@0 335 .MON_ACK_O (ROM_ACK_O),
philpem@0 336 .MON_DAT_O (ROM_DAT_O)
philpem@0 337 );
philpem@0 338 `endif
philpem@0 339
philpem@0 340 `ifdef CFG_JTAG_ENABLED
philpem@0 341 // JTAG cores
philpem@0 342 jtag_cores jtag_cores (
philpem@0 343 // ----- Inputs -----
philpem@0 344 .reg_d (jtag_reg_d),
philpem@0 345 .reg_addr_d (jtag_reg_addr_d),
philpem@0 346 // ----- Outputs -----
philpem@0 347 .reg_update (jtag_update),
philpem@0 348 .reg_q (jtag_reg_q),
philpem@0 349 .reg_addr_q (jtag_reg_addr_q),
philpem@0 350 .jtck (jtck),
philpem@0 351 .jrstn (jrstn)
philpem@0 352 );
philpem@0 353 `endif
philpem@0 354
philpem@0 355 endmodule