1.1 diff -r 07be9df9fee8 -r 35dc7ba83714 lm32_monitor.v 1.2 --- a/lm32_monitor.v Fri Aug 13 01:13:04 2010 +0100 1.3 +++ b/lm32_monitor.v Sun Mar 06 21:14:43 2011 +0000 1.4 @@ -130,13 +130,7 @@ 1.5 end 1.6 else 1.7 begin 1.8 - case (state) 1.9 - 2'b00: 1.10 - begin 1.11 - // Wait for a Wishbone access 1.12 - if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.13 - state <= 2'b01; 1.14 - end 1.15 + casez (state) 1.16 2'b01: 1.17 begin 1.18 // Output read data to Wishbone 1.19 @@ -160,6 +154,14 @@ 1.20 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}}; 1.21 state <= 2'b00; 1.22 end 1.23 + default: 1.24 + begin 1.25 + write_enable <= `FALSE; 1.26 + MON_ACK_O <= `FALSE; 1.27 + // Wait for a Wishbone access 1.28 + if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE)) 1.29 + state <= 2'b01; 1.30 + end 1.31 endcase 1.32 end 1.33 end