1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_dcache.v 1.2 --- a/lm32_dcache.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_dcache.v 1.58 @@ -420,11 +441,11 @@ 1.59 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.60 begin 1.61 if (rst_i == `TRUE) 1.62 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.63 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 1.64 else 1.65 begin 1.66 if (refill_request == `TRUE) 1.67 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.68 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 1.69 end 1.70 end 1.71 end 1.72 @@ -434,9 +455,9 @@ 1.73 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.74 begin 1.75 if (rst_i == `TRUE) 1.76 - refilling <= `FALSE; 1.77 + refilling <= #1 `FALSE; 1.78 else 1.79 - refilling <= refill; 1.80 + refilling <= #1 refill; 1.81 end 1.82 1.83 // Instruction cache control FSM 1.84 @@ -444,11 +465,11 @@ 1.85 begin 1.86 if (rst_i == `TRUE) 1.87 begin 1.88 - state <= `LM32_DC_STATE_FLUSH; 1.89 - flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.90 - refill_request <= `FALSE; 1.91 - refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 1.92 - restart_request <= `FALSE; 1.93 + state <= #1 `LM32_DC_STATE_FLUSH; 1.94 + flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.95 + refill_request <= #1 `FALSE; 1.96 + refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.97 + restart_request <= #1 `FALSE; 1.98 end 1.99 else 1.100 begin 1.101 @@ -458,35 +479,35 @@ 1.102 `LM32_DC_STATE_FLUSH: 1.103 begin 1.104 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 1.105 - state <= `LM32_DC_STATE_CHECK; 1.106 - flush_set <= flush_set - 1'b1; 1.107 + state <= #1 `LM32_DC_STATE_CHECK; 1.108 + flush_set <= #1 flush_set - 1'b1; 1.109 end 1.110 1.111 // Check for cache misses 1.112 `LM32_DC_STATE_CHECK: 1.113 begin 1.114 if (stall_a == `FALSE) 1.115 - restart_request <= `FALSE; 1.116 + restart_request <= #1 `FALSE; 1.117 if (miss == `TRUE) 1.118 begin 1.119 - refill_request <= `TRUE; 1.120 - refill_address <= address_m; 1.121 - state <= `LM32_DC_STATE_REFILL; 1.122 + refill_request <= #1 `TRUE; 1.123 + refill_address <= #1 address_m; 1.124 + state <= #1 `LM32_DC_STATE_REFILL; 1.125 end 1.126 else if (dflush == `TRUE) 1.127 - state <= `LM32_DC_STATE_FLUSH; 1.128 + state <= #1 `LM32_DC_STATE_FLUSH; 1.129 end 1.130 1.131 // Refill a cache line 1.132 `LM32_DC_STATE_REFILL: 1.133 begin 1.134 - refill_request <= `FALSE; 1.135 + refill_request <= #1 `FALSE; 1.136 if (refill_ready == `TRUE) 1.137 begin 1.138 if (last_refill == `TRUE) 1.139 begin 1.140 - restart_request <= `TRUE; 1.141 - state <= `LM32_DC_STATE_CHECK; 1.142 + restart_request <= #1 `TRUE; 1.143 + state <= #1 `LM32_DC_STATE_CHECK; 1.144 end 1.145 end 1.146 end 1.147 @@ -502,7 +523,7 @@ 1.148 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.149 begin 1.150 if (rst_i == `TRUE) 1.151 - refill_offset <= {addr_offset_width{1'b0}}; 1.152 + refill_offset <= #1 {addr_offset_width{1'b0}}; 1.153 else 1.154 begin 1.155 case (state) 1.156 @@ -511,14 +532,14 @@ 1.157 `LM32_DC_STATE_CHECK: 1.158 begin 1.159 if (miss == `TRUE) 1.160 - refill_offset <= {addr_offset_width{1'b0}}; 1.161 + refill_offset <= #1 {addr_offset_width{1'b0}}; 1.162 end 1.163 1.164 // Refill a cache line 1.165 `LM32_DC_STATE_REFILL: 1.166 begin 1.167 if (refill_ready == `TRUE) 1.168 - refill_offset <= refill_offset + 1'b1; 1.169 + refill_offset <= #1 refill_offset + 1'b1; 1.170 end 1.171 1.172 endcase