1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_debug.v 1.2 --- a/lm32_debug.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_debug.v 1.58 @@ -226,15 +247,15 @@ 1.59 begin 1.60 if (rst_i == `TRUE) 1.61 begin 1.62 - bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 1.63 - bp_e[i] <= `FALSE; 1.64 + bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 1.65 + bp_e[i] <= #1 `FALSE; 1.66 end 1.67 else 1.68 begin 1.69 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 1.70 begin 1.71 - bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 1.72 - bp_e[i] <= debug_csr_write_data[0]; 1.73 + bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 1.74 + bp_e[i] <= #1 debug_csr_write_data[0]; 1.75 end 1.76 end 1.77 end 1.78 @@ -249,17 +270,17 @@ 1.79 begin 1.80 if (rst_i == `TRUE) 1.81 begin 1.82 - wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 1.83 - wpc_c[i] <= `LM32_WPC_C_DISABLED; 1.84 + wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.85 + wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 1.86 end 1.87 else 1.88 begin 1.89 if (debug_csr_write_enable == `TRUE) 1.90 begin 1.91 if (debug_csr == `LM32_CSR_DC) 1.92 - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 1.93 + wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 1.94 if (debug_csr == `LM32_CSR_WP0 + i) 1.95 - wp[i] <= debug_csr_write_data; 1.96 + wp[i] <= #1 debug_csr_write_data; 1.97 end 1.98 end 1.99 end 1.100 @@ -270,11 +291,11 @@ 1.101 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.102 begin 1.103 if (rst_i == `TRUE) 1.104 - dc_re <= `FALSE; 1.105 + dc_re <= #1 `FALSE; 1.106 else 1.107 begin 1.108 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.109 - dc_re <= debug_csr_write_data[1]; 1.110 + dc_re <= #1 debug_csr_write_data[1]; 1.111 end 1.112 end 1.113 1.114 @@ -284,18 +305,18 @@ 1.115 begin 1.116 if (rst_i == `TRUE) 1.117 begin 1.118 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.119 - dc_ss <= `FALSE; 1.120 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.121 + dc_ss <= #1 `FALSE; 1.122 end 1.123 else 1.124 begin 1.125 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.126 begin 1.127 - dc_ss <= debug_csr_write_data[0]; 1.128 + dc_ss <= #1 debug_csr_write_data[0]; 1.129 if (debug_csr_write_data[0] == `FALSE) 1.130 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.131 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.132 else 1.133 - state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.134 + state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.135 end 1.136 case (state) 1.137 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 1.138 @@ -306,26 +327,26 @@ 1.139 ) 1.140 && (stall_x == `FALSE) 1.141 ) 1.142 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.143 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.144 end 1.145 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 1.146 begin 1.147 // Wait for an instruction to be executed 1.148 if ((q_x == `TRUE) && (stall_x == `FALSE)) 1.149 - state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.150 + state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.151 end 1.152 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 1.153 begin 1.154 // Wait for exception to be raised 1.155 `ifdef CFG_DCACHE_ENABLED 1.156 if (dcache_refill_request == `TRUE) 1.157 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.158 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.159 else 1.160 `endif 1.161 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.162 begin 1.163 - dc_ss <= `FALSE; 1.164 - state <= `LM32_DEBUG_SS_STATE_RESTART; 1.165 + dc_ss <= #1 `FALSE; 1.166 + state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 1.167 end 1.168 end 1.169 `LM32_DEBUG_SS_STATE_RESTART: 1.170 @@ -333,10 +354,10 @@ 1.171 // Watch to see if stepped instruction is restarted due to a cache miss 1.172 `ifdef CFG_DCACHE_ENABLED 1.173 if (dcache_refill_request == `TRUE) 1.174 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.175 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.176 else 1.177 `endif 1.178 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.179 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.180 end 1.181 endcase 1.182 end