1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_icache.v 1.2 --- a/lm32_icache.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_icache.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_icache.v 1.58 @@ -359,11 +380,11 @@ 1.59 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.60 begin 1.61 if (rst_i == `TRUE) 1.62 - refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.63 + refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 1.64 else 1.65 begin 1.66 if (miss == `TRUE) 1.67 - refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.68 + refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 1.69 end 1.70 end 1.71 end 1.72 @@ -373,9 +394,9 @@ 1.73 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.74 begin 1.75 if (rst_i == `TRUE) 1.76 - refilling <= `FALSE; 1.77 + refilling <= #1 `FALSE; 1.78 else 1.79 - refilling <= refill; 1.80 + refilling <= #1 refill; 1.81 end 1.82 1.83 // Instruction cache control FSM 1.84 @@ -383,10 +404,10 @@ 1.85 begin 1.86 if (rst_i == `TRUE) 1.87 begin 1.88 - state <= `LM32_IC_STATE_FLUSH_INIT; 1.89 - flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.90 - refill_address <= {`LM32_PC_WIDTH{1'bx}}; 1.91 - restart_request <= `FALSE; 1.92 + state <= #1 `LM32_IC_STATE_FLUSH_INIT; 1.93 + flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}}; 1.94 + refill_address <= #1 {`LM32_PC_WIDTH{1'bx}}; 1.95 + restart_request <= #1 `FALSE; 1.96 end 1.97 else 1.98 begin 1.99 @@ -396,8 +417,8 @@ 1.100 `LM32_IC_STATE_FLUSH_INIT: 1.101 begin 1.102 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.103 - state <= `LM32_IC_STATE_CHECK; 1.104 - flush_set <= flush_set - 1'b1; 1.105 + state <= #1 `LM32_IC_STATE_CHECK; 1.106 + flush_set <= #1 flush_set - 1'b1; 1.107 end 1.108 1.109 // Flush the cache in response to an write to the ICC CSR 1.110 @@ -406,28 +427,28 @@ 1.111 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}}) 1.112 `ifdef CFG_IROM_ENABLED 1.113 if (select_f) 1.114 - state <= `LM32_IC_STATE_REFILL; 1.115 + state <= #1 `LM32_IC_STATE_REFILL; 1.116 else 1.117 `endif 1.118 - state <= `LM32_IC_STATE_CHECK; 1.119 + state <= #1 `LM32_IC_STATE_CHECK; 1.120 1.121 - flush_set <= flush_set - 1'b1; 1.122 + flush_set <= #1 flush_set - 1'b1; 1.123 end 1.124 1.125 // Check for cache misses 1.126 `LM32_IC_STATE_CHECK: 1.127 begin 1.128 if (stall_a == `FALSE) 1.129 - restart_request <= `FALSE; 1.130 + restart_request <= #1 `FALSE; 1.131 if (iflush == `TRUE) 1.132 begin 1.133 - refill_address <= address_f; 1.134 - state <= `LM32_IC_STATE_FLUSH; 1.135 + refill_address <= #1 address_f; 1.136 + state <= #1 `LM32_IC_STATE_FLUSH; 1.137 end 1.138 else if (miss == `TRUE) 1.139 begin 1.140 - refill_address <= address_f; 1.141 - state <= `LM32_IC_STATE_REFILL; 1.142 + refill_address <= #1 address_f; 1.143 + state <= #1 `LM32_IC_STATE_REFILL; 1.144 end 1.145 end 1.146 1.147 @@ -438,8 +459,8 @@ 1.148 begin 1.149 if (last_refill == `TRUE) 1.150 begin 1.151 - restart_request <= `TRUE; 1.152 - state <= `LM32_IC_STATE_CHECK; 1.153 + restart_request <= #1 `TRUE; 1.154 + state <= #1 `LM32_IC_STATE_CHECK; 1.155 end 1.156 end 1.157 end 1.158 @@ -455,7 +476,7 @@ 1.159 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.160 begin 1.161 if (rst_i == `TRUE) 1.162 - refill_offset <= {addr_offset_width{1'b0}}; 1.163 + refill_offset <= #1 {addr_offset_width{1'b0}}; 1.164 else 1.165 begin 1.166 case (state) 1.167 @@ -464,16 +485,16 @@ 1.168 `LM32_IC_STATE_CHECK: 1.169 begin 1.170 if (iflush == `TRUE) 1.171 - refill_offset <= {addr_offset_width{1'b0}}; 1.172 + refill_offset <= #1 {addr_offset_width{1'b0}}; 1.173 else if (miss == `TRUE) 1.174 - refill_offset <= {addr_offset_width{1'b0}}; 1.175 + refill_offset <= #1 {addr_offset_width{1'b0}}; 1.176 end 1.177 1.178 // Refill a cache line 1.179 `LM32_IC_STATE_REFILL: 1.180 begin 1.181 if (refill_ready == `TRUE) 1.182 - refill_offset <= refill_offset + 1'b1; 1.183 + refill_offset <= #1 refill_offset + 1'b1; 1.184 end 1.185 1.186 endcase