1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_interrupt.v 1.2 --- a/lm32_interrupt.v Sun Mar 06 21:14:43 2011 +0000 1.3 +++ b/lm32_interrupt.v Sat Aug 06 00:02:46 2011 +0100 1.4 @@ -1,18 +1,39 @@ 1.5 -// ============================================================================= 1.6 -// COPYRIGHT NOTICE 1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.8 -// ALL RIGHTS RESERVED 1.9 -// This confidential and proprietary software may be used only as authorised by 1.10 -// a licensing agreement from Lattice Semiconductor Corporation. 1.11 -// The entire notice above must be reproduced on all authorized copies and 1.12 -// copies may only be made to the extent permitted by a licensing agreement from 1.13 -// Lattice Semiconductor Corporation. 1.14 +// ================================================================== 1.15 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.16 +// ------------------------------------------------------------------ 1.17 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.18 +// ALL RIGHTS RESERVED 1.19 +// ------------------------------------------------------------------ 1.20 +// 1.21 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.22 +// 1.23 +// Permission: 1.24 +// 1.25 +// Lattice Semiconductor grants permission to use this code 1.26 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.27 +// Open Source License Agreement. 1.28 +// 1.29 +// Disclaimer: 1.30 // 1.31 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.32 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.33 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.34 -// U.S.A email: techsupport@latticesemi.com 1.35 -// =============================================================================/ 1.36 +// Lattice Semiconductor provides no warranty regarding the use or 1.37 +// functionality of this code. It is the user's responsibility to 1.38 +// verify the user’s design for consistency and functionality through 1.39 +// the use of formal verification methods. 1.40 +// 1.41 +// -------------------------------------------------------------------- 1.42 +// 1.43 +// Lattice Semiconductor Corporation 1.44 +// 5555 NE Moore Court 1.45 +// Hillsboro, OR 97214 1.46 +// U.S.A 1.47 +// 1.48 +// TEL: 1-800-Lattice (USA and Canada) 1.49 +// 503-286-8001 (other locations) 1.50 +// 1.51 +// web: http://www.latticesemi.com/ 1.52 +// email: techsupport@latticesemi.com 1.53 +// 1.54 +// -------------------------------------------------------------------- 1.55 // FILE DETAILS 1.56 // Project : LatticeMico32 1.57 // File : lm32_interrupt.v 1.58 @@ -199,64 +220,64 @@ 1.59 begin 1.60 if (rst_i == `TRUE) 1.61 begin 1.62 - ie <= `FALSE; 1.63 - eie <= `FALSE; 1.64 + ie <= #1 `FALSE; 1.65 + eie <= #1 `FALSE; 1.66 `ifdef CFG_DEBUG_ENABLED 1.67 - bie <= `FALSE; 1.68 + bie <= #1 `FALSE; 1.69 `endif 1.70 - im <= {interrupts{1'b0}}; 1.71 - ip <= {interrupts{1'b0}}; 1.72 + im <= #1 {interrupts{1'b0}}; 1.73 + ip <= #1 {interrupts{1'b0}}; 1.74 end 1.75 else 1.76 begin 1.77 // Set IP bit when interrupt line is asserted 1.78 - ip <= asserted; 1.79 + ip <= #1 asserted; 1.80 `ifdef CFG_DEBUG_ENABLED 1.81 if (non_debug_exception == `TRUE) 1.82 begin 1.83 // Save and then clear interrupt enable 1.84 - eie <= ie; 1.85 - ie <= `FALSE; 1.86 + eie <= #1 ie; 1.87 + ie <= #1 `FALSE; 1.88 end 1.89 else if (debug_exception == `TRUE) 1.90 begin 1.91 // Save and then clear interrupt enable 1.92 - bie <= ie; 1.93 - ie <= `FALSE; 1.94 + bie <= #1 ie; 1.95 + ie <= #1 `FALSE; 1.96 end 1.97 `else 1.98 if (exception == `TRUE) 1.99 begin 1.100 // Save and then clear interrupt enable 1.101 - eie <= ie; 1.102 - ie <= `FALSE; 1.103 + eie <= #1 ie; 1.104 + ie <= #1 `FALSE; 1.105 end 1.106 `endif 1.107 else if (stall_x == `FALSE) 1.108 begin 1.109 if (eret_q_x == `TRUE) 1.110 // Restore interrupt enable 1.111 - ie <= eie; 1.112 + ie <= #1 eie; 1.113 `ifdef CFG_DEBUG_ENABLED 1.114 else if (bret_q_x == `TRUE) 1.115 // Restore interrupt enable 1.116 - ie <= bie; 1.117 + ie <= #1 bie; 1.118 `endif 1.119 else if (csr_write_enable == `TRUE) 1.120 begin 1.121 // Handle wcsr write 1.122 if (csr == `LM32_CSR_IE) 1.123 begin 1.124 - ie <= csr_write_data[0]; 1.125 - eie <= csr_write_data[1]; 1.126 + ie <= #1 csr_write_data[0]; 1.127 + eie <= #1 csr_write_data[1]; 1.128 `ifdef CFG_DEBUG_ENABLED 1.129 - bie <= csr_write_data[2]; 1.130 + bie <= #1 csr_write_data[2]; 1.131 `endif 1.132 end 1.133 if (csr == `LM32_CSR_IM) 1.134 - im <= csr_write_data[interrupts-1:0]; 1.135 + im <= #1 csr_write_data[interrupts-1:0]; 1.136 if (csr == `LM32_CSR_IP) 1.137 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 1.138 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 1.139 end 1.140 end 1.141 end 1.142 @@ -269,61 +290,61 @@ 1.143 begin 1.144 if (rst_i == `TRUE) 1.145 begin 1.146 - ie <= `FALSE; 1.147 - eie <= `FALSE; 1.148 + ie <= #1 `FALSE; 1.149 + eie <= #1 `FALSE; 1.150 `ifdef CFG_DEBUG_ENABLED 1.151 - bie <= `FALSE; 1.152 + bie <= #1 `FALSE; 1.153 `endif 1.154 - ip <= {interrupts{1'b0}}; 1.155 + ip <= #1 {interrupts{1'b0}}; 1.156 end 1.157 else 1.158 begin 1.159 // Set IP bit when interrupt line is asserted 1.160 - ip <= asserted; 1.161 + ip <= #1 asserted; 1.162 `ifdef CFG_DEBUG_ENABLED 1.163 if (non_debug_exception == `TRUE) 1.164 begin 1.165 // Save and then clear interrupt enable 1.166 - eie <= ie; 1.167 - ie <= `FALSE; 1.168 + eie <= #1 ie; 1.169 + ie <= #1 `FALSE; 1.170 end 1.171 else if (debug_exception == `TRUE) 1.172 begin 1.173 // Save and then clear interrupt enable 1.174 - bie <= ie; 1.175 - ie <= `FALSE; 1.176 + bie <= #1 ie; 1.177 + ie <= #1 `FALSE; 1.178 end 1.179 `else 1.180 if (exception == `TRUE) 1.181 begin 1.182 // Save and then clear interrupt enable 1.183 - eie <= ie; 1.184 - ie <= `FALSE; 1.185 + eie <= #1 ie; 1.186 + ie <= #1 `FALSE; 1.187 end 1.188 `endif 1.189 else if (stall_x == `FALSE) 1.190 begin 1.191 if (eret_q_x == `TRUE) 1.192 // Restore interrupt enable 1.193 - ie <= eie; 1.194 + ie <= #1 eie; 1.195 `ifdef CFG_DEBUG_ENABLED 1.196 else if (bret_q_x == `TRUE) 1.197 // Restore interrupt enable 1.198 - ie <= bie; 1.199 + ie <= #1 bie; 1.200 `endif 1.201 else if (csr_write_enable == `TRUE) 1.202 begin 1.203 // Handle wcsr write 1.204 if (csr == `LM32_CSR_IE) 1.205 begin 1.206 - ie <= csr_write_data[0]; 1.207 - eie <= csr_write_data[1]; 1.208 + ie <= #1 csr_write_data[0]; 1.209 + eie <= #1 csr_write_data[1]; 1.210 `ifdef CFG_DEBUG_ENABLED 1.211 - bie <= csr_write_data[2]; 1.212 + bie <= #1 csr_write_data[2]; 1.213 `endif 1.214 end 1.215 if (csr == `LM32_CSR_IP) 1.216 - ip <= asserted & ~csr_write_data[interrupts-1:0]; 1.217 + ip <= #1 asserted & ~csr_write_data[interrupts-1:0]; 1.218 end 1.219 end 1.220 end