lm32_load_store_unit.v

changeset 26
73de224304c1
parent 8
07be9df9fee8
child 27
d6c693415d59
     1.1 diff -r 35dc7ba83714 -r 73de224304c1 lm32_load_store_unit.v
     1.2 --- a/lm32_load_store_unit.v	Sun Mar 06 21:14:43 2011 +0000
     1.3 +++ b/lm32_load_store_unit.v	Sat Aug 06 00:02:46 2011 +0100
     1.4 @@ -1,18 +1,39 @@
     1.5 -// =============================================================================
     1.6 -//                           COPYRIGHT NOTICE
     1.7 -// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.8 -// ALL RIGHTS RESERVED
     1.9 -// This confidential and proprietary software may be used only as authorised by
    1.10 -// a licensing agreement from Lattice Semiconductor Corporation.
    1.11 -// The entire notice above must be reproduced on all authorized copies and
    1.12 -// copies may only be made to the extent permitted by a licensing agreement from
    1.13 -// Lattice Semiconductor Corporation.
    1.14 +//   ==================================================================
    1.15 +//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
    1.16 +//   ------------------------------------------------------------------
    1.17 +//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
    1.18 +//   ALL RIGHTS RESERVED 
    1.19 +//   ------------------------------------------------------------------
    1.20 +//
    1.21 +//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
    1.22 +//
    1.23 +//   Permission:
    1.24 +//
    1.25 +//      Lattice Semiconductor grants permission to use this code
    1.26 +//      pursuant to the terms of the Lattice Semiconductor Corporation
    1.27 +//      Open Source License Agreement.  
    1.28 +//
    1.29 +//   Disclaimer:
    1.30  //
    1.31 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.32 -// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.33 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.34 -// U.S.A                                   email: techsupport@latticesemi.com
    1.35 -// =============================================================================/
    1.36 +//      Lattice Semiconductor provides no warranty regarding the use or
    1.37 +//      functionality of this code. It is the user's responsibility to
    1.38 +//      verify the userís design for consistency and functionality through
    1.39 +//      the use of formal verification methods.
    1.40 +//
    1.41 +//   --------------------------------------------------------------------
    1.42 +//
    1.43 +//                  Lattice Semiconductor Corporation
    1.44 +//                  5555 NE Moore Court
    1.45 +//                  Hillsboro, OR 97214
    1.46 +//                  U.S.A
    1.47 +//
    1.48 +//                  TEL: 1-800-Lattice (USA and Canada)
    1.49 +//                         503-286-8001 (other locations)
    1.50 +//
    1.51 +//                  web: http://www.latticesemi.com/
    1.52 +//                  email: techsupport@latticesemi.com
    1.53 +//
    1.54 +//   --------------------------------------------------------------------
    1.55  //                         FILE DETAILS
    1.56  // Project      : LatticeMico32
    1.57  // File         : lm32_load_store_unit.v
    1.58 @@ -302,8 +323,8 @@
    1.59  	    .ResetB                 (rst_i),
    1.60  	    .DataInA                ({32{1'b0}}),
    1.61  	    .DataInB                (dram_store_data_m),
    1.62 -	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
    1.63 -	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
    1.64 +	    .AddressA               (load_store_address_x[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
    1.65 +	    .AddressB               (load_store_address_m[clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
    1.66  	    // .ClockEnA               (!stall_x & (load_x | store_x)),
    1.67  	    .ClockEnA               (!stall_x),
    1.68  	    .ClockEnB               (!stall_m),
    1.69 @@ -322,13 +343,13 @@
    1.70     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.71       if (rst_i == `TRUE)
    1.72         begin
    1.73 -	  dram_bypass_en <= `FALSE;
    1.74 -	  dram_bypass_data <= 0;
    1.75 +	  dram_bypass_en <= #1 `FALSE;
    1.76 +	  dram_bypass_data <= #1 0;
    1.77         end
    1.78       else
    1.79         begin
    1.80  	  if (stall_x == `FALSE)
    1.81 -	    dram_bypass_data <= dram_store_data_m;
    1.82 +	    dram_bypass_data <= #1 dram_store_data_m;
    1.83  	  
    1.84  	  if (   (stall_m == `FALSE) 
    1.85                && (stall_x == `FALSE)
    1.86 @@ -338,12 +359,12 @@
    1.87  		 )
    1.88  	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
    1.89  	     )
    1.90 -	    dram_bypass_en <= `TRUE;
    1.91 +	    dram_bypass_en <= #1 `TRUE;
    1.92  	  else
    1.93  	    if (   (dram_bypass_en == `TRUE)
    1.94  		&& (stall_x == `FALSE)
    1.95  	       )
    1.96 -	      dram_bypass_en <= `FALSE;
    1.97 +	      dram_bypass_en <= #1 `FALSE;
    1.98         end
    1.99     
   1.100     assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
   1.101 @@ -603,26 +624,26 @@
   1.102  begin
   1.103      if (rst_i == `TRUE)
   1.104      begin
   1.105 -        d_cyc_o <= `FALSE;
   1.106 -        d_stb_o <= `FALSE;
   1.107 -        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.108 -        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.109 -        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   1.110 -        d_we_o <= `FALSE;
   1.111 -        d_cti_o <= `LM32_CTYPE_END;
   1.112 -        d_lock_o <= `FALSE;
   1.113 -        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.114 -        wb_load_complete <= `FALSE;
   1.115 -        stall_wb_load <= `FALSE;
   1.116 +        d_cyc_o <= #1 `FALSE;
   1.117 +        d_stb_o <= #1 `FALSE;
   1.118 +        d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.119 +        d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.120 +        d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   1.121 +        d_we_o <= #1 `FALSE;
   1.122 +        d_cti_o <= #1 `LM32_CTYPE_END;
   1.123 +        d_lock_o <= #1 `FALSE;
   1.124 +        wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.125 +        wb_load_complete <= #1 `FALSE;
   1.126 +        stall_wb_load <= #1 `FALSE;
   1.127  `ifdef CFG_DCACHE_ENABLED                
   1.128 -        dcache_refill_ready <= `FALSE;
   1.129 +        dcache_refill_ready <= #1 `FALSE;
   1.130  `endif                
   1.131      end
   1.132      else
   1.133      begin
   1.134  `ifdef CFG_DCACHE_ENABLED 
   1.135          // Refill ready should only be asserted for a single cycle               
   1.136 -        dcache_refill_ready <= `FALSE;
   1.137 +        dcache_refill_ready <= #1 `FALSE;
   1.138  `endif                
   1.139          // Is a Wishbone cycle already in progress?
   1.140          if (d_cyc_o == `TRUE)
   1.141 @@ -634,25 +655,25 @@
   1.142                  if ((dcache_refilling == `TRUE) && (!last_word))
   1.143                  begin
   1.144                      // Fetch next word of cache line    
   1.145 -                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.146 +                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.147                  end
   1.148                  else
   1.149  `endif                
   1.150                  begin
   1.151                      // Refill/access complete
   1.152 -                    d_cyc_o <= `FALSE;
   1.153 -                    d_stb_o <= `FALSE;
   1.154 -                    d_lock_o <= `FALSE;
   1.155 +                    d_cyc_o <= #1 `FALSE;
   1.156 +                    d_stb_o <= #1 `FALSE;
   1.157 +                    d_lock_o <= #1 `FALSE;
   1.158                  end
   1.159  `ifdef CFG_DCACHE_ENABLED    
   1.160 -                d_cti_o <= next_cycle_type;
   1.161 +                d_cti_o <= #1 next_cycle_type;
   1.162                  // If we are performing a refill, indicate to cache next word of data is ready            
   1.163 -                dcache_refill_ready <= dcache_refilling;
   1.164 +                dcache_refill_ready <= #1 dcache_refilling;
   1.165  `endif
   1.166                  // Register data read from Wishbone interface
   1.167 -                wb_data_m <= d_dat_i;
   1.168 +                wb_data_m <= #1 d_dat_i;
   1.169                  // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   1.170 -                wb_load_complete <= !d_we_o;
   1.171 +                wb_load_complete <= #1 !d_we_o;
   1.172              end
   1.173              // synthesis translate_off            
   1.174              if (d_err_i == `TRUE)
   1.175 @@ -665,13 +686,13 @@
   1.176              if (dcache_refill_request == `TRUE)
   1.177              begin
   1.178                  // Start cache refill
   1.179 -                d_adr_o <= first_address;
   1.180 -                d_cyc_o <= `TRUE;
   1.181 -                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   1.182 -                d_stb_o <= `TRUE;                
   1.183 -                d_we_o <= `FALSE;
   1.184 -                d_cti_o <= first_cycle_type;
   1.185 -                //d_lock_o <= `TRUE;
   1.186 +                d_adr_o <= #1 first_address;
   1.187 +                d_cyc_o <= #1 `TRUE;
   1.188 +                d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}};
   1.189 +                d_stb_o <= #1 `TRUE;                
   1.190 +                d_we_o <= #1 `FALSE;
   1.191 +                d_cti_o <= #1 first_cycle_type;
   1.192 +                //d_lock_o <= #1 `TRUE;
   1.193              end
   1.194              else 
   1.195  `endif            
   1.196 @@ -686,13 +707,13 @@
   1.197                      )
   1.198              begin
   1.199                  // Data cache is write through, so all stores go to memory
   1.200 -                d_dat_o <= store_data_m;
   1.201 -                d_adr_o <= load_store_address_m;
   1.202 -                d_cyc_o <= `TRUE;
   1.203 -                d_sel_o <= byte_enable_m;
   1.204 -                d_stb_o <= `TRUE;
   1.205 -                d_we_o <= `TRUE;
   1.206 -                d_cti_o <= `LM32_CTYPE_END;
   1.207 +                d_dat_o <= #1 store_data_m;
   1.208 +                d_adr_o <= #1 load_store_address_m;
   1.209 +                d_cyc_o <= #1 `TRUE;
   1.210 +                d_sel_o <= #1 byte_enable_m;
   1.211 +                d_stb_o <= #1 `TRUE;
   1.212 +                d_we_o <= #1 `TRUE;
   1.213 +                d_cti_o <= #1 `LM32_CTYPE_END;
   1.214              end        
   1.215              else if (   (load_q_m == `TRUE) 
   1.216                       && (wb_select_m == `TRUE) 
   1.217 @@ -701,24 +722,24 @@
   1.218                      )
   1.219              begin
   1.220                  // Read requested address
   1.221 -                stall_wb_load <= `FALSE;
   1.222 -                d_adr_o <= load_store_address_m;
   1.223 -                d_cyc_o <= `TRUE;
   1.224 -                d_sel_o <= byte_enable_m;
   1.225 -                d_stb_o <= `TRUE;
   1.226 -                d_we_o <= `FALSE;
   1.227 -                d_cti_o <= `LM32_CTYPE_END;
   1.228 +                stall_wb_load <= #1 `FALSE;
   1.229 +                d_adr_o <= #1 load_store_address_m;
   1.230 +                d_cyc_o <= #1 `TRUE;
   1.231 +                d_sel_o <= #1 byte_enable_m;
   1.232 +                d_stb_o <= #1 `TRUE;
   1.233 +                d_we_o <= #1 `FALSE;
   1.234 +                d_cti_o <= #1 `LM32_CTYPE_END;
   1.235              end
   1.236          end
   1.237          // Clear load/store complete flag when instruction leaves M stage
   1.238          if (stall_m == `FALSE)
   1.239 -            wb_load_complete <= `FALSE;
   1.240 +            wb_load_complete <= #1 `FALSE;
   1.241          // When a Wishbone load first enters the M stage, we need to stall it
   1.242          if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   1.243 -            stall_wb_load <= `TRUE;
   1.244 +            stall_wb_load <= #1 `TRUE;
   1.245          // Clear stall request if load instruction is killed
   1.246          if ((kill_m == `TRUE) || (exception_m == `TRUE))
   1.247 -            stall_wb_load <= `FALSE;
   1.248 +            stall_wb_load <= #1 `FALSE;
   1.249      end
   1.250  end
   1.251  
   1.252 @@ -729,39 +750,39 @@
   1.253  begin
   1.254      if (rst_i == `TRUE)
   1.255      begin
   1.256 -        sign_extend_m <= `FALSE;
   1.257 -        size_m <= 2'b00;
   1.258 -        byte_enable_m <= `FALSE;
   1.259 -        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.260 +        sign_extend_m <= #1 `FALSE;
   1.261 +        size_m <= #1 2'b00;
   1.262 +        byte_enable_m <= #1 `FALSE;
   1.263 +        store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.264  `ifdef CFG_DCACHE_ENABLED
   1.265 -        dcache_select_m <= `FALSE;
   1.266 +        dcache_select_m <= #1 `FALSE;
   1.267  `endif
   1.268  `ifdef CFG_DRAM_ENABLED
   1.269 -        dram_select_m <= `FALSE;
   1.270 +        dram_select_m <= #1 `FALSE;
   1.271  `endif
   1.272  `ifdef CFG_IROM_ENABLED
   1.273 -        irom_select_m <= `FALSE;
   1.274 +        irom_select_m <= #1 `FALSE;
   1.275  `endif
   1.276 -        wb_select_m <= `FALSE;        
   1.277 +        wb_select_m <= #1 `FALSE;        
   1.278      end
   1.279      else
   1.280      begin
   1.281          if (stall_m == `FALSE)
   1.282          begin
   1.283 -            sign_extend_m <= sign_extend_x;
   1.284 -            size_m <= size_x;
   1.285 -            byte_enable_m <= byte_enable_x;    
   1.286 -            store_data_m <= store_data_x;
   1.287 +            sign_extend_m <= #1 sign_extend_x;
   1.288 +            size_m <= #1 size_x;
   1.289 +            byte_enable_m <= #1 byte_enable_x;    
   1.290 +            store_data_m <= #1 store_data_x;
   1.291  `ifdef CFG_DCACHE_ENABLED
   1.292 -            dcache_select_m <= dcache_select_x;
   1.293 +            dcache_select_m <= #1 dcache_select_x;
   1.294  `endif
   1.295  `ifdef CFG_DRAM_ENABLED
   1.296 -            dram_select_m <= dram_select_x;
   1.297 +            dram_select_m <= #1 dram_select_x;
   1.298  `endif
   1.299  `ifdef CFG_IROM_ENABLED
   1.300 -            irom_select_m <= irom_select_x;
   1.301 +            irom_select_m <= #1 irom_select_x;
   1.302  `endif
   1.303 -            wb_select_m <= wb_select_x;
   1.304 +            wb_select_m <= #1 wb_select_x;
   1.305          end
   1.306      end
   1.307  end
   1.308 @@ -771,15 +792,15 @@
   1.309  begin
   1.310      if (rst_i == `TRUE)
   1.311      begin
   1.312 -        size_w <= 2'b00;
   1.313 -        data_w <= {`LM32_WORD_WIDTH{1'b0}};
   1.314 -        sign_extend_w <= `FALSE;
   1.315 +        size_w <= #1 2'b00;
   1.316 +        data_w <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.317 +        sign_extend_w <= #1 `FALSE;
   1.318      end
   1.319      else
   1.320      begin
   1.321 -        size_w <= size_m;
   1.322 -        data_w <= data_m;
   1.323 -        sign_extend_w <= sign_extend_m;
   1.324 +        size_w <= #1 size_m;
   1.325 +        data_w <= #1 data_m;
   1.326 +        sign_extend_w <= #1 sign_extend_m;
   1.327      end
   1.328  end
   1.329