lm32_cpu.v

changeset 18
cc945f778cd7
parent 14
54dd95f89113
child 23
252df75c8f67
     1.1 diff -r 50bf3061dbff -r cc945f778cd7 lm32_cpu.v
     1.2 --- a/lm32_cpu.v	Sun Mar 06 19:49:17 2011 +0000
     1.3 +++ b/lm32_cpu.v	Sun Mar 06 21:03:32 2011 +0000
     1.4 @@ -1269,70 +1269,44 @@
     1.5     /*----------------------------------------------------------------------
     1.6      Register file instantiation as Pseudo-Dual Port EBRs.
     1.7      ----------------------------------------------------------------------*/
     1.8 -   pmi_ram_dp
     1.9 +   // Modified by GSI: removed non-portable RAM instantiation
    1.10 +   lm32_dp_ram
    1.11       #(
    1.12         // ----- Parameters -----
    1.13 -       .pmi_wr_addr_depth(1<<5),
    1.14 -       .pmi_wr_addr_width(5),
    1.15 -       .pmi_wr_data_width(32),
    1.16 -       .pmi_rd_addr_depth(1<<5),
    1.17 -       .pmi_rd_addr_width(5),
    1.18 -       .pmi_rd_data_width(32),
    1.19 -       .pmi_regmode("noreg"),
    1.20 -       .pmi_gsr("enable"),
    1.21 -       .pmi_resetmode("sync"),
    1.22 -       .pmi_init_file("none"),
    1.23 -       .pmi_init_file_format("binary"),
    1.24 -       .pmi_family(`LATTICE_FAMILY),
    1.25 -       .module_type("pmi_ram_dp")
    1.26 +       .addr_depth(1<<5),
    1.27 +       .addr_width(5),
    1.28 +       .data_width(32)
    1.29         )
    1.30     reg_0
    1.31       (
    1.32        // ----- Inputs -----
    1.33 -      .Data(w_result),
    1.34 -      .WrAddress(write_idx_w),
    1.35 -      .RdAddress(instruction_f[25:21]),
    1.36 -      .WrClock(clk_i),
    1.37 -      .RdClock(clk_i),
    1.38 -      .WrClockEn(`TRUE),
    1.39 -      .RdClockEn(`TRUE),
    1.40 -      .WE(reg_write_enable_q_w),
    1.41 -      .Reset(rst_i), 
    1.42 +      .clk_i	(clk_i),
    1.43 +      .rst_i	(rst_i), 
    1.44 +      .we_i	(reg_write_enable_q_w),
    1.45 +      .wdata_i	(w_result),
    1.46 +      .waddr_i	(write_idx_w),
    1.47 +      .raddr_i	(instruction_f[25:21]),
    1.48        // ----- Outputs -----
    1.49 -      .Q(regfile_data_0)
    1.50 +      .rdata_o	(regfile_data_0)
    1.51        );
    1.52  
    1.53 -   pmi_ram_dp
    1.54 +   lm32_dp_ram
    1.55       #(
    1.56 -       // ----- Parameters -----
    1.57 -       .pmi_wr_addr_depth(1<<5),
    1.58 -       .pmi_wr_addr_width(5),
    1.59 -       .pmi_wr_data_width(32),
    1.60 -       .pmi_rd_addr_depth(1<<5),
    1.61 -       .pmi_rd_addr_width(5),
    1.62 -       .pmi_rd_data_width(32),
    1.63 -       .pmi_regmode("noreg"),
    1.64 -       .pmi_gsr("enable"),
    1.65 -       .pmi_resetmode("sync"),
    1.66 -       .pmi_init_file("none"),
    1.67 -       .pmi_init_file_format("binary"),
    1.68 -       .pmi_family(`LATTICE_FAMILY),
    1.69 -       .module_type("pmi_ram_dp")
    1.70 +       .addr_depth(1<<5),
    1.71 +       .addr_width(5),
    1.72 +       .data_width(32)
    1.73         )
    1.74     reg_1
    1.75       (
    1.76        // ----- Inputs -----
    1.77 -      .Data(w_result),
    1.78 -      .WrAddress(write_idx_w),
    1.79 -      .RdAddress(instruction_f[20:16]),
    1.80 -      .WrClock(clk_i),
    1.81 -      .RdClock(clk_i),
    1.82 -      .WrClockEn(`TRUE),
    1.83 -      .RdClockEn(`TRUE),
    1.84 -      .WE(reg_write_enable_q_w),
    1.85 -      .Reset(rst_i), 
    1.86 +      .clk_i	(clk_i),
    1.87 +      .rst_i	(rst_i), 
    1.88 +      .we_i	(reg_write_enable_q_w),
    1.89 +      .wdata_i	(w_result),
    1.90 +      .waddr_i	(write_idx_w),
    1.91 +      .raddr_i	(instruction_f[20:16]),
    1.92        // ----- Outputs -----
    1.93 -      .Q(regfile_data_1)
    1.94 +      .rdata_o	(regfile_data_1)
    1.95        );
    1.96  `endif
    1.97  
    1.98 @@ -1882,7 +1856,9 @@
    1.99  			  exception has occured. This stall will ensure that D_CYC_O and 
   1.100  			  store_m will both be low for one cycle.
   1.101  			  */
   1.102 +`ifdef CFG_INTERRUPTS_ENABLED
   1.103  		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
   1.104 +`endif
   1.105                           || (load_m == `TRUE)
   1.106                           || (load_x == `TRUE)
   1.107                          ) 
   1.108 @@ -2042,15 +2018,29 @@
   1.109     
   1.110  // Cache flush
   1.111  `ifdef CFG_ICACHE_ENABLED
   1.112 -assign iflush =    (csr_write_enable_d == `TRUE) 
   1.113 -                && (csr_d == `LM32_CSR_ICC)
   1.114 -                && (stall_d == `FALSE)
   1.115 -                && (kill_d == `FALSE)
   1.116 -                && (valid_d == `TRUE);
   1.117 +assign iflush = (   (csr_write_enable_d == `TRUE) 
   1.118 +                 && (csr_d == `LM32_CSR_ICC)
   1.119 +                 && (stall_d == `FALSE)
   1.120 +                 && (kill_d == `FALSE)
   1.121 +                 && (valid_d == `TRUE))
   1.122 +// Added by GSI: needed to flush cache after loading firmware per JTAG
   1.123 +`ifdef CFG_HW_DEBUG_ENABLED
   1.124 +             ||
   1.125 +                (   (jtag_csr_write_enable == `TRUE)
   1.126 +		 && (jtag_csr == `LM32_CSR_ICC))
   1.127 +`endif
   1.128 +		 ;
   1.129  `endif 
   1.130  `ifdef CFG_DCACHE_ENABLED
   1.131 -assign dflush_x =  (csr_write_enable_q_x == `TRUE) 
   1.132 -                && (csr_x == `LM32_CSR_DCC);
   1.133 +assign dflush_x = (   (csr_write_enable_q_x == `TRUE) 
   1.134 +                   && (csr_x == `LM32_CSR_DCC))
   1.135 +// Added by GSI: needed to flush cache after loading firmware per JTAG
   1.136 +`ifdef CFG_HW_DEBUG_ENABLED
   1.137 +               ||
   1.138 +                  (   (jtag_csr_write_enable == `TRUE)
   1.139 +		   && (jtag_csr == `LM32_CSR_DCC))
   1.140 +`endif
   1.141 +		   ;
   1.142  `endif 
   1.143  
   1.144  // Extract CSR index
   1.145 @@ -2252,7 +2242,7 @@
   1.146          operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.147          operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.148          store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.149 -        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
   1.150 +        branch_target_x <= {`LM32_PC_WIDTH{1'b0}};        
   1.151          x_result_sel_csr_x <= `FALSE;
   1.152  `ifdef LM32_MC_ARITHMETIC_ENABLED
   1.153          x_result_sel_mc_arith_x <= `FALSE;
   1.154 @@ -2313,7 +2303,7 @@
   1.155  `endif
   1.156          csr_write_enable_x <= `FALSE;
   1.157          operand_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.158 -        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.159 +        branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
   1.160          m_result_sel_compare_m <= `FALSE;
   1.161  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.162          m_result_sel_shift_m <= `FALSE;