lm32_dcache.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_dcache.v
     1.2 --- a/lm32_dcache.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 +++ b/lm32_dcache.v	Sat Aug 06 01:26:56 2011 +0100
     1.4 @@ -441,11 +441,11 @@
     1.5  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
     1.6  begin
     1.7      if (rst_i == `TRUE)
     1.8 -        refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1};
     1.9 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
    1.10      else
    1.11      begin        
    1.12          if (refill_request == `TRUE)
    1.13 -            refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]};
    1.14 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
    1.15      end
    1.16  end
    1.17      end 
    1.18 @@ -455,9 +455,9 @@
    1.19  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.20  begin
    1.21      if (rst_i == `TRUE)
    1.22 -        refilling <= #1 `FALSE;
    1.23 +        refilling <= `FALSE;
    1.24      else 
    1.25 -        refilling <= #1 refill;
    1.26 +        refilling <= refill;
    1.27  end
    1.28  
    1.29  // Instruction cache control FSM
    1.30 @@ -465,11 +465,11 @@
    1.31  begin
    1.32      if (rst_i == `TRUE)
    1.33      begin
    1.34 -        state <= #1 `LM32_DC_STATE_FLUSH;
    1.35 -        flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
    1.36 -        refill_request <= #1 `FALSE;
    1.37 -        refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.38 -        restart_request <= #1 `FALSE;
    1.39 +        state <= `LM32_DC_STATE_FLUSH;
    1.40 +        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
    1.41 +        refill_request <= `FALSE;
    1.42 +        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
    1.43 +        restart_request <= `FALSE;
    1.44      end
    1.45      else 
    1.46      begin
    1.47 @@ -479,35 +479,35 @@
    1.48          `LM32_DC_STATE_FLUSH:
    1.49          begin
    1.50              if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
    1.51 -                state <= #1 `LM32_DC_STATE_CHECK;
    1.52 -            flush_set <= #1 flush_set - 1'b1;
    1.53 +                state <= `LM32_DC_STATE_CHECK;
    1.54 +            flush_set <= flush_set - 1'b1;
    1.55          end
    1.56          
    1.57          // Check for cache misses
    1.58          `LM32_DC_STATE_CHECK:
    1.59          begin
    1.60              if (stall_a == `FALSE)
    1.61 -                restart_request <= #1 `FALSE;
    1.62 +                restart_request <= `FALSE;
    1.63              if (miss == `TRUE)
    1.64              begin
    1.65 -                refill_request <= #1 `TRUE;
    1.66 -                refill_address <= #1 address_m;
    1.67 -                state <= #1 `LM32_DC_STATE_REFILL;
    1.68 +                refill_request <= `TRUE;
    1.69 +                refill_address <= address_m;
    1.70 +                state <= `LM32_DC_STATE_REFILL;
    1.71              end
    1.72              else if (dflush == `TRUE)
    1.73 -                state <= #1 `LM32_DC_STATE_FLUSH;
    1.74 +                state <= `LM32_DC_STATE_FLUSH;
    1.75          end
    1.76  
    1.77          // Refill a cache line
    1.78          `LM32_DC_STATE_REFILL:
    1.79          begin
    1.80 -            refill_request <= #1 `FALSE;
    1.81 +            refill_request <= `FALSE;
    1.82              if (refill_ready == `TRUE)
    1.83              begin
    1.84                  if (last_refill == `TRUE)
    1.85                  begin
    1.86 -                    restart_request <= #1 `TRUE;
    1.87 -                    state <= #1 `LM32_DC_STATE_CHECK;
    1.88 +                    restart_request <= `TRUE;
    1.89 +                    state <= `LM32_DC_STATE_CHECK;
    1.90                  end
    1.91              end
    1.92          end
    1.93 @@ -523,7 +523,7 @@
    1.94  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.95  begin
    1.96      if (rst_i == `TRUE)
    1.97 -        refill_offset <= #1 {addr_offset_width{1'b0}};
    1.98 +        refill_offset <= {addr_offset_width{1'b0}};
    1.99      else 
   1.100      begin
   1.101          case (state)
   1.102 @@ -532,14 +532,14 @@
   1.103          `LM32_DC_STATE_CHECK:
   1.104          begin
   1.105              if (miss == `TRUE)
   1.106 -                refill_offset <= #1 {addr_offset_width{1'b0}};
   1.107 +                refill_offset <= {addr_offset_width{1'b0}};
   1.108          end
   1.109  
   1.110          // Refill a cache line
   1.111          `LM32_DC_STATE_REFILL:
   1.112          begin
   1.113              if (refill_ready == `TRUE)
   1.114 -                refill_offset <= #1 refill_offset + 1'b1;
   1.115 +                refill_offset <= refill_offset + 1'b1;
   1.116          end
   1.117          
   1.118          endcase