lm32_debug.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_debug.v
     1.2 --- a/lm32_debug.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 +++ b/lm32_debug.v	Sat Aug 06 01:26:56 2011 +0100
     1.4 @@ -247,15 +247,15 @@
     1.5  begin
     1.6      if (rst_i == `TRUE)
     1.7      begin
     1.8 -        bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}};
     1.9 -        bp_e[i] <= #1 `FALSE;
    1.10 +        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
    1.11 +        bp_e[i] <= `FALSE;
    1.12      end
    1.13      else
    1.14      begin
    1.15          if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
    1.16          begin
    1.17 -            bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG];
    1.18 -            bp_e[i] <= #1 debug_csr_write_data[0];
    1.19 +            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
    1.20 +            bp_e[i] <= debug_csr_write_data[0];
    1.21          end
    1.22      end
    1.23  end    
    1.24 @@ -270,17 +270,17 @@
    1.25  begin
    1.26      if (rst_i == `TRUE)
    1.27      begin
    1.28 -        wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.29 -        wpc_c[i] <= #1 `LM32_WPC_C_DISABLED;
    1.30 +        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
    1.31 +        wpc_c[i] <= `LM32_WPC_C_DISABLED;
    1.32      end
    1.33      else
    1.34      begin
    1.35          if (debug_csr_write_enable == `TRUE)
    1.36          begin
    1.37              if (debug_csr == `LM32_CSR_DC)
    1.38 -                wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2];
    1.39 +                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
    1.40              if (debug_csr == `LM32_CSR_WP0 + i)
    1.41 -                wp[i] <= #1 debug_csr_write_data;
    1.42 +                wp[i] <= debug_csr_write_data;
    1.43          end
    1.44      end  
    1.45  end
    1.46 @@ -291,11 +291,11 @@
    1.47  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.48  begin
    1.49      if (rst_i == `TRUE)
    1.50 -        dc_re <= #1 `FALSE;
    1.51 +        dc_re <= `FALSE;
    1.52      else
    1.53      begin
    1.54          if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
    1.55 -            dc_re <= #1 debug_csr_write_data[1];
    1.56 +            dc_re <= debug_csr_write_data[1];
    1.57      end
    1.58  end    
    1.59  
    1.60 @@ -305,18 +305,18 @@
    1.61  begin
    1.62      if (rst_i == `TRUE)
    1.63      begin
    1.64 -        state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
    1.65 -        dc_ss <= #1 `FALSE;
    1.66 +        state <= `LM32_DEBUG_SS_STATE_IDLE;
    1.67 +        dc_ss <= `FALSE;
    1.68      end
    1.69      else
    1.70      begin
    1.71          if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
    1.72          begin
    1.73 -            dc_ss <= #1 debug_csr_write_data[0];
    1.74 +            dc_ss <= debug_csr_write_data[0];
    1.75              if (debug_csr_write_data[0] == `FALSE) 
    1.76 -                state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
    1.77 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
    1.78              else 
    1.79 -                state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
    1.80 +                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
    1.81          end
    1.82          case (state)
    1.83          `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
    1.84 @@ -327,26 +327,26 @@
    1.85                      )
    1.86                  && (stall_x == `FALSE)
    1.87                 )
    1.88 -                state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
    1.89 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
    1.90          end
    1.91          `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
    1.92          begin
    1.93              // Wait for an instruction to be executed
    1.94              if ((q_x == `TRUE) && (stall_x == `FALSE))
    1.95 -                state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
    1.96 +                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
    1.97          end
    1.98          `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
    1.99          begin
   1.100              // Wait for exception to be raised
   1.101  `ifdef CFG_DCACHE_ENABLED
   1.102              if (dcache_refill_request == `TRUE)
   1.103 -                state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   1.104 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   1.105              else 
   1.106  `endif
   1.107                   if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
   1.108              begin
   1.109 -                dc_ss <= #1 `FALSE;
   1.110 -                state <= #1 `LM32_DEBUG_SS_STATE_RESTART;
   1.111 +                dc_ss <= `FALSE;
   1.112 +                state <= `LM32_DEBUG_SS_STATE_RESTART;
   1.113              end
   1.114          end
   1.115          `LM32_DEBUG_SS_STATE_RESTART:
   1.116 @@ -354,10 +354,10 @@
   1.117              // Watch to see if stepped instruction is restarted due to a cache miss
   1.118  `ifdef CFG_DCACHE_ENABLED
   1.119              if (dcache_refill_request == `TRUE)
   1.120 -                state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   1.121 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   1.122              else 
   1.123  `endif
   1.124 -                state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
   1.125 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
   1.126          end
   1.127          endcase
   1.128      end