lm32_interrupt.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_interrupt.v
     1.2 --- a/lm32_interrupt.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 +++ b/lm32_interrupt.v	Sat Aug 06 01:26:56 2011 +0100
     1.4 @@ -220,64 +220,64 @@
     1.5  begin
     1.6      if (rst_i == `TRUE)
     1.7      begin
     1.8 -        ie <= #1 `FALSE;
     1.9 -        eie <= #1 `FALSE;
    1.10 +        ie <= `FALSE;
    1.11 +        eie <= `FALSE;
    1.12  `ifdef CFG_DEBUG_ENABLED
    1.13 -        bie <= #1 `FALSE;
    1.14 +        bie <= `FALSE;
    1.15  `endif
    1.16 -        im <= #1 {interrupts{1'b0}};
    1.17 -        ip <= #1 {interrupts{1'b0}};
    1.18 +        im <= {interrupts{1'b0}};
    1.19 +        ip <= {interrupts{1'b0}};
    1.20      end
    1.21      else
    1.22      begin
    1.23          // Set IP bit when interrupt line is asserted
    1.24 -        ip <= #1 asserted;
    1.25 +        ip <= asserted;
    1.26  `ifdef CFG_DEBUG_ENABLED
    1.27          if (non_debug_exception == `TRUE)
    1.28          begin
    1.29              // Save and then clear interrupt enable
    1.30 -            eie <= #1 ie;
    1.31 -            ie <= #1 `FALSE;
    1.32 +            eie <= ie;
    1.33 +            ie <= `FALSE;
    1.34          end
    1.35          else if (debug_exception == `TRUE)
    1.36          begin
    1.37              // Save and then clear interrupt enable
    1.38 -            bie <= #1 ie;
    1.39 -            ie <= #1 `FALSE;
    1.40 +            bie <= ie;
    1.41 +            ie <= `FALSE;
    1.42          end
    1.43  `else
    1.44          if (exception == `TRUE)
    1.45          begin
    1.46              // Save and then clear interrupt enable
    1.47 -            eie <= #1 ie;
    1.48 -            ie <= #1 `FALSE;
    1.49 +            eie <= ie;
    1.50 +            ie <= `FALSE;
    1.51          end
    1.52  `endif
    1.53          else if (stall_x == `FALSE)
    1.54          begin
    1.55              if (eret_q_x == `TRUE)
    1.56                  // Restore interrupt enable
    1.57 -                ie <= #1 eie;          
    1.58 +                ie <= eie;          
    1.59  `ifdef CFG_DEBUG_ENABLED
    1.60              else if (bret_q_x == `TRUE)
    1.61                  // Restore interrupt enable
    1.62 -                ie <= #1 bie;
    1.63 +                ie <= bie;
    1.64  `endif
    1.65              else if (csr_write_enable == `TRUE)
    1.66              begin
    1.67                  // Handle wcsr write
    1.68                  if (csr == `LM32_CSR_IE)
    1.69                  begin
    1.70 -                    ie <= #1 csr_write_data[0];
    1.71 -                    eie <= #1 csr_write_data[1];
    1.72 +                    ie <= csr_write_data[0];
    1.73 +                    eie <= csr_write_data[1];
    1.74  `ifdef CFG_DEBUG_ENABLED
    1.75 -                    bie <= #1 csr_write_data[2];
    1.76 +                    bie <= csr_write_data[2];
    1.77  `endif
    1.78                  end
    1.79                  if (csr == `LM32_CSR_IM)
    1.80 -                    im <= #1 csr_write_data[interrupts-1:0];
    1.81 +                    im <= csr_write_data[interrupts-1:0];
    1.82                  if (csr == `LM32_CSR_IP)
    1.83 -                    ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
    1.84 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
    1.85              end
    1.86          end
    1.87      end
    1.88 @@ -290,61 +290,61 @@
    1.89  begin
    1.90      if (rst_i == `TRUE)
    1.91      begin
    1.92 -        ie <= #1 `FALSE;
    1.93 -        eie <= #1 `FALSE;
    1.94 +        ie <= `FALSE;
    1.95 +        eie <= `FALSE;
    1.96  `ifdef CFG_DEBUG_ENABLED
    1.97 -        bie <= #1 `FALSE;
    1.98 +        bie <= `FALSE;
    1.99  `endif
   1.100 -        ip <= #1 {interrupts{1'b0}};
   1.101 +        ip <= {interrupts{1'b0}};
   1.102      end
   1.103      else
   1.104      begin
   1.105          // Set IP bit when interrupt line is asserted
   1.106 -        ip <= #1 asserted;
   1.107 +        ip <= asserted;
   1.108  `ifdef CFG_DEBUG_ENABLED
   1.109          if (non_debug_exception == `TRUE)
   1.110          begin
   1.111              // Save and then clear interrupt enable
   1.112 -            eie <= #1 ie;
   1.113 -            ie <= #1 `FALSE;
   1.114 +            eie <= ie;
   1.115 +            ie <= `FALSE;
   1.116          end
   1.117          else if (debug_exception == `TRUE)
   1.118          begin
   1.119              // Save and then clear interrupt enable
   1.120 -            bie <= #1 ie;
   1.121 -            ie <= #1 `FALSE;
   1.122 +            bie <= ie;
   1.123 +            ie <= `FALSE;
   1.124          end
   1.125  `else
   1.126          if (exception == `TRUE)
   1.127          begin
   1.128              // Save and then clear interrupt enable
   1.129 -            eie <= #1 ie;
   1.130 -            ie <= #1 `FALSE;
   1.131 +            eie <= ie;
   1.132 +            ie <= `FALSE;
   1.133          end
   1.134  `endif
   1.135          else if (stall_x == `FALSE)
   1.136          begin
   1.137              if (eret_q_x == `TRUE)
   1.138                  // Restore interrupt enable
   1.139 -                ie <= #1 eie;          
   1.140 +                ie <= eie;          
   1.141  `ifdef CFG_DEBUG_ENABLED
   1.142              else if (bret_q_x == `TRUE)
   1.143                  // Restore interrupt enable
   1.144 -                ie <= #1 bie;
   1.145 +                ie <= bie;
   1.146  `endif
   1.147              else if (csr_write_enable == `TRUE)
   1.148              begin
   1.149                  // Handle wcsr write
   1.150                  if (csr == `LM32_CSR_IE)
   1.151                  begin
   1.152 -                    ie <= #1 csr_write_data[0];
   1.153 -                    eie <= #1 csr_write_data[1];
   1.154 +                    ie <= csr_write_data[0];
   1.155 +                    eie <= csr_write_data[1];
   1.156  `ifdef CFG_DEBUG_ENABLED
   1.157 -                    bie <= #1 csr_write_data[2];
   1.158 +                    bie <= csr_write_data[2];
   1.159  `endif
   1.160                  end
   1.161                  if (csr == `LM32_CSR_IP)
   1.162 -                    ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
   1.163 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
   1.164              end
   1.165          end
   1.166      end