lm32_load_store_unit.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_load_store_unit.v
     1.2 --- a/lm32_load_store_unit.v	Sat Aug 06 00:02:46 2011 +0100
     1.3 +++ b/lm32_load_store_unit.v	Sat Aug 06 01:26:56 2011 +0100
     1.4 @@ -343,13 +343,13 @@
     1.5     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
     1.6       if (rst_i == `TRUE)
     1.7         begin
     1.8 -	  dram_bypass_en <= #1 `FALSE;
     1.9 -	  dram_bypass_data <= #1 0;
    1.10 +	  dram_bypass_en <= `FALSE;
    1.11 +	  dram_bypass_data <= 0;
    1.12         end
    1.13       else
    1.14         begin
    1.15  	  if (stall_x == `FALSE)
    1.16 -	    dram_bypass_data <= #1 dram_store_data_m;
    1.17 +	    dram_bypass_data <= dram_store_data_m;
    1.18  	  
    1.19  	  if (   (stall_m == `FALSE) 
    1.20                && (stall_x == `FALSE)
    1.21 @@ -359,12 +359,12 @@
    1.22  		 )
    1.23  	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
    1.24  	     )
    1.25 -	    dram_bypass_en <= #1 `TRUE;
    1.26 +	    dram_bypass_en <= `TRUE;
    1.27  	  else
    1.28  	    if (   (dram_bypass_en == `TRUE)
    1.29  		&& (stall_x == `FALSE)
    1.30  	       )
    1.31 -	      dram_bypass_en <= #1 `FALSE;
    1.32 +	      dram_bypass_en <= `FALSE;
    1.33         end
    1.34     
    1.35     assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
    1.36 @@ -624,26 +624,26 @@
    1.37  begin
    1.38      if (rst_i == `TRUE)
    1.39      begin
    1.40 -        d_cyc_o <= #1 `FALSE;
    1.41 -        d_stb_o <= #1 `FALSE;
    1.42 -        d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.43 -        d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.44 -        d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
    1.45 -        d_we_o <= #1 `FALSE;
    1.46 -        d_cti_o <= #1 `LM32_CTYPE_END;
    1.47 -        d_lock_o <= #1 `FALSE;
    1.48 -        wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.49 -        wb_load_complete <= #1 `FALSE;
    1.50 -        stall_wb_load <= #1 `FALSE;
    1.51 +        d_cyc_o <= `FALSE;
    1.52 +        d_stb_o <= `FALSE;
    1.53 +        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
    1.54 +        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
    1.55 +        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
    1.56 +        d_we_o <= `FALSE;
    1.57 +        d_cti_o <= `LM32_CTYPE_END;
    1.58 +        d_lock_o <= `FALSE;
    1.59 +        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
    1.60 +        wb_load_complete <= `FALSE;
    1.61 +        stall_wb_load <= `FALSE;
    1.62  `ifdef CFG_DCACHE_ENABLED                
    1.63 -        dcache_refill_ready <= #1 `FALSE;
    1.64 +        dcache_refill_ready <= `FALSE;
    1.65  `endif                
    1.66      end
    1.67      else
    1.68      begin
    1.69  `ifdef CFG_DCACHE_ENABLED 
    1.70          // Refill ready should only be asserted for a single cycle               
    1.71 -        dcache_refill_ready <= #1 `FALSE;
    1.72 +        dcache_refill_ready <= `FALSE;
    1.73  `endif                
    1.74          // Is a Wishbone cycle already in progress?
    1.75          if (d_cyc_o == `TRUE)
    1.76 @@ -655,25 +655,25 @@
    1.77                  if ((dcache_refilling == `TRUE) && (!last_word))
    1.78                  begin
    1.79                      // Fetch next word of cache line    
    1.80 -                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
    1.81 +                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
    1.82                  end
    1.83                  else
    1.84  `endif                
    1.85                  begin
    1.86                      // Refill/access complete
    1.87 -                    d_cyc_o <= #1 `FALSE;
    1.88 -                    d_stb_o <= #1 `FALSE;
    1.89 -                    d_lock_o <= #1 `FALSE;
    1.90 +                    d_cyc_o <= `FALSE;
    1.91 +                    d_stb_o <= `FALSE;
    1.92 +                    d_lock_o <= `FALSE;
    1.93                  end
    1.94  `ifdef CFG_DCACHE_ENABLED    
    1.95 -                d_cti_o <= #1 next_cycle_type;
    1.96 +                d_cti_o <= next_cycle_type;
    1.97                  // If we are performing a refill, indicate to cache next word of data is ready            
    1.98 -                dcache_refill_ready <= #1 dcache_refilling;
    1.99 +                dcache_refill_ready <= dcache_refilling;
   1.100  `endif
   1.101                  // Register data read from Wishbone interface
   1.102 -                wb_data_m <= #1 d_dat_i;
   1.103 +                wb_data_m <= d_dat_i;
   1.104                  // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   1.105 -                wb_load_complete <= #1 !d_we_o;
   1.106 +                wb_load_complete <= !d_we_o;
   1.107              end
   1.108              // synthesis translate_off            
   1.109              if (d_err_i == `TRUE)
   1.110 @@ -686,13 +686,13 @@
   1.111              if (dcache_refill_request == `TRUE)
   1.112              begin
   1.113                  // Start cache refill
   1.114 -                d_adr_o <= #1 first_address;
   1.115 -                d_cyc_o <= #1 `TRUE;
   1.116 -                d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}};
   1.117 -                d_stb_o <= #1 `TRUE;                
   1.118 -                d_we_o <= #1 `FALSE;
   1.119 -                d_cti_o <= #1 first_cycle_type;
   1.120 -                //d_lock_o <= #1 `TRUE;
   1.121 +                d_adr_o <= first_address;
   1.122 +                d_cyc_o <= `TRUE;
   1.123 +                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   1.124 +                d_stb_o <= `TRUE;                
   1.125 +                d_we_o <= `FALSE;
   1.126 +                d_cti_o <= first_cycle_type;
   1.127 +                //d_lock_o <= `TRUE;
   1.128              end
   1.129              else 
   1.130  `endif            
   1.131 @@ -707,13 +707,13 @@
   1.132                      )
   1.133              begin
   1.134                  // Data cache is write through, so all stores go to memory
   1.135 -                d_dat_o <= #1 store_data_m;
   1.136 -                d_adr_o <= #1 load_store_address_m;
   1.137 -                d_cyc_o <= #1 `TRUE;
   1.138 -                d_sel_o <= #1 byte_enable_m;
   1.139 -                d_stb_o <= #1 `TRUE;
   1.140 -                d_we_o <= #1 `TRUE;
   1.141 -                d_cti_o <= #1 `LM32_CTYPE_END;
   1.142 +                d_dat_o <= store_data_m;
   1.143 +                d_adr_o <= load_store_address_m;
   1.144 +                d_cyc_o <= `TRUE;
   1.145 +                d_sel_o <= byte_enable_m;
   1.146 +                d_stb_o <= `TRUE;
   1.147 +                d_we_o <= `TRUE;
   1.148 +                d_cti_o <= `LM32_CTYPE_END;
   1.149              end        
   1.150              else if (   (load_q_m == `TRUE) 
   1.151                       && (wb_select_m == `TRUE) 
   1.152 @@ -722,24 +722,24 @@
   1.153                      )
   1.154              begin
   1.155                  // Read requested address
   1.156 -                stall_wb_load <= #1 `FALSE;
   1.157 -                d_adr_o <= #1 load_store_address_m;
   1.158 -                d_cyc_o <= #1 `TRUE;
   1.159 -                d_sel_o <= #1 byte_enable_m;
   1.160 -                d_stb_o <= #1 `TRUE;
   1.161 -                d_we_o <= #1 `FALSE;
   1.162 -                d_cti_o <= #1 `LM32_CTYPE_END;
   1.163 +                stall_wb_load <= `FALSE;
   1.164 +                d_adr_o <= load_store_address_m;
   1.165 +                d_cyc_o <= `TRUE;
   1.166 +                d_sel_o <= byte_enable_m;
   1.167 +                d_stb_o <= `TRUE;
   1.168 +                d_we_o <= `FALSE;
   1.169 +                d_cti_o <= `LM32_CTYPE_END;
   1.170              end
   1.171          end
   1.172          // Clear load/store complete flag when instruction leaves M stage
   1.173          if (stall_m == `FALSE)
   1.174 -            wb_load_complete <= #1 `FALSE;
   1.175 +            wb_load_complete <= `FALSE;
   1.176          // When a Wishbone load first enters the M stage, we need to stall it
   1.177          if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   1.178 -            stall_wb_load <= #1 `TRUE;
   1.179 +            stall_wb_load <= `TRUE;
   1.180          // Clear stall request if load instruction is killed
   1.181          if ((kill_m == `TRUE) || (exception_m == `TRUE))
   1.182 -            stall_wb_load <= #1 `FALSE;
   1.183 +            stall_wb_load <= `FALSE;
   1.184      end
   1.185  end
   1.186  
   1.187 @@ -750,39 +750,39 @@
   1.188  begin
   1.189      if (rst_i == `TRUE)
   1.190      begin
   1.191 -        sign_extend_m <= #1 `FALSE;
   1.192 -        size_m <= #1 2'b00;
   1.193 -        byte_enable_m <= #1 `FALSE;
   1.194 -        store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.195 +        sign_extend_m <= `FALSE;
   1.196 +        size_m <= 2'b00;
   1.197 +        byte_enable_m <= `FALSE;
   1.198 +        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.199  `ifdef CFG_DCACHE_ENABLED
   1.200 -        dcache_select_m <= #1 `FALSE;
   1.201 +        dcache_select_m <= `FALSE;
   1.202  `endif
   1.203  `ifdef CFG_DRAM_ENABLED
   1.204 -        dram_select_m <= #1 `FALSE;
   1.205 +        dram_select_m <= `FALSE;
   1.206  `endif
   1.207  `ifdef CFG_IROM_ENABLED
   1.208 -        irom_select_m <= #1 `FALSE;
   1.209 +        irom_select_m <= `FALSE;
   1.210  `endif
   1.211 -        wb_select_m <= #1 `FALSE;        
   1.212 +        wb_select_m <= `FALSE;        
   1.213      end
   1.214      else
   1.215      begin
   1.216          if (stall_m == `FALSE)
   1.217          begin
   1.218 -            sign_extend_m <= #1 sign_extend_x;
   1.219 -            size_m <= #1 size_x;
   1.220 -            byte_enable_m <= #1 byte_enable_x;    
   1.221 -            store_data_m <= #1 store_data_x;
   1.222 +            sign_extend_m <= sign_extend_x;
   1.223 +            size_m <= size_x;
   1.224 +            byte_enable_m <= byte_enable_x;    
   1.225 +            store_data_m <= store_data_x;
   1.226  `ifdef CFG_DCACHE_ENABLED
   1.227 -            dcache_select_m <= #1 dcache_select_x;
   1.228 +            dcache_select_m <= dcache_select_x;
   1.229  `endif
   1.230  `ifdef CFG_DRAM_ENABLED
   1.231 -            dram_select_m <= #1 dram_select_x;
   1.232 +            dram_select_m <= dram_select_x;
   1.233  `endif
   1.234  `ifdef CFG_IROM_ENABLED
   1.235 -            irom_select_m <= #1 irom_select_x;
   1.236 +            irom_select_m <= irom_select_x;
   1.237  `endif
   1.238 -            wb_select_m <= #1 wb_select_x;
   1.239 +            wb_select_m <= wb_select_x;
   1.240          end
   1.241      end
   1.242  end
   1.243 @@ -792,15 +792,15 @@
   1.244  begin
   1.245      if (rst_i == `TRUE)
   1.246      begin
   1.247 -        size_w <= #1 2'b00;
   1.248 -        data_w <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.249 -        sign_extend_w <= #1 `FALSE;
   1.250 +        size_w <= 2'b00;
   1.251 +        data_w <= {`LM32_WORD_WIDTH{1'b0}};
   1.252 +        sign_extend_w <= `FALSE;
   1.253      end
   1.254      else
   1.255      begin
   1.256 -        size_w <= #1 size_m;
   1.257 -        data_w <= #1 data_m;
   1.258 -        sign_extend_w <= #1 sign_extend_m;
   1.259 +        size_w <= size_m;
   1.260 +        data_w <= data_m;
   1.261 +        sign_extend_w <= sign_extend_m;
   1.262      end
   1.263  end
   1.264