1.1 diff -r 73de224304c1 -r d6c693415d59 lm32_ram.v 1.2 --- a/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 1.3 +++ b/lm32_ram.v Sat Aug 06 01:26:56 2011 +0100 1.4 @@ -191,13 +191,13 @@ 1.5 always @(posedge read_clk) 1.6 if (reset) 1.7 begin 1.8 - raw_data <= #1 0; 1.9 - raw <= #1 1'b0; 1.10 + raw_data <= 0; 1.11 + raw <= 1'b0; 1.12 end 1.13 else 1.14 begin 1.15 - raw_data <= #1 raw_data_nxt; 1.16 - raw <= #1 raw_nxt; 1.17 + raw_data <= raw_data_nxt; 1.18 + raw <= raw_nxt; 1.19 end 1.20 1.21 pmi_ram_dp_true 1.22 @@ -273,7 +273,7 @@ 1.23 1.24 always @(posedge read_clk) 1.25 if (enable_read) 1.26 - ra <= #1 read_address; 1.27 + ra <= read_address; 1.28 end 1.29 1.30 else 1.31 @@ -296,12 +296,12 @@ 1.32 // Write port 1.33 always @(posedge write_clk) 1.34 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 1.35 - mem[write_address] <= #1 write_data; 1.36 + mem[write_address] <= write_data; 1.37 1.38 // Register read address for use on next cycle 1.39 always @(posedge read_clk) 1.40 if (enable_read) 1.41 - ra <= #1 read_address; 1.42 + ra <= read_address; 1.43 1.44 end 1.45