[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)

Sun, 06 Mar 2011 21:14:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:14:43 +0000
changeset 22
35dc7ba83714
parent 8
07be9df9fee8
child 23
252df75c8f67
child 26
73de224304c1

[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)

document/lm32.htm file | annotate | diff | revisions
document/lm32_archman.pdf file | annotate | diff | revisions
lm32_cpu.v file | annotate | diff | revisions
lm32_include.v file | annotate | diff | revisions
lm32_monitor.v file | annotate | diff | revisions
     1.1 diff -r 07be9df9fee8 -r 35dc7ba83714 document/lm32.htm
     1.2 --- a/document/lm32.htm	Fri Aug 13 01:13:04 2010 +0100
     1.3 +++ b/document/lm32.htm	Sun Mar 06 21:14:43 2011 +0000
     1.4 @@ -107,7 +107,7 @@
     1.5  
     1.6  	if (window.setRelStartPage)
     1.7  	{
     1.8 -	setRelStartPage("MSB_Peripherals.htm");
     1.9 +	setRelStartPage("msb_peripherals.htm");
    1.10  
    1.11  		autoSync(0);
    1.12  		sendSyncInfo();
    1.13 @@ -155,6 +155,15 @@
    1.14  <tr valign="top" class="whs6">
    1.15  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.16  <p class=Table
    1.17 +	style="font-weight: normal;">3.6</td>
    1.18 +<td colspan="1" rowspan="1" width="598px" class="whs10">
    1.19 +<p class=whs10
    1.20 +	style="margin-left: 0px;">Fixed the issue of the processor locking 
    1.21 + up when Instruction Cache is not used.</td></tr>
    1.22 +
    1.23 +<tr valign="top" class="whs6">
    1.24 +<td colspan="1" rowspan="1" width="93px" class="whs9">
    1.25 +<p class=Table
    1.26  	style="font-weight: normal;">3.5</td>
    1.27  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.28  <p class=whs10
    1.29 @@ -165,9 +174,19 @@
    1.30  <tr valign="top" class="whs6">
    1.31  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.32  <p class=Table
    1.33 +	style="font-weight: normal;">3.4</td>
    1.34 +<td colspan="1" rowspan="1" width="598px" class="whs10">
    1.35 +<p class=whs10
    1.36 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
    1.37 +
    1.38 +<tr valign="top" class="whs6">
    1.39 +<td colspan="1" rowspan="1" width="93px" class="whs9">
    1.40 +<p class=Table
    1.41  	style="font-weight: normal;">3.3</td>
    1.42  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.43  <p class=whs10
    1.44 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
    1.45 +<p class=whs10
    1.46  	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
    1.47   connected through a local bus.</td></tr>
    1.48  
    1.49 @@ -177,6 +196,8 @@
    1.50  	style="font-weight: normal;">3.2</td>
    1.51  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.52  <p class=whs10
    1.53 +	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
    1.54 +<p class=whs10
    1.55  	style="margin-left: 0px;">Added Memory Type to instruction cache and 
    1.56   data cache.</td></tr>
    1.57  
    1.58 @@ -185,6 +206,7 @@
    1.59  <p class=Table
    1.60  	style="font-weight: normal;">3.1</td>
    1.61  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.62 +<p class="whs11">Updated to support ispLEVER 7.1.</p>
    1.63  <p class="whs11">Added static predictor to improve the behavior 
    1.64   of branches.</p>
    1.65  <p class="whs11">Added support for optionally mapping the register 
    1.66 @@ -197,8 +219,9 @@
    1.67  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.68  <p class=Table
    1.69  	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
    1.70 - </span></td>
    1.71 + (7.0 SP2)</span></td>
    1.72  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.73 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
    1.74  <p class="whs11">Fixed incorrect handling of data cache miss 
    1.75   in the presence of an instruction cache miss.</td></tr>
    1.76  
    1.77 @@ -406,9 +429,9 @@
    1.78  <p class=Table>Enables the Program Counter Trace feature, which enables 
    1.79   you to run the program trace during debug to find items in your C or C++ 
    1.80   Code during debug, such as breakpoints and exceptions. Refer to <span 
    1.81 - style="font-weight: bold;"><B>Help &gt; Help Contents &gt; Lattice Software 
    1.82 - Project Environment &gt; Concepts &gt; Program Counter Trace</B></span> for 
    1.83 - more information on Program Counter Trace.</td></tr>
    1.84 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
    1.85 + and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
    1.86 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
    1.87  
    1.88  <tr valign="top" class="whs15">
    1.89  <td colspan="1" rowspan="1" width="167px" class="whs18">
    1.90 @@ -416,9 +439,9 @@
    1.91  <td colspan="1" rowspan="1" width="524px" class="whs21">
    1.92  <p class=Table>Enables you to specify the depth of the Program Counter 
    1.93   Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
    1.94 - Contents &gt; Lattice Software Project Environment &nbsp;&gt; 
    1.95 - Concepts &gt; Program Counter Trace</B></span> for more information on Program 
    1.96 - Counter Trace.</td></tr>
    1.97 + Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
    1.98 + &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
    1.99 + Program Counter Trace.</td></tr>
   1.100  
   1.101  <tr valign="top" class="whs15">
   1.102  <td colspan="2" rowspan="1" width="691px" class="whs20">
   1.103 @@ -428,13 +451,6 @@
   1.104  
   1.105  <tr valign="top" class="whs15">
   1.106  <td colspan="1" rowspan="1" width="167px" class="whs18">
   1.107 -<p class=Table>Enable Shifter</td>
   1.108 -<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.109 -<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 
   1.110 - </td></tr>
   1.111 -
   1.112 -<tr valign="top" class="whs15">
   1.113 -<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.114  <p class=Table>Enable Piplined Barrel Shifter</td>
   1.115  <td colspan="1" rowspan="1" width="524px" class="whs19">
   1.116  <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
     2.1 diff -r 07be9df9fee8 -r 35dc7ba83714 document/lm32_archman.pdf
     2.2 Binary file document/lm32_archman.pdf has changed
     3.1 diff -r 07be9df9fee8 -r 35dc7ba83714 lm32_cpu.v
     3.2 --- a/lm32_cpu.v	Fri Aug 13 01:13:04 2010 +0100
     3.3 +++ b/lm32_cpu.v	Sun Mar 06 21:14:43 2011 +0000
     3.4 @@ -954,6 +954,7 @@
     3.5      .d_dat_i                (D_DAT_I),
     3.6      .d_ack_i                (D_ACK_I),
     3.7      .d_err_i                (D_ERR_I),
     3.8 +    .d_rty_i                (D_RTY_I),
     3.9      // ----- Outputs -------
    3.10      // To pipeline
    3.11  `ifdef CFG_DCACHE_ENABLED
     4.1 diff -r 07be9df9fee8 -r 35dc7ba83714 lm32_include.v
     4.2 --- a/lm32_include.v	Fri Aug 13 01:13:04 2010 +0100
     4.3 +++ b/lm32_include.v	Sun Mar 06 21:14:43 2011 +0000
     4.4 @@ -296,7 +296,7 @@
     4.5  
     4.6  // Use an asynchronous reset
     4.7  // To use a synchronous reset, define this macro as nothing
     4.8 -`define CFG_RESET_SENSITIVITY 
     4.9 +`define CFG_RESET_SENSITIVITY or posedge rst_i
    4.10  
    4.11  // V.T. Srce
    4.12  `define SRCE
     5.1 diff -r 07be9df9fee8 -r 35dc7ba83714 lm32_monitor.v
     5.2 --- a/lm32_monitor.v	Fri Aug 13 01:13:04 2010 +0100
     5.3 +++ b/lm32_monitor.v	Sun Mar 06 21:14:43 2011 +0000
     5.4 @@ -130,13 +130,7 @@
     5.5      end
     5.6      else
     5.7      begin
     5.8 -        case (state)
     5.9 -        2'b00:
    5.10 -        begin
    5.11 -            // Wait for a Wishbone access
    5.12 -            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    5.13 -                state <= 2'b01;
    5.14 -        end
    5.15 +        casez (state)
    5.16          2'b01:
    5.17          begin
    5.18              // Output read data to Wishbone
    5.19 @@ -160,6 +154,14 @@
    5.20              MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    5.21              state <= 2'b00;
    5.22          end
    5.23 +        default:
    5.24 +        begin
    5.25 +           write_enable <= `FALSE;
    5.26 +           MON_ACK_O <= `FALSE;
    5.27 +            // Wait for a Wishbone access
    5.28 +            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    5.29 +                state <= 2'b01;
    5.30 +        end
    5.31          endcase        
    5.32      end
    5.33  end