IPCores/lm32_cpu / files

     1.1 diff -r 27f96ec74b85 -r 5fb37de64edc jtag_cores.v
     1.2 --- a/jtag_cores.v	Sun Mar 06 19:32:57 2011 +0000
     1.3 +++ b/jtag_cores.v	Sun Mar 06 19:48:34 2011 +0000
     1.4 @@ -1,36 +1,60 @@
     1.5 -// TODO
     1.6 +module jtag_cores (
     1.7 +    input [7:0] reg_d,
     1.8 +    input [2:0] reg_addr_d,
     1.9 +    output reg_update,
    1.10 +    output [7:0] reg_q,
    1.11 +    output [2:0] reg_addr_q,
    1.12 +    output jtck,
    1.13 +    output jrstn
    1.14 +);
    1.15  
    1.16 -module jtag_cores (
    1.17 -    // ----- Inputs -------
    1.18 -    reg_d,
    1.19 -    reg_addr_d,
    1.20 -    // ----- Outputs -------    
    1.21 -    reg_update,
    1.22 -    reg_q,
    1.23 -    reg_addr_q,
    1.24 -    jtck,
    1.25 -    jrstn
    1.26 +wire sel;
    1.27 +wire tck;
    1.28 +wire tdi;
    1.29 +wire tdo;
    1.30 +wire shift;
    1.31 +wire update;
    1.32 +wire reset;
    1.33 +
    1.34 +jtag_tap jtag_tap (
    1.35 +	.sel(sel),
    1.36 +	.tck(tck),
    1.37 +	.tdi(tdi),
    1.38 +	.tdo(tdo),
    1.39 +	.shift(shift),
    1.40 +	.update(update),
    1.41 +	.reset(reset)
    1.42  );
    1.43  
    1.44 -input [7:0] reg_d;
    1.45 -input [2:0] reg_addr_d;
    1.46 +reg [10:0] jtag_shift;
    1.47 +reg [10:0] jtag_latched;
    1.48  
    1.49 -output reg_update;
    1.50 -wire   reg_update;
    1.51 -output [7:0] reg_q;
    1.52 -wire   [7:0] reg_q;
    1.53 -output [2:0] reg_addr_q;
    1.54 -wire   [2:0] reg_addr_q;
    1.55 +always @(posedge tck or posedge reset)
    1.56 +begin
    1.57 +	if(reset)
    1.58 +		jtag_shift <= 11'b0;
    1.59 +	else begin
    1.60 +		if(shift)
    1.61 +			jtag_shift <= {tdi, jtag_shift[10:1]};
    1.62 +		else
    1.63 +			jtag_shift <= {reg_d, reg_addr_d};
    1.64 +	end
    1.65 +end
    1.66  
    1.67 -output jtck;
    1.68 -wire   jtck;
    1.69 -output jrstn;
    1.70 -wire   jrstn;
    1.71 +assign tdo = jtag_shift[0];
    1.72  
    1.73 -assign reg_update = 1'b0;
    1.74 -assign reg_q = 8'hxx;
    1.75 -assign reg_addr_q = 3'bxxx;
    1.76 -assign jtck = 1'b0;
    1.77 -assign jrstn = 1'b1;
    1.78 -    
    1.79 +always @(posedge reg_update or posedge reset)
    1.80 +begin
    1.81 +	if(reset)
    1.82 +		jtag_latched <= 11'b0;
    1.83 +	else
    1.84 +		jtag_latched <= jtag_shift;
    1.85 +end
    1.86 +
    1.87 +assign reg_update = update & sel;
    1.88 +assign reg_q = jtag_latched[10:3];
    1.89 +assign reg_addr_q = jtag_latched[2:0];
    1.90 +assign jtck = tck;
    1.91 +assign jrstn = ~reset;
    1.92 +
    1.93  endmodule

     2.1 diff -r 27f96ec74b85 -r 5fb37de64edc jtag_tap_spartan6.v
     2.2 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.3 +++ b/jtag_tap_spartan6.v	Sun Mar 06 19:48:34 2011 +0000
     2.4 @@ -0,0 +1,28 @@
     2.5 +
     2.6 +module jtag_tap(
     2.7 +	output sel,
     2.8 +	output tck,
     2.9 +	output tdi,
    2.10 +	input tdo,
    2.11 +	output shift,
    2.12 +	output update,
    2.13 +	output reset
    2.14 +);
    2.15 +
    2.16 +BSCAN_SPARTAN6 #(
    2.17 +	.JTAG_CHAIN(1)
    2.18 +) bscan (
    2.19 +	.CAPTURE(),
    2.20 +	.DRCK(tck),
    2.21 +	.RESET(reset),
    2.22 +	.RUNTEST(),
    2.23 +	.SEL(sel),
    2.24 +	.SHIFT(shift),
    2.25 +	.TCK(),
    2.26 +	.TDI(tdi),
    2.27 +	.TMS(),
    2.28 +	.UPDATE(update),
    2.29 +	.TDO(tdo)
    2.30 +);
    2.31 +
    2.32 +endmodule

     3.1 diff -r 27f96ec74b85 -r 5fb37de64edc lm32_top.v
     3.2 --- a/lm32_top.v	Sun Mar 06 19:32:57 2011 +0000
     3.3 +++ b/lm32_top.v	Sun Mar 06 19:48:34 2011 +0000
     3.4 @@ -341,16 +341,12 @@
     3.5  // JTAG cores 
     3.6  jtag_cores jtag_cores (
     3.7      // ----- Inputs -----
     3.8 -`ifdef INCLUDE_LM32
     3.9      .reg_d                 (jtag_reg_d),
    3.10      .reg_addr_d            (jtag_reg_addr_d),
    3.11 -`endif
    3.12      // ----- Outputs -----
    3.13 -`ifdef INCLUDE_LM32
    3.14      .reg_update            (jtag_update),
    3.15      .reg_q                 (jtag_reg_q),
    3.16      .reg_addr_q            (jtag_reg_addr_q),
    3.17 -`endif
    3.18      .jtck                  (jtck),
    3.19      .jrstn                 (jrstn)
    3.20      );