[MERGE] Merge in changes from Lattice LM32 v3.5 LM32_V3_5_WITH_PATCHES

Fri, 13 Aug 2010 01:15:02 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 13 Aug 2010 01:15:02 +0100
changeset 9
0eb235b23d55
parent 7
0a26167af7e1
parent 8
07be9df9fee8
child 10
3847381aefad

[MERGE] Merge in changes from Lattice LM32 v3.5

lm32_addsub.v file | annotate | diff | revisions
lm32_dcache.v file | annotate | diff | revisions
lm32_icache.v file | annotate | diff | revisions
lm32_include.v file | annotate | diff | revisions
lm32_ram.v file | annotate | diff | revisions
     2.1 Binary file document/ds_icon.jpg has changed
     3.1 Binary file document/ds_icon_ast.jpg has changed
     4.1 Binary file document/dsb_icon.jpg has changed
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   7.133 +<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   7.134 +
   7.135 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   7.136 + optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   7.137 +
   7.138 +<p class="whs2"><span style="font-style: italic;"><I>*If the 
   7.139 + processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   7.140 +
   7.141 +<h2>Revision History</h2>
   7.142 +
   7.143 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
   7.144 +<script language='JavaScript'><!--
   7.145 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   7.146 +//--></script>
   7.147 +<col class="whs4">
   7.148 +<col class="whs5">
   7.149 +
   7.150 +<tr valign="top" class="whs6">
   7.151 +<td bgcolor="#DEE8F4" width="93px" class="whs7">
   7.152 +<p class=Table
   7.153 +	style="font-weight: bold;">Version</td>
   7.154 +<td bgcolor="#DEE8F4" width="598px" class="whs8">
   7.155 +<p class=Table
   7.156 +	style="font-weight: bold;">Description</td></tr>
   7.157 +
   7.158 +<tr valign="top" class="whs6">
   7.159 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.160 +<p class=Table
   7.161 +	style="font-weight: normal;">3.5</td>
   7.162 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.163 +<p class=whs10
   7.164 +	style="margin-left: 0px;">Support added to allow Inline Memories to 
   7.165 + be generated as non-power-of-two, as long as they are a multiple of 1024 
   7.166 + bytes</td></tr>
   7.167 +
   7.168 +<tr valign="top" class="whs6">
   7.169 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.170 +<p class=Table
   7.171 +	style="font-weight: normal;">3.3</td>
   7.172 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.173 +<p class=whs10
   7.174 +	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   7.175 + connected through a local bus.</td></tr>
   7.176 +
   7.177 +<tr valign="top" class="whs6">
   7.178 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.179 +<p class=Table
   7.180 +	style="font-weight: normal;">3.2</td>
   7.181 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.182 +<p class=whs10
   7.183 +	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   7.184 + data cache.</td></tr>
   7.185 +
   7.186 +<tr valign="top" class="whs6">
   7.187 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.188 +<p class=Table
   7.189 +	style="font-weight: normal;">3.1</td>
   7.190 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.191 +<p class="whs11">Added static predictor to improve the behavior 
   7.192 + of branches.</p>
   7.193 +<p class="whs11">Added support for optionally mapping the register 
   7.194 + file to EBRs (on-chip memory).</p>
   7.195 +<p class="whs11">Added support for selecting between distributed 
   7.196 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   7.197 + data caches.</td></tr>
   7.198 +
   7.199 +<tr valign="top" class="whs6">
   7.200 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.201 +<p class=Table
   7.202 +	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   7.203 + </span></td>
   7.204 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.205 +<p class="whs11">Fixed incorrect handling of data cache miss 
   7.206 + in the presence of an instruction cache miss.</td></tr>
   7.207 +
   7.208 +<tr valign="top" class="whs6">
   7.209 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   7.210 +<p class="whs11">1.0</td>
   7.211 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   7.212 +<p class="whs11">Initial version.</td></tr>
   7.213 +<script language='JavaScript'><!--
   7.214 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   7.215 +//--></script>
   7.216 +</table>
   7.217 +
   7.218 +&nbsp; 
   7.219 +
   7.220 +<h2>Dialog Box Parameters &#8211; 
   7.221 + General Tab</h2>
   7.222 +
   7.223 +<table x-use-null-cells cellspacing="0" class="whs12">
   7.224 +<col class="whs13">
   7.225 +<col class="whs14">
   7.226 +
   7.227 +<tr valign="top" class="whs15">
   7.228 +<td bgcolor="#DEE8F4" width="167px" class="whs16">
   7.229 +<p class=Table
   7.230 +	style="font-weight: bold;">Parameter</td>
   7.231 +<td bgcolor="#DEE8F4" width="524px" class="whs17">
   7.232 +<p class=Table
   7.233 +	style="font-weight: bold;">Description</td></tr>
   7.234 +
   7.235 +<tr valign="top" class="whs15">
   7.236 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.237 +<p class=Table
   7.238 +	style="font-weight: normal;">Instance Name</td>
   7.239 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.240 +<p class=Table
   7.241 +	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   7.242 + processor. Alphanumeric values and underscores are supported. The default 
   7.243 + is LM32.</td></tr>
   7.244 +
   7.245 +<tr valign="top" class="whs15">
   7.246 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.247 +<p class=Table
   7.248 +	style="font-weight: bold;">Settings</td>
   7.249 +</tr>
   7.250 +
   7.251 +<tr valign="top" class="whs15">
   7.252 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.253 +<p class=Table>Use EBRs for Register File</td>
   7.254 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.255 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   7.256 +
   7.257 +<tr valign="top" class="whs15">
   7.258 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.259 +<p class=Table>Enable Divide</td>
   7.260 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.261 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   7.262 + modu</span>).</td></tr>
   7.263 +
   7.264 +<tr valign="top" class="whs15">
   7.265 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.266 +<p class=Table>Enable Sign Extend</td>
   7.267 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.268 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   7.269 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   7.270 +
   7.271 +<tr valign="top" class="whs15">
   7.272 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.273 +<p class=Table>Location of Exception Handlers</td>
   7.274 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.275 +<p class=Table>Specifies the default value for the vector table. This can 
   7.276 + be changed by updating the EBA control register or status register.</p>
   7.277 +<p class=Table>This address must be aligned to a 256-byte boundary, since 
   7.278 + the hardware ignores the least-significant byte. Unpredictable behavior 
   7.279 + occurs when the exception base address and the exception vectors are not 
   7.280 + aligned on a 256-byte boundary.</td></tr>
   7.281 +
   7.282 +<tr valign="top" class="whs15">
   7.283 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.284 +<p class=Table
   7.285 +	style="font-weight: bold;">Multiplier Settings</td>
   7.286 +</tr>
   7.287 +
   7.288 +<tr valign="top" class="whs15">
   7.289 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.290 +<p class=Table>Enable Multiplier</td>
   7.291 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.292 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   7.293 + muli)</span>.</td></tr>
   7.294 +
   7.295 +<tr valign="top" class="whs15">
   7.296 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.297 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   7.298 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.299 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   7.300 +
   7.301 +<tr valign="top" class="whs15">
   7.302 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.303 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   7.304 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.305 +<p class=Table>Enables the multiplier using LUTs.</td></tr>
   7.306 +
   7.307 +<tr valign="top" class="whs15">
   7.308 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.309 +<p class=Table
   7.310 +	style="font-weight: bold;">Instruction Cache</td>
   7.311 +</tr>
   7.312 +
   7.313 +<tr valign="top" class="whs15">
   7.314 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.315 +<p class=Table>Instruction Cache Enabled</td>
   7.316 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.317 +<p class=Table
   7.318 +	style="margin-left: 14px;">Determines whether an instruction cache 
   7.319 + is implemented.</td></tr>
   7.320 +
   7.321 +<tr valign="top" class="whs15">
   7.322 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.323 +<p class=Table>Number of Sets</td>
   7.324 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.325 +<p class=Table
   7.326 +	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   7.327 + cache. Supported values are 128, 256, 512, 1024.</td></tr>
   7.328 +
   7.329 +<tr valign="top" class="whs15">
   7.330 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.331 +<p class=Table>Set Associativity</td>
   7.332 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.333 +<p class=Table
   7.334 +	style="margin-left: 14px;">Specifies the associativity of the instruction 
   7.335 + cache. Supported values are 1, 2.</td></tr>
   7.336 +
   7.337 +<tr valign="top" class="whs15">
   7.338 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.339 +<p class=Table>Bytes/Cache Line</td>
   7.340 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.341 +<p class=Table
   7.342 +	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   7.343 + cache line. Supported values are 4, 8, 16.</td></tr>
   7.344 +
   7.345 +<tr valign="top" class="whs15">
   7.346 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.347 +<p class=Table>Memory Type</td>
   7.348 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.349 +<p class=Table
   7.350 +	style="margin-left: 15px;">Determines the FPGA resource to be used 
   7.351 + to implement the instruction cache. The decision can be left to the synthesis 
   7.352 + tool (Auto), or you can select from the following options:</p>
   7.353 +<ul type="disc" class="whs22">
   7.354 +	
   7.355 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   7.356 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   7.357 +	
   7.358 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   7.359 + Implements the instruction cache as distributed RAM.</p></li>
   7.360 +	
   7.361 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   7.362 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   7.363 +	
   7.364 +	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   7.365 + the instruction cache as pseudo-dual-port EBR (one read port and one write 
   7.366 + port). </p></li>
   7.367 +</ul></td></tr>
   7.368 +
   7.369 +<tr valign="top" class="whs15">
   7.370 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.371 +<p class=Table
   7.372 +	style="font-weight: bold;">Debug Setting</td>
   7.373 +</tr>
   7.374 +
   7.375 +<tr valign="top" class="whs15">
   7.376 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.377 +<p class=Table>Enable Debug Interface</td>
   7.378 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.379 +<p class=Table>Includes the debugger stub in the CPU, which is required 
   7.380 + for debugging.</td></tr>
   7.381 +
   7.382 +<tr valign="top" class="whs15">
   7.383 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.384 +<p class=Table># of H/W Watchpoint Registers</td>
   7.385 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.386 +<p class=Table
   7.387 +	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   7.388 + registers to be used in the debugging process.</td></tr>
   7.389 +
   7.390 +<tr valign="top" class="whs15">
   7.391 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.392 +<p class=Table>Enable Debugging Code in Flash or ROM</td>
   7.393 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.394 +<p class=Table
   7.395 +	style="font-weight: normal;">Enables you to set hardware breakpoints 
   7.396 + in read-only memory.</td></tr>
   7.397 +
   7.398 +<tr valign="top" class="whs15">
   7.399 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.400 +<p class=Table># of H/W Breakpoint Registers</td>
   7.401 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.402 +<p class=Table>Specifies the number of hardware breakpoint registers to 
   7.403 + be used in the debugging process.</td></tr>
   7.404 +
   7.405 +<tr valign="top" class="whs15">
   7.406 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.407 +<p class=Table>Enable PC Trace</td>
   7.408 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.409 +<p class=Table>Enables the Program Counter Trace feature, which enables 
   7.410 + you to run the program trace during debug to find items in your C or C++ 
   7.411 + Code during debug, such as breakpoints and exceptions. Refer to <span 
   7.412 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; Lattice Software 
   7.413 + Project Environment &gt; Concepts &gt; Program Counter Trace</B></span> for 
   7.414 + more information on Program Counter Trace.</td></tr>
   7.415 +
   7.416 +<tr valign="top" class="whs15">
   7.417 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.418 +<p class=Table>Trace Depth</td>
   7.419 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.420 +<p class=Table>Enables you to specify the depth of the Program Counter 
   7.421 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   7.422 + Contents &gt; Lattice Software Project Environment &nbsp;&gt; 
   7.423 + Concepts &gt; Program Counter Trace</B></span> for more information on Program 
   7.424 + Counter Trace.</td></tr>
   7.425 +
   7.426 +<tr valign="top" class="whs15">
   7.427 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.428 +<p class=Table
   7.429 +	style="font-weight: bold;">Shifter Settings</td>
   7.430 +</tr>
   7.431 +
   7.432 +<tr valign="top" class="whs15">
   7.433 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.434 +<p class=Table>Enable Shifter</td>
   7.435 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.436 +<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 
   7.437 + </td></tr>
   7.438 +
   7.439 +<tr valign="top" class="whs15">
   7.440 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.441 +<p class=Table>Enable Piplined Barrel Shifter</td>
   7.442 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.443 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   7.444 + to perform a shift operation in three cycles.</td></tr>
   7.445 +
   7.446 +<tr valign="top" class="whs15">
   7.447 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.448 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   7.449 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   7.450 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   7.451 + shifter is implemented to shift one bit per cycle and take thirty-two 
   7.452 + cycles to complete.</td></tr>
   7.453 +
   7.454 +<tr valign="top" class="whs15">
   7.455 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   7.456 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   7.457 +</tr>
   7.458 +
   7.459 +<tr valign="top" class="whs15">
   7.460 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.461 +<p class=Table>Data Cache Enabled</td>
   7.462 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.463 +<p class=Table>Determines whether a data cache is implemented.</td></tr>
   7.464 +
   7.465 +<tr valign="top" class="whs15">
   7.466 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.467 +<p class=Table>Number of Sets</td>
   7.468 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.469 +<p class=Table>Specifies the number of sets in the data cache. Supported 
   7.470 + values are 128, 256, 512, 1024.</td></tr>
   7.471 +
   7.472 +<tr valign="top" class="whs15">
   7.473 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.474 +<p class=Table>Set Associativity</td>
   7.475 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.476 +<p class=Table>Specifies the associativity of the data cache. Supported 
   7.477 + values are 1, 2.</td></tr>
   7.478 +
   7.479 +<tr valign="top" class="whs15">
   7.480 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   7.481 +<p class=Table>Bytes/Cache Line</td>
   7.482 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   7.483 +<p class=Table>Specifies the number of bytes per data cache line. Supported 
   7.484 + values are 4, 8, 16.</td></tr>
   7.485 +
   7.486 +<tr valign="top" class="whs15">
   7.487 +<td colspan="1" rowspan="1" width="167px" class="whs23">
   7.488 +<p class=Table>Memory Type</td>
   7.489 +<td colspan="1" rowspan="1" width="524px" class="whs24">
   7.490 +<p class=Table>Determines the FPGA resource to be used to implement the 
   7.491 + data cache. The decision can be left to the synthesis tool (Auto), or 
   7.492 + you can select from the following options:</p>
   7.493 +<ul>
   7.494 +	
   7.495 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   7.496 + Leaves the implementation of the data cache to the synthesis tool.</p></li>
   7.497 +	
   7.498 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   7.499 + Implements the data cache as distributed RAM.</p></li>
   7.500 +	
   7.501 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   7.502 + Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   7.503 +</ul></td></tr>
   7.504 +</table>
   7.505 +
   7.506 +<p>&nbsp;</p>
   7.507 +
   7.508 +<h2>Dialog Box Parameters &#8211; 
   7.509 + Inline Memory Tab</h2>
   7.510 +
   7.511 +<table x-use-null-cells cellspacing="0" class="whs12">
   7.512 +<col class="whs13">
   7.513 +<col class="whs14">
   7.514 +
   7.515 +<tr valign="top" class="whs15">
   7.516 +<td bgcolor="#DEE8F4" width="167px" class="whs25">
   7.517 +<p class=Table
   7.518 +	style="font-weight: bold;">Parameter</td>
   7.519 +<td bgcolor="#DEE8F4" width="524px" class="whs26">
   7.520 +<p class=Table
   7.521 +	style="font-weight: bold;">Description</td></tr>
   7.522 +
   7.523 +<tr valign="top" class="whs15">
   7.524 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   7.525 +<p class=Table
   7.526 +	style="font-weight: bold;">Instruction Inline Memory</td>
   7.527 +</tr>
   7.528 +
   7.529 +<tr valign="top" class="whs15">
   7.530 +<td width="167px" class="whs28">
   7.531 +<p class=Table>Enable</td>
   7.532 +<td width="524px" class="whs29">
   7.533 +<p class=Table>Enables the instruction inline memory</td></tr>
   7.534 +
   7.535 +<tr valign="top" class="whs15">
   7.536 +<td width="167px" class="whs28">
   7.537 +<p class=Table>Instance Name</td>
   7.538 +<td width="524px" class="whs29">
   7.539 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   7.540 + values and underscores are supported. The default is Instruction_IM.</td></tr>
   7.541 +
   7.542 +<tr valign="top" class="whs15">
   7.543 +<td width="167px" class="whs28">
   7.544 +<p class=Table>Base Address</td>
   7.545 +<td width="524px" class="whs29">
   7.546 +<p class=Table>Specifies the base address for the instruction inline memory. 
   7.547 + The default is 0x10000000.</td></tr>
   7.548 +
   7.549 +<tr valign="top" class="whs15">
   7.550 +<td width="167px" class="whs28">
   7.551 +<p class=Table>Size of Memory in Bytes</td>
   7.552 +<td width="524px" class="whs29">
   7.553 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   7.554 +
   7.555 +<tr valign="top" class="whs15">
   7.556 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   7.557 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   7.558 +</tr>
   7.559 +
   7.560 +<tr valign="top" class="whs15">
   7.561 +<td width="167px" class="whs28">
   7.562 +<p class=Table>Initialization File Name</td>
   7.563 +<td width="524px" class="whs29">
   7.564 +<p class=Table>Specifies the name of the memory initialization file for 
   7.565 + instruction inline memory.</td></tr>
   7.566 +
   7.567 +<tr valign="top" class="whs15">
   7.568 +<td width="167px" class="whs28">
   7.569 +<p class=Table>File Format</td>
   7.570 +<td width="524px" class="whs29">
   7.571 +<p class=Table>Specifies the format of the memory initialization file: 
   7.572 + hex or binary.</td></tr>
   7.573 +
   7.574 +<tr valign="top" class="whs15">
   7.575 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   7.576 +<p class=Table
   7.577 +	style="font-weight: bold;">Data Inline Memory</td>
   7.578 +</tr>
   7.579 +
   7.580 +<tr valign="top" class="whs15">
   7.581 +<td width="167px" class="whs28">
   7.582 +<p class=Table>Enabled</td>
   7.583 +<td width="524px" class="whs29">
   7.584 +<p class=Table>Enables the data inline memory.</td></tr>
   7.585 +
   7.586 +<tr valign="top" class="whs15">
   7.587 +<td width="167px" class="whs28">
   7.588 +<p class=Table>Instance Name</td>
   7.589 +<td width="524px" class="whs29">
   7.590 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   7.591 + values and underscores are supported. The default is Data_IM.</td></tr>
   7.592 +
   7.593 +<tr valign="top" class="whs15">
   7.594 +<td width="167px" class="whs28">
   7.595 +<p class=Table>Base Address</td>
   7.596 +<td width="524px" class="whs29">
   7.597 +<p class=Table>Specifies the base address for the data inline memory. The 
   7.598 + default is 0x20000000.</td></tr>
   7.599 +
   7.600 +<tr valign="top" class="whs15">
   7.601 +<td width="167px" class="whs28">
   7.602 +<p class=Table>Size of Memory in Bytes</td>
   7.603 +<td width="524px" class="whs29">
   7.604 +<p class=Table>Specifies the size of the data inline memory.</td></tr>
   7.605 +
   7.606 +<tr valign="top" class="whs15">
   7.607 +<td colspan="2" rowspan="1" width="691px" class="whs27">
   7.608 +<p class=Table
   7.609 +	style="font-weight: bold;">Memory File</td>
   7.610 +</tr>
   7.611 +
   7.612 +<tr valign="top" class="whs15">
   7.613 +<td colspan="1" rowspan="1" width="167px" class="whs28">
   7.614 +<p class=Table>Initialization File Name</td>
   7.615 +<td colspan="1" rowspan="1" width="524px" class="whs29">
   7.616 +<p class=Table>Specifies the name of the memory initialization file for 
   7.617 + data inline memory.</td></tr>
   7.618 +
   7.619 +<tr valign="top" class="whs15">
   7.620 +<td colspan="1" rowspan="1" width="167px" class="whs30">
   7.621 +<p class=Table>File Format</td>
   7.622 +<td colspan="1" rowspan="1" width="524px" class="whs31">
   7.623 +<p class=Table>Specifies the format of the memory initialization file: 
   7.624 + hex or binary.</td></tr>
   7.625 +</table>
   7.626 +
   7.627 +<p>&nbsp;</p>
   7.628 +
   7.629 +<p>For the revision history of the component RTL files, refer to the header 
   7.630 + of each component Verilog source file. </p>
   7.631 +
   7.632 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   7.633 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   7.634 + and then click the note button.</p>
   7.635 +
   7.636 +<script type="text/javascript" language="JavaScript">
   7.637 +<!--
   7.638 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
   7.639 +  document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>");
   7.640 +//-->
   7.641 +</script><script type="text/javascript" language="javascript1.2">
   7.642 +<!--
   7.643 +if (window.writeIntopicBar)
   7.644 +	writeIntopicBar(0);
   7.645 +//-->
   7.646 +</script>
   7.647 +</body>
   7.648 +</html>
     8.1 Binary file document/lm32_archman.pdf has changed
     9.1 Binary file document/qm_icon.jpg has changed
    15.1 --- a/lm32_cpu.v	Tue Apr 06 18:27:55 2010 +0100
    15.2 +++ b/lm32_cpu.v	Fri Aug 13 01:15:02 2010 +0100
    15.3 @@ -536,7 +536,6 @@
    15.4  `endif
    15.5  wire direction_d;                               // Which direction to shift in
    15.6  reg direction_x;                                        
    15.7 -reg direction_m;
    15.8  wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
    15.9  `endif
   15.10  `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   15.11 @@ -789,7 +788,6 @@
   15.12      .i_dat_i                (I_DAT_I),
   15.13      .i_ack_i                (I_ACK_I),
   15.14      .i_err_i                (I_ERR_I),
   15.15 -    .i_rty_i                (I_RTY_I),
   15.16  `endif
   15.17  `ifdef CFG_HW_DEBUG_ENABLED
   15.18      .jtag_read_enable       (jtag_read_enable),
   15.19 @@ -932,7 +930,6 @@
   15.20      .stall_a                (stall_a),
   15.21      .stall_x                (stall_x),
   15.22      .stall_m                (stall_m),
   15.23 -    .kill_x                 (kill_x),
   15.24      .kill_m                 (kill_m),
   15.25      .exception_m            (exception_m),
   15.26      .store_operand_x        (store_operand_x),
   15.27 @@ -957,7 +954,6 @@
   15.28      .d_dat_i                (D_DAT_I),
   15.29      .d_ack_i                (D_ACK_I),
   15.30      .d_err_i                (D_ERR_I),
   15.31 -    .d_rty_i                (D_RTY_I),
   15.32      // ----- Outputs -------
   15.33      // To pipeline
   15.34  `ifdef CFG_DCACHE_ENABLED
   15.35 @@ -2264,8 +2260,8 @@
   15.36  `endif
   15.37  `ifdef CFG_SIGN_EXTEND_ENABLED
   15.38          x_result_sel_sext_x <= `FALSE;
   15.39 -`endif    
   15.40 -        x_result_sel_logic_x <= `FALSE;
   15.41 +`endif  
   15.42 +	x_result_sel_logic_x <= `FALSE;
   15.43  `ifdef CFG_USER_ENABLED
   15.44          x_result_sel_user_x <= `FALSE;
   15.45  `endif
   15.46 @@ -2331,9 +2327,6 @@
   15.47          exception_m <= `FALSE;
   15.48          load_m <= `FALSE;
   15.49          store_m <= `FALSE;
   15.50 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   15.51 -        direction_m <= `FALSE;
   15.52 -`endif
   15.53          write_enable_m <= `FALSE;            
   15.54          write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
   15.55          condition_met_m <= `FALSE;
   15.56 @@ -2384,7 +2377,7 @@
   15.57  `ifdef CFG_SIGN_EXTEND_ENABLED
   15.58              x_result_sel_sext_x <= x_result_sel_sext_d;
   15.59  `endif    
   15.60 -            x_result_sel_logic_x <= x_result_sel_logic_d;
   15.61 +	    x_result_sel_logic_x <= x_result_sel_logic_d;
   15.62  `ifdef CFG_USER_ENABLED
   15.63              x_result_sel_user_x <= x_result_sel_user_d;
   15.64  `endif
   15.65 @@ -2458,7 +2451,6 @@
   15.66              end
   15.67              m_bypass_enable_m <= m_bypass_enable_x;
   15.68  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   15.69 -            direction_m <= direction_x;
   15.70  `endif
   15.71              load_m <= load_x;
   15.72              store_m <= store_x;
    22.1 --- a/lm32_instruction_unit.v	Tue Apr 06 18:27:55 2010 +0100
    22.2 +++ b/lm32_instruction_unit.v	Fri Aug 13 01:15:02 2010 +0100
    22.3 @@ -91,7 +91,6 @@
    22.4      i_dat_i,
    22.5      i_ack_i,
    22.6      i_err_i,
    22.7 -    i_rty_i,
    22.8  `endif
    22.9  `ifdef CFG_HW_DEBUG_ENABLED
   22.10      jtag_read_enable,
   22.11 @@ -202,7 +201,6 @@
   22.12  input [`LM32_WORD_RNG] i_dat_i;                         // Instruction Wishbone interface read data
   22.13  input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
   22.14  input i_err_i;                                          // Instruction Wishbone interface error
   22.15 -input i_rty_i;                                          // Instruction Wishbone interface retry
   22.16  `endif
   22.17  
   22.18  `ifdef CFG_HW_DEBUG_ENABLED
    25.1 --- a/lm32_load_store_unit.v	Tue Apr 06 18:27:55 2010 +0100
    25.2 +++ b/lm32_load_store_unit.v	Fri Aug 13 01:15:02 2010 +0100
    25.3 @@ -53,7 +53,6 @@
    25.4      stall_a,
    25.5      stall_x,
    25.6      stall_m,
    25.7 -    kill_x,
    25.8      kill_m,
    25.9      exception_m,
   25.10      store_operand_x,
   25.11 @@ -132,7 +131,6 @@
   25.12  input stall_a;                                          // A stage stall 
   25.13  input stall_x;                                          // X stage stall        
   25.14  input stall_m;                                          // M stage stall
   25.15 -input kill_x;                                           // Kill instruction in X stage
   25.16  input kill_m;                                           // Kill instruction in M stage
   25.17  input exception_m;                                      // An exception occured in the M stage
   25.18  
    28.1 --- a/lm32_monitor.v	Tue Apr 06 18:27:55 2010 +0100
    28.2 +++ b/lm32_monitor.v	Fri Aug 13 01:15:02 2010 +0100
    28.3 @@ -43,9 +43,6 @@
    28.4      MON_SEL_I,
    28.5      MON_STB_I,
    28.6      MON_WE_I,
    28.7 -    MON_LOCK_I,
    28.8 -    MON_CTI_I,
    28.9 -    MON_BTE_I,
   28.10      // ----- Outputs -------
   28.11      MON_ACK_O,
   28.12      MON_RTY_O,
   28.13 @@ -59,15 +56,12 @@
   28.14  
   28.15  input clk_i;                                        // Wishbone clock
   28.16  input rst_i;                                        // Wishbone reset
   28.17 -input [`LM32_WORD_RNG] MON_ADR_I;                   // Wishbone address
   28.18 +input [10:2] MON_ADR_I;                             // Wishbone address
   28.19  input MON_STB_I;                                    // Wishbone strobe
   28.20  input MON_CYC_I;                                    // Wishbone cycle
   28.21  input [`LM32_WORD_RNG] MON_DAT_I;                   // Wishbone write data
   28.22  input [`LM32_BYTE_SELECT_RNG] MON_SEL_I;            // Wishbone byte select
   28.23  input MON_WE_I;                                     // Wishbone write enable
   28.24 -input MON_LOCK_I;                                   // Wishbone locked transfer
   28.25 -input [`LM32_CTYPE_RNG] MON_CTI_I;                  // Wishbone cycle type
   28.26 -input [`LM32_BTYPE_RNG] MON_BTE_I;                  // Wishbone burst type
   28.27     
   28.28  /////////////////////////////////////////////////////
   28.29  // Outputs
    33.1 --- a/lm32_top.v	Tue Apr 06 18:27:55 2010 +0100
    33.2 +++ b/lm32_top.v	Fri Aug 13 01:15:02 2010 +0100
    33.3 @@ -356,15 +356,12 @@
    33.4  			   // ----- Inputs -------
    33.5  			   .clk_i                 (clk_i),
    33.6  			   .rst_i                 (rst_i),
    33.7 -			   .MON_ADR_I             (DEBUG_ADR_I),
    33.8 +			   .MON_ADR_I             (DEBUG_ADR_I[10:2]),
    33.9  			   .MON_STB_I             (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
   33.10  			   .MON_CYC_I             (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
   33.11  			   .MON_WE_I              (DEBUG_WE_I),
   33.12  			   .MON_SEL_I             (DEBUG_SEL_I),
   33.13  			   .MON_DAT_I             (DEBUG_DAT_I),
   33.14 -			   .MON_CTI_I             (DEBUG_CTI_I),
   33.15 -			   .MON_BTE_I             (DEBUG_BTE_I),
   33.16 -			   .MON_LOCK_I            (DEBUG_LOCK_I),
   33.17  			   // ----- Outputs ------    
   33.18  			   .MON_RTY_O             (DEBUG_RTY_O),
   33.19  			   .MON_ERR_O             (DEBUG_ERR_O),