[MERGE] Merge changes from LatticeMico32 v3.6

Sun, 06 Mar 2011 21:17:31 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:17:31 +0000
changeset 23
252df75c8f67
parent 21
77cc432fd249
parent 22
35dc7ba83714
child 24
c336e674a37e

[MERGE] Merge changes from LatticeMico32 v3.6

lm32_cpu.v file | annotate | diff | revisions
lm32_include.v file | annotate | diff | revisions
     1.1 --- a/document/lm32.htm	Sun Mar 06 21:08:02 2011 +0000
     1.2 +++ b/document/lm32.htm	Sun Mar 06 21:17:31 2011 +0000
     1.3 @@ -107,7 +107,7 @@
     1.4  
     1.5  	if (window.setRelStartPage)
     1.6  	{
     1.7 -	setRelStartPage("MSB_Peripherals.htm");
     1.8 +	setRelStartPage("msb_peripherals.htm");
     1.9  
    1.10  		autoSync(0);
    1.11  		sendSyncInfo();
    1.12 @@ -155,6 +155,15 @@
    1.13  <tr valign="top" class="whs6">
    1.14  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.15  <p class=Table
    1.16 +	style="font-weight: normal;">3.6</td>
    1.17 +<td colspan="1" rowspan="1" width="598px" class="whs10">
    1.18 +<p class=whs10
    1.19 +	style="margin-left: 0px;">Fixed the issue of the processor locking 
    1.20 + up when Instruction Cache is not used.</td></tr>
    1.21 +
    1.22 +<tr valign="top" class="whs6">
    1.23 +<td colspan="1" rowspan="1" width="93px" class="whs9">
    1.24 +<p class=Table
    1.25  	style="font-weight: normal;">3.5</td>
    1.26  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.27  <p class=whs10
    1.28 @@ -165,9 +174,19 @@
    1.29  <tr valign="top" class="whs6">
    1.30  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.31  <p class=Table
    1.32 +	style="font-weight: normal;">3.4</td>
    1.33 +<td colspan="1" rowspan="1" width="598px" class="whs10">
    1.34 +<p class=whs10
    1.35 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
    1.36 +
    1.37 +<tr valign="top" class="whs6">
    1.38 +<td colspan="1" rowspan="1" width="93px" class="whs9">
    1.39 +<p class=Table
    1.40  	style="font-weight: normal;">3.3</td>
    1.41  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.42  <p class=whs10
    1.43 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
    1.44 +<p class=whs10
    1.45  	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
    1.46   connected through a local bus.</td></tr>
    1.47  
    1.48 @@ -177,6 +196,8 @@
    1.49  	style="font-weight: normal;">3.2</td>
    1.50  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.51  <p class=whs10
    1.52 +	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
    1.53 +<p class=whs10
    1.54  	style="margin-left: 0px;">Added Memory Type to instruction cache and 
    1.55   data cache.</td></tr>
    1.56  
    1.57 @@ -185,6 +206,7 @@
    1.58  <p class=Table
    1.59  	style="font-weight: normal;">3.1</td>
    1.60  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.61 +<p class="whs11">Updated to support ispLEVER 7.1.</p>
    1.62  <p class="whs11">Added static predictor to improve the behavior 
    1.63   of branches.</p>
    1.64  <p class="whs11">Added support for optionally mapping the register 
    1.65 @@ -197,8 +219,9 @@
    1.66  <td colspan="1" rowspan="1" width="93px" class="whs9">
    1.67  <p class=Table
    1.68  	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
    1.69 - </span></td>
    1.70 + (7.0 SP2)</span></td>
    1.71  <td colspan="1" rowspan="1" width="598px" class="whs10">
    1.72 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
    1.73  <p class="whs11">Fixed incorrect handling of data cache miss 
    1.74   in the presence of an instruction cache miss.</td></tr>
    1.75  
    1.76 @@ -406,9 +429,9 @@
    1.77  <p class=Table>Enables the Program Counter Trace feature, which enables 
    1.78   you to run the program trace during debug to find items in your C or C++ 
    1.79   Code during debug, such as breakpoints and exceptions. Refer to <span 
    1.80 - style="font-weight: bold;"><B>Help &gt; Help Contents &gt; Lattice Software 
    1.81 - Project Environment &gt; Concepts &gt; Program Counter Trace</B></span> for 
    1.82 - more information on Program Counter Trace.</td></tr>
    1.83 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
    1.84 + and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
    1.85 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
    1.86  
    1.87  <tr valign="top" class="whs15">
    1.88  <td colspan="1" rowspan="1" width="167px" class="whs18">
    1.89 @@ -416,9 +439,9 @@
    1.90  <td colspan="1" rowspan="1" width="524px" class="whs21">
    1.91  <p class=Table>Enables you to specify the depth of the Program Counter 
    1.92   Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
    1.93 - Contents &gt; Lattice Software Project Environment &nbsp;&gt; 
    1.94 - Concepts &gt; Program Counter Trace</B></span> for more information on Program 
    1.95 - Counter Trace.</td></tr>
    1.96 + Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
    1.97 + &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
    1.98 + Program Counter Trace.</td></tr>
    1.99  
   1.100  <tr valign="top" class="whs15">
   1.101  <td colspan="2" rowspan="1" width="691px" class="whs20">
   1.102 @@ -428,13 +451,6 @@
   1.103  
   1.104  <tr valign="top" class="whs15">
   1.105  <td colspan="1" rowspan="1" width="167px" class="whs18">
   1.106 -<p class=Table>Enable Shifter</td>
   1.107 -<td colspan="1" rowspan="1" width="524px" class="whs19">
   1.108 -<p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 
   1.109 - </td></tr>
   1.110 -
   1.111 -<tr valign="top" class="whs15">
   1.112 -<td colspan="1" rowspan="1" width="167px" class="whs18">
   1.113  <p class=Table>Enable Piplined Barrel Shifter</td>
   1.114  <td colspan="1" rowspan="1" width="524px" class="whs19">
   1.115  <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
     2.1 Binary file document/lm32_archman.pdf has changed
     3.1 --- a/lm32_cpu.v	Sun Mar 06 21:08:02 2011 +0000
     3.2 +++ b/lm32_cpu.v	Sun Mar 06 21:17:31 2011 +0000
     3.3 @@ -954,6 +954,7 @@
     3.4      .d_dat_i                (D_DAT_I),
     3.5      .d_ack_i                (D_ACK_I),
     3.6      .d_err_i                (D_ERR_I),
     3.7 +    .d_rty_i                (D_RTY_I),
     3.8      // ----- Outputs -------
     3.9      // To pipeline
    3.10  `ifdef CFG_DCACHE_ENABLED
     4.1 --- a/lm32_include.v	Sun Mar 06 21:08:02 2011 +0000
     4.2 +++ b/lm32_include.v	Sun Mar 06 21:17:31 2011 +0000
     4.3 @@ -338,7 +338,8 @@
     4.4  
     4.5  // Use an asynchronous reset
     4.6  // To use a synchronous reset, define this macro as nothing
     4.7 -`define CFG_RESET_SENSITIVITY 
     4.8 +//`define CFG_RESET_SENSITIVITY or posedge rst_i
     4.9 +`define CFG_RESET_SENSITIVITY
    4.10  
    4.11  // Whether to include context registers for debug exceptions
    4.12  // in addition to standard exception handling registers