IPCores/lm32_cpu / files

     1.1 --- a/lm32_addsub.v	Sun Apr 04 20:42:58 2010 +0100
     1.2 +++ b/lm32_addsub.v	Sun Apr 04 20:52:32 2010 +0100
     1.3 @@ -64,13 +64,17 @@
     1.4  // Instantiations
     1.5  ///////////////////////////////////////////////////// 
     1.6  
     1.7 +// Only use Lattice specific constructs when compiling with ispLEVER
     1.8 +`ifdef PLATFORM_LATTICE
     1.9         generate
    1.10  	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
    1.11 +`endif
    1.12  	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
    1.13  	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
    1.14     
    1.15  	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
    1.16  	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
    1.17 +`ifdef PLATFORM_LATTICE
    1.18  	  end else begin
    1.19  	    pmi_addsub #(// ----- Parameters -------
    1.20  			 .pmi_data_width     (32),
    1.21 @@ -89,5 +93,6 @@
    1.22  			 .Overflow           ());
    1.23  	  end
    1.24         endgenerate 
    1.25 +`endif
    1.26  
    1.27  endmodule

     2.1 --- a/lm32_dcache.v	Sun Apr 04 20:42:58 2010 +0100
     2.2 +++ b/lm32_dcache.v	Sun Apr 04 20:52:32 2010 +0100
     2.3 @@ -196,14 +196,16 @@
     2.4  		    // ----- Parameters -------
     2.5  		    .data_width (32),
     2.6  		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
     2.7 -`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
     2.8 +`ifdef PLATFORM_LATTICE
     2.9 + `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
    2.10  		    .RAM_IMPLEMENTATION ("EBR"),
    2.11  		    .RAM_TYPE ("RAM_DP_TRUE")
    2.12 -`else
    2.13 - `ifdef CFG_DCACHE_DAT_USE_SLICE
    2.14 + `else
    2.15 +  `ifdef CFG_DCACHE_DAT_USE_SLICE
    2.16  		    .RAM_IMPLEMENTATION ("SLICE")
    2.17 - `else
    2.18 +  `else
    2.19  		    .RAM_IMPLEMENTATION ("AUTO")
    2.20 +  `endif
    2.21   `endif
    2.22  `endif
    2.23  		    ) way_0_data_ram 

     3.1 --- a/lm32_icache.v	Sun Apr 04 20:42:58 2010 +0100
     3.2 +++ b/lm32_icache.v	Sun Apr 04 20:52:32 2010 +0100
     3.3 @@ -199,18 +199,20 @@
     3.4  	       // ----- Parameters -------
     3.5  	       .data_width                 (32),
     3.6  	       .address_width              (`LM32_IC_DMEM_ADDR_WIDTH),
     3.7 -`ifdef CFG_ICACHE_DAT_USE_DP_TRUE
     3.8 +`ifdef PLATFORM_LATTICE
     3.9 + `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
    3.10  	       .RAM_IMPLEMENTATION         ("EBR"),
    3.11  	       .RAM_TYPE                   ("RAM_DP_TRUE")
    3.12 -`else
    3.13 - `ifdef CFG_ICACHE_DAT_USE_DP
    3.14 + `else
    3.15 +  `ifdef CFG_ICACHE_DAT_USE_DP
    3.16  	       .RAM_IMPLEMENTATION         ("EBR"),
    3.17  	       .RAM_TYPE                   ("RAM_DP")
    3.18 - `else
    3.19 -  `ifdef CFG_ICACHE_DAT_USE_SLICE
    3.20 +  `else
    3.21 +   `ifdef CFG_ICACHE_DAT_USE_SLICE
    3.22  	       .RAM_IMPLEMENTATION         ("SLICE")
    3.23 -  `else
    3.24 +   `else
    3.25  	       .RAM_IMPLEMENTATION         ("AUTO")
    3.26 +   `endif
    3.27    `endif
    3.28   `endif
    3.29  `endif

     4.1 --- a/lm32_ram.v	Sun Apr 04 20:42:58 2010 +0100
     4.2 +++ b/lm32_ram.v	Sun Apr 04 20:52:32 2010 +0100
     4.3 @@ -58,10 +58,12 @@
     4.4      ----------------------------------------------------------------------*/
     4.5     parameter data_width = 1;               // Width of the data ports
     4.6     parameter address_width = 1;            // Width of the address ports
     4.7 +`ifdef PLATFORM_LATTICE
     4.8     parameter RAM_IMPLEMENTATION = "AUTO";  // Implement memory in EBRs, else
     4.9                                             // let synthesis tool select best 
    4.10                                             // possible solution (EBR or LUT)
    4.11     parameter RAM_TYPE = "RAM_DP";          // Type of EBR to be used
    4.12 +`endif
    4.13     
    4.14     /*----------------------------------------------------------------------
    4.15      Inputs
    4.16 @@ -82,7 +84,8 @@
    4.17      ----------------------------------------------------------------------*/
    4.18     output [data_width-1:0] read_data;      // Data read from specified addess
    4.19     wire   [data_width-1:0] read_data;
    4.20 -   
    4.21 +
    4.22 +`ifdef PLATFORM_LATTICE
    4.23     generate
    4.24        
    4.25        if ( RAM_IMPLEMENTATION == "EBR" )
    4.26 @@ -257,6 +260,7 @@
    4.27        
    4.28  	else 
    4.29  	  begin
    4.30 +`endif
    4.31  	     /*----------------------------------------------------------------------
    4.32  	      Internal nets and registers
    4.33  	      ----------------------------------------------------------------------*/
    4.34 @@ -282,8 +286,9 @@
    4.35  	       if (enable_read)
    4.36  		 ra <= read_address;
    4.37  	     
    4.38 +`ifdef PLATFORM_LATTICE
    4.39  	  end
    4.40  
    4.41     endgenerate
    4.42 -
    4.43 +`endif
    4.44  endmodule