Mon, 05 Apr 2010 21:00:31 +0100
reduce size of caches to fit in DE1 FPGA
The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).
| lm32_include.v | file | annotate | diff | revisions |
1.1 --- a/lm32_include.v Mon Apr 05 20:25:37 2010 +0100 1.2 +++ b/lm32_include.v Mon Apr 05 21:00:31 2010 +0100 1.3 @@ -51,20 +51,20 @@ 1.4 // CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software) 1.5 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all 1.6 // Works 100% OK with expensive synthesizers. 1.7 -/*`define CFG_ICACHE_ENABLED 1.8 -`define CFG_ICACHE_ASSOCIATIVITY 2 1.9 +`define CFG_ICACHE_ENABLED 1.10 +`define CFG_ICACHE_ASSOCIATIVITY 1 1.11 `define CFG_ICACHE_SETS 512 1.12 -`define CFG_ICACHE_BYTES_PER_LINE 16 1.13 +`define CFG_ICACHE_BYTES_PER_LINE 4 1.14 `define CFG_ICACHE_BASE_ADDRESS 32'h0 1.15 -`define CFG_ICACHE_LIMIT 32'h7fffffff 1.16 +`define CFG_ICACHE_LIMIT 32'h7FFF_FFFF 1.17 1.18 `define CFG_DCACHE_ENABLED 1.19 -`define CFG_DCACHE_ASSOCIATIVITY 2 1.20 +`define CFG_DCACHE_ASSOCIATIVITY 1 1.21 `define CFG_DCACHE_SETS 512 1.22 -`define CFG_DCACHE_BYTES_PER_LINE 16 1.23 +`define CFG_DCACHE_BYTES_PER_LINE 4 1.24 `define CFG_DCACHE_BASE_ADDRESS 32'h0 1.25 -`define CFG_DCACHE_LIMIT 32'h7fffffff 1.26 -*/ 1.27 +`define CFG_DCACHE_LIMIT 32'h0FFF_FFFF 1.28 + 1.29 // 1.30 // End of common configuration options 1.31 //