IPCores/lm32_cpu / files

     1.1 Binary file doc/ds_icon.jpg has changed

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     3.1 Binary file doc/dsb_icon.jpg has changed

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     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/doc/lm32.htm	Tue Mar 08 09:40:42 2011 +0000
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   6.133 +<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   6.134 +
   6.135 +<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   6.136 + optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   6.137 +
   6.138 +<p class="whs2"><span style="font-style: italic;"><I>*If the 
   6.139 + processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   6.140 +
   6.141 +<h2>Revision History</h2>
   6.142 +
   6.143 +<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
   6.144 +<script language='JavaScript'><!--
   6.145 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='738' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   6.146 +//--></script>
   6.147 +<col class="whs4">
   6.148 +<col class="whs5">
   6.149 +
   6.150 +<tr valign="top" class="whs6">
   6.151 +<td bgcolor="#DEE8F4" width="93px" class="whs7">
   6.152 +<p class=Table
   6.153 +	style="font-weight: bold;">Version</td>
   6.154 +<td bgcolor="#DEE8F4" width="598px" class="whs8">
   6.155 +<p class=Table
   6.156 +	style="font-weight: bold;">Description</td></tr>
   6.157 +
   6.158 +<tr valign="top" class="whs6">
   6.159 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.160 +<p class=Table
   6.161 +	style="font-weight: normal;">3.6</td>
   6.162 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.163 +<p class=whs10
   6.164 +	style="margin-left: 0px;">Fixed the issue of the processor locking 
   6.165 + up when Instruction Cache is not used.</td></tr>
   6.166 +
   6.167 +<tr valign="top" class="whs6">
   6.168 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.169 +<p class=Table
   6.170 +	style="font-weight: normal;">3.5</td>
   6.171 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.172 +<p class=whs10
   6.173 +	style="margin-left: 0px;">Support added to allow Inline Memories to 
   6.174 + be generated as non-power-of-two, as long as they are a multiple of 1024 
   6.175 + bytes</td></tr>
   6.176 +
   6.177 +<tr valign="top" class="whs6">
   6.178 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.179 +<p class=Table
   6.180 +	style="font-weight: normal;">3.4</td>
   6.181 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.182 +<p class=whs10
   6.183 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
   6.184 +
   6.185 +<tr valign="top" class="whs6">
   6.186 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.187 +<p class=Table
   6.188 +	style="font-weight: normal;">3.3</td>
   6.189 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.190 +<p class=whs10
   6.191 +	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
   6.192 +<p class=whs10
   6.193 +	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   6.194 + connected through a local bus.</td></tr>
   6.195 +
   6.196 +<tr valign="top" class="whs6">
   6.197 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.198 +<p class=Table
   6.199 +	style="font-weight: normal;">3.2</td>
   6.200 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.201 +<p class=whs10
   6.202 +	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
   6.203 +<p class=whs10
   6.204 +	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   6.205 + data cache.</td></tr>
   6.206 +
   6.207 +<tr valign="top" class="whs6">
   6.208 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.209 +<p class=Table
   6.210 +	style="font-weight: normal;">3.1</td>
   6.211 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.212 +<p class="whs11">Updated to support ispLEVER 7.1.</p>
   6.213 +<p class="whs11">Added static predictor to improve the behavior 
   6.214 + of branches.</p>
   6.215 +<p class="whs11">Added support for optionally mapping the register 
   6.216 + file to EBRs (on-chip memory).</p>
   6.217 +<p class="whs11">Added support for selecting between distributed 
   6.218 + RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   6.219 + data caches.</td></tr>
   6.220 +
   6.221 +<tr valign="top" class="whs6">
   6.222 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.223 +<p class=Table
   6.224 +	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   6.225 + (7.0 SP2)</span></td>
   6.226 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.227 +<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
   6.228 +<p class="whs11">Fixed incorrect handling of data cache miss 
   6.229 + in the presence of an instruction cache miss.</td></tr>
   6.230 +
   6.231 +<tr valign="top" class="whs6">
   6.232 +<td colspan="1" rowspan="1" width="93px" class="whs9">
   6.233 +<p class="whs11">1.0</td>
   6.234 +<td colspan="1" rowspan="1" width="598px" class="whs10">
   6.235 +<p class="whs11">Initial version.</td></tr>
   6.236 +<script language='JavaScript'><!--
   6.237 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   6.238 +//--></script>
   6.239 +</table>
   6.240 +
   6.241 +&nbsp; 
   6.242 +
   6.243 +<h2>Dialog Box Parameters &#8211; 
   6.244 + General Tab</h2>
   6.245 +
   6.246 +<table x-use-null-cells cellspacing="0" class="whs12">
   6.247 +<col class="whs13">
   6.248 +<col class="whs14">
   6.249 +
   6.250 +<tr valign="top" class="whs15">
   6.251 +<td bgcolor="#DEE8F4" width="167px" class="whs16">
   6.252 +<p class=Table
   6.253 +	style="font-weight: bold;">Parameter</td>
   6.254 +<td bgcolor="#DEE8F4" width="524px" class="whs17">
   6.255 +<p class=Table
   6.256 +	style="font-weight: bold;">Description</td></tr>
   6.257 +
   6.258 +<tr valign="top" class="whs15">
   6.259 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.260 +<p class=Table
   6.261 +	style="font-weight: normal;">Instance Name</td>
   6.262 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.263 +<p class=Table
   6.264 +	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   6.265 + processor. Alphanumeric values and underscores are supported. The default 
   6.266 + is LM32.</td></tr>
   6.267 +
   6.268 +<tr valign="top" class="whs15">
   6.269 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.270 +<p class=Table
   6.271 +	style="font-weight: bold;">Settings</td>
   6.272 +</tr>
   6.273 +
   6.274 +<tr valign="top" class="whs15">
   6.275 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.276 +<p class=Table>Use EBRs for Register File</td>
   6.277 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.278 +<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   6.279 +
   6.280 +<tr valign="top" class="whs15">
   6.281 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.282 +<p class=Table>Enable Divide</td>
   6.283 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.284 +<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   6.285 + modu</span>).</td></tr>
   6.286 +
   6.287 +<tr valign="top" class="whs15">
   6.288 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.289 +<p class=Table>Enable Sign Extend</td>
   6.290 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.291 +<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   6.292 + sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   6.293 +
   6.294 +<tr valign="top" class="whs15">
   6.295 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.296 +<p class=Table>Location of Exception Handlers</td>
   6.297 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.298 +<p class=Table>Specifies the default value for the vector table. This can 
   6.299 + be changed by updating the EBA control register or status register.</p>
   6.300 +<p class=Table>This address must be aligned to a 256-byte boundary, since 
   6.301 + the hardware ignores the least-significant byte. Unpredictable behavior 
   6.302 + occurs when the exception base address and the exception vectors are not 
   6.303 + aligned on a 256-byte boundary.</td></tr>
   6.304 +
   6.305 +<tr valign="top" class="whs15">
   6.306 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.307 +<p class=Table
   6.308 +	style="font-weight: bold;">Multiplier Settings</td>
   6.309 +</tr>
   6.310 +
   6.311 +<tr valign="top" class="whs15">
   6.312 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.313 +<p class=Table>Enable Multiplier</td>
   6.314 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.315 +<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   6.316 + muli)</span>.</td></tr>
   6.317 +
   6.318 +<tr valign="top" class="whs15">
   6.319 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.320 +<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   6.321 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.322 +<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   6.323 +
   6.324 +<tr valign="top" class="whs15">
   6.325 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.326 +<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   6.327 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.328 +<p class=Table>Enables the multiplier using LUTs.</td></tr>
   6.329 +
   6.330 +<tr valign="top" class="whs15">
   6.331 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.332 +<p class=Table
   6.333 +	style="font-weight: bold;">Instruction Cache</td>
   6.334 +</tr>
   6.335 +
   6.336 +<tr valign="top" class="whs15">
   6.337 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.338 +<p class=Table>Instruction Cache Enabled</td>
   6.339 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.340 +<p class=Table
   6.341 +	style="margin-left: 14px;">Determines whether an instruction cache 
   6.342 + is implemented.</td></tr>
   6.343 +
   6.344 +<tr valign="top" class="whs15">
   6.345 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.346 +<p class=Table>Number of Sets</td>
   6.347 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.348 +<p class=Table
   6.349 +	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   6.350 + cache. Supported values are 128, 256, 512, 1024.</td></tr>
   6.351 +
   6.352 +<tr valign="top" class="whs15">
   6.353 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.354 +<p class=Table>Set Associativity</td>
   6.355 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.356 +<p class=Table
   6.357 +	style="margin-left: 14px;">Specifies the associativity of the instruction 
   6.358 + cache. Supported values are 1, 2.</td></tr>
   6.359 +
   6.360 +<tr valign="top" class="whs15">
   6.361 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.362 +<p class=Table>Bytes/Cache Line</td>
   6.363 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.364 +<p class=Table
   6.365 +	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   6.366 + cache line. Supported values are 4, 8, 16.</td></tr>
   6.367 +
   6.368 +<tr valign="top" class="whs15">
   6.369 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.370 +<p class=Table>Memory Type</td>
   6.371 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.372 +<p class=Table
   6.373 +	style="margin-left: 15px;">Determines the FPGA resource to be used 
   6.374 + to implement the instruction cache. The decision can be left to the synthesis 
   6.375 + tool (Auto), or you can select from the following options:</p>
   6.376 +<ul type="disc" class="whs22">
   6.377 +	
   6.378 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   6.379 + Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   6.380 +	
   6.381 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   6.382 + Implements the instruction cache as distributed RAM.</p></li>
   6.383 +	
   6.384 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   6.385 + Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   6.386 +	
   6.387 +	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   6.388 + the instruction cache as pseudo-dual-port EBR (one read port and one write 
   6.389 + port). </p></li>
   6.390 +</ul></td></tr>
   6.391 +
   6.392 +<tr valign="top" class="whs15">
   6.393 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.394 +<p class=Table
   6.395 +	style="font-weight: bold;">Debug Setting</td>
   6.396 +</tr>
   6.397 +
   6.398 +<tr valign="top" class="whs15">
   6.399 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.400 +<p class=Table>Enable Debug Interface</td>
   6.401 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.402 +<p class=Table>Includes the debugger stub in the CPU, which is required 
   6.403 + for debugging.</td></tr>
   6.404 +
   6.405 +<tr valign="top" class="whs15">
   6.406 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.407 +<p class=Table># of H/W Watchpoint Registers</td>
   6.408 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.409 +<p class=Table
   6.410 +	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   6.411 + registers to be used in the debugging process.</td></tr>
   6.412 +
   6.413 +<tr valign="top" class="whs15">
   6.414 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.415 +<p class=Table>Enable Debugging Code in Flash or ROM</td>
   6.416 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.417 +<p class=Table
   6.418 +	style="font-weight: normal;">Enables you to set hardware breakpoints 
   6.419 + in read-only memory.</td></tr>
   6.420 +
   6.421 +<tr valign="top" class="whs15">
   6.422 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.423 +<p class=Table># of H/W Breakpoint Registers</td>
   6.424 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.425 +<p class=Table>Specifies the number of hardware breakpoint registers to 
   6.426 + be used in the debugging process.</td></tr>
   6.427 +
   6.428 +<tr valign="top" class="whs15">
   6.429 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.430 +<p class=Table>Enable PC Trace</td>
   6.431 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.432 +<p class=Table>Enables the Program Counter Trace feature, which enables 
   6.433 + you to run the program trace during debug to find items in your C or C++ 
   6.434 + Code during debug, such as breakpoints and exceptions. Refer to <span 
   6.435 + style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
   6.436 + and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
   6.437 + Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
   6.438 +
   6.439 +<tr valign="top" class="whs15">
   6.440 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.441 +<p class=Table>Trace Depth</td>
   6.442 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.443 +<p class=Table>Enables you to specify the depth of the Program Counter 
   6.444 + Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   6.445 + Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
   6.446 + &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
   6.447 + Program Counter Trace.</td></tr>
   6.448 +
   6.449 +<tr valign="top" class="whs15">
   6.450 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.451 +<p class=Table
   6.452 +	style="font-weight: bold;">Shifter Settings</td>
   6.453 +</tr>
   6.454 +
   6.455 +<tr valign="top" class="whs15">
   6.456 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.457 +<p class=Table>Enable Piplined Barrel Shifter</td>
   6.458 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.459 +<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   6.460 + to perform a shift operation in three cycles.</td></tr>
   6.461 +
   6.462 +<tr valign="top" class="whs15">
   6.463 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.464 +<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   6.465 +<td colspan="1" rowspan="1" width="524px" class="whs19">
   6.466 +<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   6.467 + shifter is implemented to shift one bit per cycle and take thirty-two 
   6.468 + cycles to complete.</td></tr>
   6.469 +
   6.470 +<tr valign="top" class="whs15">
   6.471 +<td colspan="2" rowspan="1" width="691px" class="whs20">
   6.472 +<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   6.473 +</tr>
   6.474 +
   6.475 +<tr valign="top" class="whs15">
   6.476 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.477 +<p class=Table>Data Cache Enabled</td>
   6.478 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.479 +<p class=Table>Determines whether a data cache is implemented.</td></tr>
   6.480 +
   6.481 +<tr valign="top" class="whs15">
   6.482 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.483 +<p class=Table>Number of Sets</td>
   6.484 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.485 +<p class=Table>Specifies the number of sets in the data cache. Supported 
   6.486 + values are 128, 256, 512, 1024.</td></tr>
   6.487 +
   6.488 +<tr valign="top" class="whs15">
   6.489 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.490 +<p class=Table>Set Associativity</td>
   6.491 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.492 +<p class=Table>Specifies the associativity of the data cache. Supported 
   6.493 + values are 1, 2.</td></tr>
   6.494 +
   6.495 +<tr valign="top" class="whs15">
   6.496 +<td colspan="1" rowspan="1" width="167px" class="whs18">
   6.497 +<p class=Table>Bytes/Cache Line</td>
   6.498 +<td colspan="1" rowspan="1" width="524px" class="whs21">
   6.499 +<p class=Table>Specifies the number of bytes per data cache line. Supported 
   6.500 + values are 4, 8, 16.</td></tr>
   6.501 +
   6.502 +<tr valign="top" class="whs15">
   6.503 +<td colspan="1" rowspan="1" width="167px" class="whs23">
   6.504 +<p class=Table>Memory Type</td>
   6.505 +<td colspan="1" rowspan="1" width="524px" class="whs24">
   6.506 +<p class=Table>Determines the FPGA resource to be used to implement the 
   6.507 + data cache. The decision can be left to the synthesis tool (Auto), or 
   6.508 + you can select from the following options:</p>
   6.509 +<ul>
   6.510 +	
   6.511 +	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   6.512 + Leaves the implementation of the data cache to the synthesis tool.</p></li>
   6.513 +	
   6.514 +	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   6.515 + Implements the data cache as distributed RAM.</p></li>
   6.516 +	
   6.517 +	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   6.518 + Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   6.519 +</ul></td></tr>
   6.520 +</table>
   6.521 +
   6.522 +<p>&nbsp;</p>
   6.523 +
   6.524 +<h2>Dialog Box Parameters &#8211; 
   6.525 + Inline Memory Tab</h2>
   6.526 +
   6.527 +<table x-use-null-cells cellspacing="0" class="whs12">
   6.528 +<col class="whs13">
   6.529 +<col class="whs14">
   6.530 +
   6.531 +<tr valign="top" class="whs15">
   6.532 +<td bgcolor="#DEE8F4" width="167px" class="whs25">
   6.533 +<p class=Table
   6.534 +	style="font-weight: bold;">Parameter</td>
   6.535 +<td bgcolor="#DEE8F4" width="524px" class="whs26">
   6.536 +<p class=Table
   6.537 +	style="font-weight: bold;">Description</td></tr>
   6.538 +
   6.539 +<tr valign="top" class="whs15">
   6.540 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.541 +<p class=Table
   6.542 +	style="font-weight: bold;">Instruction Inline Memory</td>
   6.543 +</tr>
   6.544 +
   6.545 +<tr valign="top" class="whs15">
   6.546 +<td width="167px" class="whs28">
   6.547 +<p class=Table>Enable</td>
   6.548 +<td width="524px" class="whs29">
   6.549 +<p class=Table>Enables the instruction inline memory</td></tr>
   6.550 +
   6.551 +<tr valign="top" class="whs15">
   6.552 +<td width="167px" class="whs28">
   6.553 +<p class=Table>Instance Name</td>
   6.554 +<td width="524px" class="whs29">
   6.555 +<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   6.556 + values and underscores are supported. The default is Instruction_IM.</td></tr>
   6.557 +
   6.558 +<tr valign="top" class="whs15">
   6.559 +<td width="167px" class="whs28">
   6.560 +<p class=Table>Base Address</td>
   6.561 +<td width="524px" class="whs29">
   6.562 +<p class=Table>Specifies the base address for the instruction inline memory. 
   6.563 + The default is 0x10000000.</td></tr>
   6.564 +
   6.565 +<tr valign="top" class="whs15">
   6.566 +<td width="167px" class="whs28">
   6.567 +<p class=Table>Size of Memory in Bytes</td>
   6.568 +<td width="524px" class="whs29">
   6.569 +<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   6.570 +
   6.571 +<tr valign="top" class="whs15">
   6.572 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.573 +<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   6.574 +</tr>
   6.575 +
   6.576 +<tr valign="top" class="whs15">
   6.577 +<td width="167px" class="whs28">
   6.578 +<p class=Table>Initialization File Name</td>
   6.579 +<td width="524px" class="whs29">
   6.580 +<p class=Table>Specifies the name of the memory initialization file for 
   6.581 + instruction inline memory.</td></tr>
   6.582 +
   6.583 +<tr valign="top" class="whs15">
   6.584 +<td width="167px" class="whs28">
   6.585 +<p class=Table>File Format</td>
   6.586 +<td width="524px" class="whs29">
   6.587 +<p class=Table>Specifies the format of the memory initialization file: 
   6.588 + hex or binary.</td></tr>
   6.589 +
   6.590 +<tr valign="top" class="whs15">
   6.591 +<td rowspan="1" colspan="2" width="691px" class="whs27">
   6.592 +<p class=Table
   6.593 +	style="font-weight: bold;">Data Inline Memory</td>
   6.594 +</tr>
   6.595 +
   6.596 +<tr valign="top" class="whs15">
   6.597 +<td width="167px" class="whs28">
   6.598 +<p class=Table>Enabled</td>
   6.599 +<td width="524px" class="whs29">
   6.600 +<p class=Table>Enables the data inline memory.</td></tr>
   6.601 +
   6.602 +<tr valign="top" class="whs15">
   6.603 +<td width="167px" class="whs28">
   6.604 +<p class=Table>Instance Name</td>
   6.605 +<td width="524px" class="whs29">
   6.606 +<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   6.607 + values and underscores are supported. The default is Data_IM.</td></tr>
   6.608 +
   6.609 +<tr valign="top" class="whs15">
   6.610 +<td width="167px" class="whs28">
   6.611 +<p class=Table>Base Address</td>
   6.612 +<td width="524px" class="whs29">
   6.613 +<p class=Table>Specifies the base address for the data inline memory. The 
   6.614 + default is 0x20000000.</td></tr>
   6.615 +
   6.616 +<tr valign="top" class="whs15">
   6.617 +<td width="167px" class="whs28">
   6.618 +<p class=Table>Size of Memory in Bytes</td>
   6.619 +<td width="524px" class="whs29">
   6.620 +<p class=Table>Specifies the size of the data inline memory.</td></tr>
   6.621 +
   6.622 +<tr valign="top" class="whs15">
   6.623 +<td colspan="2" rowspan="1" width="691px" class="whs27">
   6.624 +<p class=Table
   6.625 +	style="font-weight: bold;">Memory File</td>
   6.626 +</tr>
   6.627 +
   6.628 +<tr valign="top" class="whs15">
   6.629 +<td colspan="1" rowspan="1" width="167px" class="whs28">
   6.630 +<p class=Table>Initialization File Name</td>
   6.631 +<td colspan="1" rowspan="1" width="524px" class="whs29">
   6.632 +<p class=Table>Specifies the name of the memory initialization file for 
   6.633 + data inline memory.</td></tr>
   6.634 +
   6.635 +<tr valign="top" class="whs15">
   6.636 +<td colspan="1" rowspan="1" width="167px" class="whs30">
   6.637 +<p class=Table>File Format</td>
   6.638 +<td colspan="1" rowspan="1" width="524px" class="whs31">
   6.639 +<p class=Table>Specifies the format of the memory initialization file: 
   6.640 + hex or binary.</td></tr>
   6.641 +</table>
   6.642 +
   6.643 +<p>&nbsp;</p>
   6.644 +
   6.645 +<p>For the revision history of the component RTL files, refer to the header 
   6.646 + of each component Verilog source file. </p>
   6.647 +
   6.648 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   6.649 + fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   6.650 + and then click the note button.</p>
   6.651 +
   6.652 +<script type="text/javascript" language="JavaScript">
   6.653 +<!--
   6.654 + if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
   6.655 +  document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>");
   6.656 +//-->
   6.657 +</script><script type="text/javascript" language="javascript1.2">
   6.658 +<!--
   6.659 +if (window.writeIntopicBar)
   6.660 +	writeIntopicBar(0);
   6.661 +//-->
   6.662 +</script>
   6.663 +</body>
   6.664 +</html>

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    14.1 --- a/document/lm32.htm	Sun Mar 06 21:17:31 2011 +0000
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  14.133 -<h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
  14.134 -
  14.135 -<p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
  14.136 - optimized for Lattice Semiconductor field-programmable gate arrays. </p>
  14.137 -
  14.138 -<p class="whs2"><span style="font-style: italic;"><I>*If the 
  14.139 - processor manual fails to open, see the note at the bottom of this page.</I></span></p>
  14.140 -
  14.141 -<h2>Revision History</h2>
  14.142 -
  14.143 -<table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
  14.144 -<script language='JavaScript'><!--
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  14.146 -//--></script>
  14.147 -<col class="whs4">
  14.148 -<col class="whs5">
  14.149 -
  14.150 -<tr valign="top" class="whs6">
  14.151 -<td bgcolor="#DEE8F4" width="93px" class="whs7">
  14.152 -<p class=Table
  14.153 -	style="font-weight: bold;">Version</td>
  14.154 -<td bgcolor="#DEE8F4" width="598px" class="whs8">
  14.155 -<p class=Table
  14.156 -	style="font-weight: bold;">Description</td></tr>
  14.157 -
  14.158 -<tr valign="top" class="whs6">
  14.159 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.160 -<p class=Table
  14.161 -	style="font-weight: normal;">3.6</td>
  14.162 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.163 -<p class=whs10
  14.164 -	style="margin-left: 0px;">Fixed the issue of the processor locking 
  14.165 - up when Instruction Cache is not used.</td></tr>
  14.166 -
  14.167 -<tr valign="top" class="whs6">
  14.168 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.169 -<p class=Table
  14.170 -	style="font-weight: normal;">3.5</td>
  14.171 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.172 -<p class=whs10
  14.173 -	style="margin-left: 0px;">Support added to allow Inline Memories to 
  14.174 - be generated as non-power-of-two, as long as they are a multiple of 1024 
  14.175 - bytes</td></tr>
  14.176 -
  14.177 -<tr valign="top" class="whs6">
  14.178 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.179 -<p class=Table
  14.180 -	style="font-weight: normal;">3.4</td>
  14.181 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.182 -<p class=whs10
  14.183 -	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
  14.184 -
  14.185 -<tr valign="top" class="whs6">
  14.186 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.187 -<p class=Table
  14.188 -	style="font-weight: normal;">3.3</td>
  14.189 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.190 -<p class=whs10
  14.191 -	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
  14.192 -<p class=whs10
  14.193 -	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
  14.194 - connected through a local bus.</td></tr>
  14.195 -
  14.196 -<tr valign="top" class="whs6">
  14.197 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.198 -<p class=Table
  14.199 -	style="font-weight: normal;">3.2</td>
  14.200 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.201 -<p class=whs10
  14.202 -	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
  14.203 -<p class=whs10
  14.204 -	style="margin-left: 0px;">Added Memory Type to instruction cache and 
  14.205 - data cache.</td></tr>
  14.206 -
  14.207 -<tr valign="top" class="whs6">
  14.208 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.209 -<p class=Table
  14.210 -	style="font-weight: normal;">3.1</td>
  14.211 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.212 -<p class="whs11">Updated to support ispLEVER 7.1.</p>
  14.213 -<p class="whs11">Added static predictor to improve the behavior 
  14.214 - of branches.</p>
  14.215 -<p class="whs11">Added support for optionally mapping the register 
  14.216 - file to EBRs (on-chip memory).</p>
  14.217 -<p class="whs11">Added support for selecting between distributed 
  14.218 - RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
  14.219 - data caches.</td></tr>
  14.220 -
  14.221 -<tr valign="top" class="whs6">
  14.222 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.223 -<p class=Table
  14.224 -	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
  14.225 - (7.0 SP2)</span></td>
  14.226 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.227 -<p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
  14.228 -<p class="whs11">Fixed incorrect handling of data cache miss 
  14.229 - in the presence of an instruction cache miss.</td></tr>
  14.230 -
  14.231 -<tr valign="top" class="whs6">
  14.232 -<td colspan="1" rowspan="1" width="93px" class="whs9">
  14.233 -<p class="whs11">1.0</td>
  14.234 -<td colspan="1" rowspan="1" width="598px" class="whs10">
  14.235 -<p class="whs11">Initial version.</td></tr>
  14.236 -<script language='JavaScript'><!--
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  14.239 -</table>
  14.240 -
  14.241 -&nbsp; 
  14.242 -
  14.243 -<h2>Dialog Box Parameters &#8211; 
  14.244 - General Tab</h2>
  14.245 -
  14.246 -<table x-use-null-cells cellspacing="0" class="whs12">
  14.247 -<col class="whs13">
  14.248 -<col class="whs14">
  14.249 -
  14.250 -<tr valign="top" class="whs15">
  14.251 -<td bgcolor="#DEE8F4" width="167px" class="whs16">
  14.252 -<p class=Table
  14.253 -	style="font-weight: bold;">Parameter</td>
  14.254 -<td bgcolor="#DEE8F4" width="524px" class="whs17">
  14.255 -<p class=Table
  14.256 -	style="font-weight: bold;">Description</td></tr>
  14.257 -
  14.258 -<tr valign="top" class="whs15">
  14.259 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.260 -<p class=Table
  14.261 -	style="font-weight: normal;">Instance Name</td>
  14.262 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.263 -<p class=Table
  14.264 -	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
  14.265 - processor. Alphanumeric values and underscores are supported. The default 
  14.266 - is LM32.</td></tr>
  14.267 -
  14.268 -<tr valign="top" class="whs15">
  14.269 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.270 -<p class=Table
  14.271 -	style="font-weight: bold;">Settings</td>
  14.272 -</tr>
  14.273 -
  14.274 -<tr valign="top" class="whs15">
  14.275 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.276 -<p class=Table>Use EBRs for Register File</td>
  14.277 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.278 -<p class=Table>Uses embedded block RAMS for the register file.</td></tr>
  14.279 -
  14.280 -<tr valign="top" class="whs15">
  14.281 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.282 -<p class=Table>Enable Divide</td>
  14.283 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.284 -<p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
  14.285 - modu</span>).</td></tr>
  14.286 -
  14.287 -<tr valign="top" class="whs15">
  14.288 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.289 -<p class=Table>Enable Sign Extend</td>
  14.290 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.291 -<p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
  14.292 - sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
  14.293 -
  14.294 -<tr valign="top" class="whs15">
  14.295 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.296 -<p class=Table>Location of Exception Handlers</td>
  14.297 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.298 -<p class=Table>Specifies the default value for the vector table. This can 
  14.299 - be changed by updating the EBA control register or status register.</p>
  14.300 -<p class=Table>This address must be aligned to a 256-byte boundary, since 
  14.301 - the hardware ignores the least-significant byte. Unpredictable behavior 
  14.302 - occurs when the exception base address and the exception vectors are not 
  14.303 - aligned on a 256-byte boundary.</td></tr>
  14.304 -
  14.305 -<tr valign="top" class="whs15">
  14.306 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.307 -<p class=Table
  14.308 -	style="font-weight: bold;">Multiplier Settings</td>
  14.309 -</tr>
  14.310 -
  14.311 -<tr valign="top" class="whs15">
  14.312 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.313 -<p class=Table>Enable Multiplier</td>
  14.314 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.315 -<p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
  14.316 - muli)</span>.</td></tr>
  14.317 -
  14.318 -<tr valign="top" class="whs15">
  14.319 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.320 -<p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
  14.321 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.322 -<p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
  14.323 -
  14.324 -<tr valign="top" class="whs15">
  14.325 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.326 -<p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
  14.327 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.328 -<p class=Table>Enables the multiplier using LUTs.</td></tr>
  14.329 -
  14.330 -<tr valign="top" class="whs15">
  14.331 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.332 -<p class=Table
  14.333 -	style="font-weight: bold;">Instruction Cache</td>
  14.334 -</tr>
  14.335 -
  14.336 -<tr valign="top" class="whs15">
  14.337 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.338 -<p class=Table>Instruction Cache Enabled</td>
  14.339 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.340 -<p class=Table
  14.341 -	style="margin-left: 14px;">Determines whether an instruction cache 
  14.342 - is implemented.</td></tr>
  14.343 -
  14.344 -<tr valign="top" class="whs15">
  14.345 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.346 -<p class=Table>Number of Sets</td>
  14.347 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.348 -<p class=Table
  14.349 -	style="margin-left: 14px;">Specifies the number of sets in the instruction 
  14.350 - cache. Supported values are 128, 256, 512, 1024.</td></tr>
  14.351 -
  14.352 -<tr valign="top" class="whs15">
  14.353 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.354 -<p class=Table>Set Associativity</td>
  14.355 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.356 -<p class=Table
  14.357 -	style="margin-left: 14px;">Specifies the associativity of the instruction 
  14.358 - cache. Supported values are 1, 2.</td></tr>
  14.359 -
  14.360 -<tr valign="top" class="whs15">
  14.361 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.362 -<p class=Table>Bytes/Cache Line</td>
  14.363 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.364 -<p class=Table
  14.365 -	style="margin-left: 15px;">Specifies the number of bytes per instruction 
  14.366 - cache line. Supported values are 4, 8, 16.</td></tr>
  14.367 -
  14.368 -<tr valign="top" class="whs15">
  14.369 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.370 -<p class=Table>Memory Type</td>
  14.371 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.372 -<p class=Table
  14.373 -	style="margin-left: 15px;">Determines the FPGA resource to be used 
  14.374 - to implement the instruction cache. The decision can be left to the synthesis 
  14.375 - tool (Auto), or you can select from the following options:</p>
  14.376 -<ul type="disc" class="whs22">
  14.377 -	
  14.378 -	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
  14.379 - Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
  14.380 -	
  14.381 -	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
  14.382 - Implements the instruction cache as distributed RAM.</p></li>
  14.383 -	
  14.384 -	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
  14.385 - Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
  14.386 -	
  14.387 -	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
  14.388 - the instruction cache as pseudo-dual-port EBR (one read port and one write 
  14.389 - port). </p></li>
  14.390 -</ul></td></tr>
  14.391 -
  14.392 -<tr valign="top" class="whs15">
  14.393 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.394 -<p class=Table
  14.395 -	style="font-weight: bold;">Debug Setting</td>
  14.396 -</tr>
  14.397 -
  14.398 -<tr valign="top" class="whs15">
  14.399 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.400 -<p class=Table>Enable Debug Interface</td>
  14.401 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.402 -<p class=Table>Includes the debugger stub in the CPU, which is required 
  14.403 - for debugging.</td></tr>
  14.404 -
  14.405 -<tr valign="top" class="whs15">
  14.406 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.407 -<p class=Table># of H/W Watchpoint Registers</td>
  14.408 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.409 -<p class=Table
  14.410 -	style="font-weight: normal;">Specifies the number of hardware watchpoint 
  14.411 - registers to be used in the debugging process.</td></tr>
  14.412 -
  14.413 -<tr valign="top" class="whs15">
  14.414 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.415 -<p class=Table>Enable Debugging Code in Flash or ROM</td>
  14.416 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.417 -<p class=Table
  14.418 -	style="font-weight: normal;">Enables you to set hardware breakpoints 
  14.419 - in read-only memory.</td></tr>
  14.420 -
  14.421 -<tr valign="top" class="whs15">
  14.422 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.423 -<p class=Table># of H/W Breakpoint Registers</td>
  14.424 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.425 -<p class=Table>Specifies the number of hardware breakpoint registers to 
  14.426 - be used in the debugging process.</td></tr>
  14.427 -
  14.428 -<tr valign="top" class="whs15">
  14.429 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.430 -<p class=Table>Enable PC Trace</td>
  14.431 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.432 -<p class=Table>Enables the Program Counter Trace feature, which enables 
  14.433 - you to run the program trace during debug to find items in your C or C++ 
  14.434 - Code during debug, such as breakpoints and exceptions. Refer to <span 
  14.435 - style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
  14.436 - and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
  14.437 - Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
  14.438 -
  14.439 -<tr valign="top" class="whs15">
  14.440 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.441 -<p class=Table>Trace Depth</td>
  14.442 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.443 -<p class=Table>Enables you to specify the depth of the Program Counter 
  14.444 - Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
  14.445 - Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
  14.446 - &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
  14.447 - Program Counter Trace.</td></tr>
  14.448 -
  14.449 -<tr valign="top" class="whs15">
  14.450 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.451 -<p class=Table
  14.452 -	style="font-weight: bold;">Shifter Settings</td>
  14.453 -</tr>
  14.454 -
  14.455 -<tr valign="top" class="whs15">
  14.456 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.457 -<p class=Table>Enable Piplined Barrel Shifter</td>
  14.458 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.459 -<p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
  14.460 - to perform a shift operation in three cycles.</td></tr>
  14.461 -
  14.462 -<tr valign="top" class="whs15">
  14.463 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.464 -<p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
  14.465 -<td colspan="1" rowspan="1" width="524px" class="whs19">
  14.466 -<p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
  14.467 - shifter is implemented to shift one bit per cycle and take thirty-two 
  14.468 - cycles to complete.</td></tr>
  14.469 -
  14.470 -<tr valign="top" class="whs15">
  14.471 -<td colspan="2" rowspan="1" width="691px" class="whs20">
  14.472 -<p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
  14.473 -</tr>
  14.474 -
  14.475 -<tr valign="top" class="whs15">
  14.476 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.477 -<p class=Table>Data Cache Enabled</td>
  14.478 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.479 -<p class=Table>Determines whether a data cache is implemented.</td></tr>
  14.480 -
  14.481 -<tr valign="top" class="whs15">
  14.482 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.483 -<p class=Table>Number of Sets</td>
  14.484 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.485 -<p class=Table>Specifies the number of sets in the data cache. Supported 
  14.486 - values are 128, 256, 512, 1024.</td></tr>
  14.487 -
  14.488 -<tr valign="top" class="whs15">
  14.489 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.490 -<p class=Table>Set Associativity</td>
  14.491 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.492 -<p class=Table>Specifies the associativity of the data cache. Supported 
  14.493 - values are 1, 2.</td></tr>
  14.494 -
  14.495 -<tr valign="top" class="whs15">
  14.496 -<td colspan="1" rowspan="1" width="167px" class="whs18">
  14.497 -<p class=Table>Bytes/Cache Line</td>
  14.498 -<td colspan="1" rowspan="1" width="524px" class="whs21">
  14.499 -<p class=Table>Specifies the number of bytes per data cache line. Supported 
  14.500 - values are 4, 8, 16.</td></tr>
  14.501 -
  14.502 -<tr valign="top" class="whs15">
  14.503 -<td colspan="1" rowspan="1" width="167px" class="whs23">
  14.504 -<p class=Table>Memory Type</td>
  14.505 -<td colspan="1" rowspan="1" width="524px" class="whs24">
  14.506 -<p class=Table>Determines the FPGA resource to be used to implement the 
  14.507 - data cache. The decision can be left to the synthesis tool (Auto), or 
  14.508 - you can select from the following options:</p>
  14.509 -<ul>
  14.510 -	
  14.511 -	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
  14.512 - Leaves the implementation of the data cache to the synthesis tool.</p></li>
  14.513 -	
  14.514 -	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
  14.515 - Implements the data cache as distributed RAM.</p></li>
  14.516 -	
  14.517 -	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
  14.518 - Implements the data cache as dual-port EBR (two read/write ports).</p></li>
  14.519 -</ul></td></tr>
  14.520 -</table>
  14.521 -
  14.522 -<p>&nbsp;</p>
  14.523 -
  14.524 -<h2>Dialog Box Parameters &#8211; 
  14.525 - Inline Memory Tab</h2>
  14.526 -
  14.527 -<table x-use-null-cells cellspacing="0" class="whs12">
  14.528 -<col class="whs13">
  14.529 -<col class="whs14">
  14.530 -
  14.531 -<tr valign="top" class="whs15">
  14.532 -<td bgcolor="#DEE8F4" width="167px" class="whs25">
  14.533 -<p class=Table
  14.534 -	style="font-weight: bold;">Parameter</td>
  14.535 -<td bgcolor="#DEE8F4" width="524px" class="whs26">
  14.536 -<p class=Table
  14.537 -	style="font-weight: bold;">Description</td></tr>
  14.538 -
  14.539 -<tr valign="top" class="whs15">
  14.540 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.541 -<p class=Table
  14.542 -	style="font-weight: bold;">Instruction Inline Memory</td>
  14.543 -</tr>
  14.544 -
  14.545 -<tr valign="top" class="whs15">
  14.546 -<td width="167px" class="whs28">
  14.547 -<p class=Table>Enable</td>
  14.548 -<td width="524px" class="whs29">
  14.549 -<p class=Table>Enables the instruction inline memory</td></tr>
  14.550 -
  14.551 -<tr valign="top" class="whs15">
  14.552 -<td width="167px" class="whs28">
  14.553 -<p class=Table>Instance Name</td>
  14.554 -<td width="524px" class="whs29">
  14.555 -<p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
  14.556 - values and underscores are supported. The default is Instruction_IM.</td></tr>
  14.557 -
  14.558 -<tr valign="top" class="whs15">
  14.559 -<td width="167px" class="whs28">
  14.560 -<p class=Table>Base Address</td>
  14.561 -<td width="524px" class="whs29">
  14.562 -<p class=Table>Specifies the base address for the instruction inline memory. 
  14.563 - The default is 0x10000000.</td></tr>
  14.564 -
  14.565 -<tr valign="top" class="whs15">
  14.566 -<td width="167px" class="whs28">
  14.567 -<p class=Table>Size of Memory in Bytes</td>
  14.568 -<td width="524px" class="whs29">
  14.569 -<p class=Table>Specifies the size of the instruction inline memory.</td></tr>
  14.570 -
  14.571 -<tr valign="top" class="whs15">
  14.572 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.573 -<p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
  14.574 -</tr>
  14.575 -
  14.576 -<tr valign="top" class="whs15">
  14.577 -<td width="167px" class="whs28">
  14.578 -<p class=Table>Initialization File Name</td>
  14.579 -<td width="524px" class="whs29">
  14.580 -<p class=Table>Specifies the name of the memory initialization file for 
  14.581 - instruction inline memory.</td></tr>
  14.582 -
  14.583 -<tr valign="top" class="whs15">
  14.584 -<td width="167px" class="whs28">
  14.585 -<p class=Table>File Format</td>
  14.586 -<td width="524px" class="whs29">
  14.587 -<p class=Table>Specifies the format of the memory initialization file: 
  14.588 - hex or binary.</td></tr>
  14.589 -
  14.590 -<tr valign="top" class="whs15">
  14.591 -<td rowspan="1" colspan="2" width="691px" class="whs27">
  14.592 -<p class=Table
  14.593 -	style="font-weight: bold;">Data Inline Memory</td>
  14.594 -</tr>
  14.595 -
  14.596 -<tr valign="top" class="whs15">
  14.597 -<td width="167px" class="whs28">
  14.598 -<p class=Table>Enabled</td>
  14.599 -<td width="524px" class="whs29">
  14.600 -<p class=Table>Enables the data inline memory.</td></tr>
  14.601 -
  14.602 -<tr valign="top" class="whs15">
  14.603 -<td width="167px" class="whs28">
  14.604 -<p class=Table>Instance Name</td>
  14.605 -<td width="524px" class="whs29">
  14.606 -<p class=Table>Specifies the name of the data inline memory. Alphanumeric 
  14.607 - values and underscores are supported. The default is Data_IM.</td></tr>
  14.608 -
  14.609 -<tr valign="top" class="whs15">
  14.610 -<td width="167px" class="whs28">
  14.611 -<p class=Table>Base Address</td>
  14.612 -<td width="524px" class="whs29">
  14.613 -<p class=Table>Specifies the base address for the data inline memory. The 
  14.614 - default is 0x20000000.</td></tr>
  14.615 -
  14.616 -<tr valign="top" class="whs15">
  14.617 -<td width="167px" class="whs28">
  14.618 -<p class=Table>Size of Memory in Bytes</td>
  14.619 -<td width="524px" class="whs29">
  14.620 -<p class=Table>Specifies the size of the data inline memory.</td></tr>
  14.621 -
  14.622 -<tr valign="top" class="whs15">
  14.623 -<td colspan="2" rowspan="1" width="691px" class="whs27">
  14.624 -<p class=Table
  14.625 -	style="font-weight: bold;">Memory File</td>
  14.626 -</tr>
  14.627 -
  14.628 -<tr valign="top" class="whs15">
  14.629 -<td colspan="1" rowspan="1" width="167px" class="whs28">
  14.630 -<p class=Table>Initialization File Name</td>
  14.631 -<td colspan="1" rowspan="1" width="524px" class="whs29">
  14.632 -<p class=Table>Specifies the name of the memory initialization file for 
  14.633 - data inline memory.</td></tr>
  14.634 -
  14.635 -<tr valign="top" class="whs15">
  14.636 -<td colspan="1" rowspan="1" width="167px" class="whs30">
  14.637 -<p class=Table>File Format</td>
  14.638 -<td colspan="1" rowspan="1" width="524px" class="whs31">
  14.639 -<p class=Table>Specifies the format of the memory initialization file: 
  14.640 - hex or binary.</td></tr>
  14.641 -</table>
  14.642 -
  14.643 -<p>&nbsp;</p>
  14.644 -
  14.645 -<p>For the revision history of the component RTL files, refer to the header 
  14.646 - of each component Verilog source file. </p>
  14.647 -
  14.648 -<p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
  14.649 - fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
  14.650 - and then click the note button.</p>
  14.651 -
  14.652 -<script type="text/javascript" language="JavaScript">
  14.653 -<!--
  14.654 - if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape'))
  14.655 -  document.write("<div id='tooltip' class='WebHelpPopupMenu'></div>");
  14.656 -//-->
  14.657 -</script><script type="text/javascript" language="javascript1.2">
  14.658 -<!--
  14.659 -if (window.writeIntopicBar)
  14.660 -	writeIntopicBar(0);
  14.661 -//-->
  14.662 -</script>
  14.663 -</body>
  14.664 -</html>

    15.1 Binary file document/lm32_archman.pdf has changed

    16.1 Binary file document/qm_icon.jpg has changed

    17.1 --- a/jtag_cores.v	Sun Mar 06 21:17:31 2011 +0000
    17.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.3 @@ -1,66 +0,0 @@
    17.4 -// Modified by GSI to use simple positive edge clocking and the JTAG capture state
    17.5 -
    17.6 -module jtag_cores (
    17.7 -    input [7:0] reg_d,
    17.8 -    input [2:0] reg_addr_d,
    17.9 -    output reg_update,
   17.10 -    output [7:0] reg_q,
   17.11 -    output [2:0] reg_addr_q,
   17.12 -    output jtck,
   17.13 -    output jrstn
   17.14 -);
   17.15 -
   17.16 -wire tck;
   17.17 -wire tdi;
   17.18 -wire tdo;
   17.19 -wire capture;
   17.20 -wire shift;
   17.21 -wire update;
   17.22 -wire e1dr;
   17.23 -wire reset;
   17.24 -
   17.25 -jtag_tap jtag_tap (
   17.26 -	.tck(tck),
   17.27 -	.tdi(tdi),
   17.28 -	.tdo(tdo),
   17.29 -	.capture(capture),
   17.30 -	.shift(shift),
   17.31 -	.e1dr(e1dr),
   17.32 -	.update(update),
   17.33 -	.reset(reset)
   17.34 -);
   17.35 -
   17.36 -reg [10:0] jtag_shift;
   17.37 -reg [10:0] jtag_latched;
   17.38 -
   17.39 -always @(posedge tck)
   17.40 -begin
   17.41 -	if(reset)
   17.42 -		jtag_shift <= 11'b0;
   17.43 -	else begin
   17.44 -		if (shift)
   17.45 -			jtag_shift <= {tdi, jtag_shift[10:1]};
   17.46 -		else if (capture)
   17.47 -			jtag_shift <= {reg_d, reg_addr_d};
   17.48 -	end
   17.49 -end
   17.50 -
   17.51 -assign tdo = jtag_shift[0];
   17.52 -
   17.53 -always @(posedge tck)
   17.54 -begin
   17.55 -	if(reset)
   17.56 -		jtag_latched <= 11'b0;
   17.57 -	else begin
   17.58 -	   if (e1dr)
   17.59 -		   jtag_latched <= jtag_shift;
   17.60 -	end
   17.61 -end
   17.62 -
   17.63 -assign reg_update = update;
   17.64 -assign reg_q = jtag_latched[10:3];
   17.65 -assign reg_addr_q = jtag_latched[2:0];
   17.66 -assign jtck = tck;
   17.67 -assign jrstn = ~reset;
   17.68 -
   17.69 -endmodule

    18.1 --- a/jtag_tap_altera.v	Sun Mar 06 21:17:31 2011 +0000
    18.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.3 @@ -1,59 +0,0 @@
    18.4 -module jtag_tap(
    18.5 -  output tck,
    18.6 -  output tdi,
    18.7 -  input tdo,
    18.8 -  output capture,
    18.9 -  output shift,
   18.10 -  output e1dr,
   18.11 -  output update,
   18.12 -  output reset
   18.13 -);
   18.14 -
   18.15 -assign reset = 0;
   18.16 -wire nil1, nil2, nil3, nil4;
   18.17 -
   18.18 -sld_virtual_jtag altera_jtag(
   18.19 -  .ir_in       		(),
   18.20 -  .ir_out		(),
   18.21 -  .tck			(tck),
   18.22 -  .tdo			(tdo),
   18.23 -  .tdi			(tdi),
   18.24 -  .virtual_state_cdr	(capture),
   18.25 -  .virtual_state_sdr	(shift),
   18.26 -  .virtual_state_e1dr	(e1dr),
   18.27 -  .virtual_state_pdr	(nil1),
   18.28 -  .virtual_state_e2dr	(nil2),
   18.29 -  .virtual_state_udr	(update),
   18.30 -  .virtual_state_cir	(nil3),
   18.31 -  .virtual_state_uir	(nil4)
   18.32 -  // synopsys translate_off
   18.33 -  ,
   18.34 -  .jtag_state_cdr	(),
   18.35 -  .jtag_state_cir	(),
   18.36 -  .jtag_state_e1dr	(),
   18.37 -  .jtag_state_e1ir	(),
   18.38 -  .jtag_state_e2dr	(),
   18.39 -  .jtag_state_e2ir	(),
   18.40 -  .jtag_state_pdr	(),
   18.41 -  .jtag_state_pir	(),
   18.42 -  .jtag_state_rti	(),
   18.43 -  .jtag_state_sdr	(),
   18.44 -  .jtag_state_sdrs	(),
   18.45 -  .jtag_state_sir	(),
   18.46 -  .jtag_state_sirs	(),
   18.47 -  .jtag_state_tlr	(),
   18.48 -  .jtag_state_udr	(),
   18.49 -  .jtag_state_uir	(),
   18.50 -  .tms			()
   18.51 -  // synopsys translate_on
   18.52 -  );
   18.53 -
   18.54 -defparam
   18.55 -   altera_jtag.sld_auto_instance_index = "YES",
   18.56 -   altera_jtag.sld_instance_index = 0,
   18.57 -   altera_jtag.sld_ir_width = 1,
   18.58 -   altera_jtag.sld_sim_action = "",
   18.59 -   altera_jtag.sld_sim_n_scan = 0,
   18.60 -   altera_jtag.sld_sim_total_length = 0;
   18.61 -
   18.62 -endmodule

    19.1 --- a/jtag_tap_xilinx_spartan6.v	Sun Mar 06 21:17:31 2011 +0000
    19.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.3 @@ -1,43 +0,0 @@
    19.4 -
    19.5 -module jtag_tap(
    19.6 -	output tck,
    19.7 -	output tdi,
    19.8 -	input tdo,
    19.9 -	output capture,
   19.10 -	output shift,
   19.11 -	output e1dr,
   19.12 -	output update,
   19.13 -	output reset
   19.14 -);
   19.15 -
   19.16 -// Unfortunately the exit1 state for DR (e1dr) is mising
   19.17 -// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
   19.18 -wire g_capture;
   19.19 -wire g_shift;
   19.20 -wire g_update;
   19.21 -reg update_delay;
   19.22 -
   19.23 -assign capture = g_capture & sel;
   19.24 -assign shift = g_shift & sel;
   19.25 -assign e1dr = g_update & sel;
   19.26 -assign update = update_delay;
   19.27 -
   19.28 -BSCAN_SPARTAN6 #(
   19.29 -	.JTAG_CHAIN(1)
   19.30 -) bscan (
   19.31 -	.CAPTURE(g_capture),
   19.32 -	.DRCK(tck),
   19.33 -	.RESET(reset),
   19.34 -	.RUNTEST(),
   19.35 -	.SEL(sel),
   19.36 -	.SHIFT(g_shift),
   19.37 -	.TCK(),
   19.38 -	.TDI(tdi),
   19.39 -	.TMS(),
   19.40 -	.UPDATE(g_update),
   19.41 -	.TDO(tdo)
   19.42 -);
   19.43 -
   19.44 -update_delay <= g_update;
   19.45 -
   19.46 -endmodule

    20.1 --- a/lm32_adder.v	Sun Mar 06 21:17:31 2011 +0000
    20.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.3 @@ -1,115 +0,0 @@
    20.4 -// =============================================================================
    20.5 -//                           COPYRIGHT NOTICE
    20.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    20.7 -// ALL RIGHTS RESERVED
    20.8 -// This confidential and proprietary software may be used only as authorised by
    20.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   20.10 -// The entire notice above must be reproduced on all authorized copies and
   20.11 -// copies may only be made to the extent permitted by a licensing agreement from
   20.12 -// Lattice Semiconductor Corporation.
   20.13 -//
   20.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   20.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   20.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   20.17 -// U.S.A                                   email: techsupport@latticesemi.com
   20.18 -// ============================================================================/
   20.19 -//                         FILE DETAILS
   20.20 -// Project          : LatticeMico32
   20.21 -// File             : lm32_adder.v
   20.22 -// Title            : Integer adder / subtractor with comparison flag generation 
   20.23 -// Dependencies     : lm32_include.v
   20.24 -// Version          : 6.1.17
   20.25 -//                  : Initial Release
   20.26 -// Version          : 7.0SP2, 3.0
   20.27 -//                  : No Change
   20.28 -// Version          : 3.1
   20.29 -//                  : No Change
   20.30 -// =============================================================================
   20.31 -
   20.32 -`include "lm32_include.v"
   20.33 -
   20.34 -/////////////////////////////////////////////////////
   20.35 -// Module interface
   20.36 -/////////////////////////////////////////////////////
   20.37 -
   20.38 -module lm32_adder (
   20.39 -    // ----- Inputs -------
   20.40 -    adder_op_x,
   20.41 -    adder_op_x_n,
   20.42 -    operand_0_x,
   20.43 -    operand_1_x,
   20.44 -    // ----- Outputs -------
   20.45 -    adder_result_x,
   20.46 -    adder_carry_n_x,
   20.47 -    adder_overflow_x
   20.48 -    );
   20.49 -
   20.50 -/////////////////////////////////////////////////////
   20.51 -// Inputs
   20.52 -/////////////////////////////////////////////////////
   20.53 -
   20.54 -input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
   20.55 -input adder_op_x_n;                                     // Inverted version of adder_op_x
   20.56 -input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
   20.57 -input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
   20.58 -
   20.59 -/////////////////////////////////////////////////////
   20.60 -// Outputs
   20.61 -/////////////////////////////////////////////////////
   20.62 -
   20.63 -output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
   20.64 -wire   [`LM32_WORD_RNG] adder_result_x;
   20.65 -output adder_carry_n_x;                                 // Inverted carry
   20.66 -wire   adder_carry_n_x;
   20.67 -output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
   20.68 -reg    adder_overflow_x;
   20.69 -    
   20.70 -/////////////////////////////////////////////////////
   20.71 -// Internal nets and registers 
   20.72 -/////////////////////////////////////////////////////
   20.73 -
   20.74 -wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
   20.75 -wire b_sign;                                            // Sign of operand 1
   20.76 -wire result_sign;                                       // Sign of result
   20.77 -
   20.78 -/////////////////////////////////////////////////////
   20.79 -// Instantiations 
   20.80 -/////////////////////////////////////////////////////
   20.81 -
   20.82 -lm32_addsub addsub (
   20.83 -    // ----- Inputs -----
   20.84 -    .DataA          (operand_0_x), 
   20.85 -    .DataB          (operand_1_x), 
   20.86 -    .Cin            (adder_op_x), 
   20.87 -    .Add_Sub        (adder_op_x_n), 
   20.88 -    // ----- Ouputs -----
   20.89 -    .Result         (adder_result_x), 
   20.90 -    .Cout           (adder_carry_n_x)
   20.91 -    );
   20.92 -
   20.93 -/////////////////////////////////////////////////////
   20.94 -// Combinational Logic
   20.95 -/////////////////////////////////////////////////////
   20.96 -
   20.97 -// Extract signs of operands and result
   20.98 -
   20.99 -assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
  20.100 -assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
  20.101 -assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
  20.102 -
  20.103 -// Determine whether an overflow occured when performing a subtraction
  20.104 -
  20.105 -always @(*)
  20.106 -begin    
  20.107 -    //  +ve - -ve = -ve -> overflow
  20.108 -    //  -ve - +ve = +ve -> overflow
  20.109 -    if  (   (!a_sign & b_sign & result_sign)
  20.110 -         || (a_sign & !b_sign & !result_sign)
  20.111 -        )
  20.112 -        adder_overflow_x = `TRUE;
  20.113 -    else
  20.114 -        adder_overflow_x = `FALSE;
  20.115 -end
  20.116 -    
  20.117 -endmodule
  20.118 -

    21.1 --- a/lm32_addsub.v	Sun Mar 06 21:17:31 2011 +0000
    21.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.3 @@ -1,98 +0,0 @@
    21.4 -// =============================================================================
    21.5 -//                           COPYRIGHT NOTICE
    21.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    21.7 -// ALL RIGHTS RESERVED
    21.8 -// This confidential and proprietary software may be used only as authorised by
    21.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   21.10 -// The entire notice above must be reproduced on all authorized copies and
   21.11 -// copies may only be made to the extent permitted by a licensing agreement from
   21.12 -// Lattice Semiconductor Corporation.
   21.13 -//
   21.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   21.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   21.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   21.17 -// U.S.A                                   email: techsupport@latticesemi.com
   21.18 -// =============================================================================/
   21.19 -//                         FILE DETAILS
   21.20 -// Project          : LatticeMico32
   21.21 -// File             : lm32_addsub.v
   21.22 -// Title            : PMI adder/subtractor.
   21.23 -// Version          : 6.1.17
   21.24 -//                  : Initial Release
   21.25 -// Version          : 7.0SP2, 3.0
   21.26 -//                  : No Change
   21.27 -// Version          : 3.1
   21.28 -//                  : No Change
   21.29 -// =============================================================================
   21.30 -
   21.31 -`include "lm32_include.v"
   21.32 -
   21.33 -/////////////////////////////////////////////////////
   21.34 -// Module interface
   21.35 -/////////////////////////////////////////////////////
   21.36 -
   21.37 -module lm32_addsub (
   21.38 -    // ----- Inputs -------
   21.39 -    DataA, 
   21.40 -    DataB, 
   21.41 -    Cin, 
   21.42 -    Add_Sub, 
   21.43 -    // ----- Outputs -------
   21.44 -    Result, 
   21.45 -    Cout
   21.46 -    );
   21.47 -
   21.48 -/////////////////////////////////////////////////////
   21.49 -// Inputs
   21.50 -/////////////////////////////////////////////////////
   21.51 -
   21.52 -input [31:0] DataA;
   21.53 -input [31:0] DataB;
   21.54 -input Cin;
   21.55 -input Add_Sub;
   21.56 -
   21.57 -/////////////////////////////////////////////////////
   21.58 -// Outputs
   21.59 -/////////////////////////////////////////////////////
   21.60 -
   21.61 -output [31:0] Result;
   21.62 -wire   [31:0] Result;
   21.63 -output Cout;
   21.64 -wire   Cout;
   21.65 -
   21.66 -/////////////////////////////////////////////////////
   21.67 -// Instantiations
   21.68 -///////////////////////////////////////////////////// 
   21.69 -
   21.70 -// Only use Lattice specific constructs when compiling with ispLEVER
   21.71 -`ifdef PLATFORM_LATTICE
   21.72 -       generate
   21.73 -	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
   21.74 -`endif
   21.75 -	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
   21.76 -	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
   21.77 -   
   21.78 -	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
   21.79 -	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
   21.80 -`ifdef PLATFORM_LATTICE
   21.81 -	  end else begin
   21.82 -	    pmi_addsub #(// ----- Parameters -------
   21.83 -			 .pmi_data_width     (32),
   21.84 -			 .pmi_result_width   (32),
   21.85 -			 .pmi_sign           ("off"),
   21.86 -			 .pmi_family         (`LATTICE_FAMILY),
   21.87 -			 .module_type        ("pmi_addsub")) 
   21.88 -	      addsub    (// ----- Inputs -------
   21.89 -			 .DataA              (DataA),
   21.90 -			 .DataB              (DataB),
   21.91 -			 .Cin                (Cin),
   21.92 -			 .Add_Sub            (Add_Sub),
   21.93 -			 // ----- Outputs -------
   21.94 -			 .Result             (Result),
   21.95 -			 .Cout               (Cout),
   21.96 -			 .Overflow           ());
   21.97 -	  end
   21.98 -       endgenerate 
   21.99 -`endif
  21.100 -
  21.101 -endmodule

    22.1 --- a/lm32_cpu.v	Sun Mar 06 21:17:31 2011 +0000
    22.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.3 @@ -1,2717 +0,0 @@
    22.4 -// =============================================================================
    22.5 -//                           COPYRIGHT NOTICE
    22.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation
    22.7 -// ALL RIGHTS RESERVED
    22.8 -// This confidential and proprietary software may be used only as authorised by
    22.9 -// a licensing agreement from Lattice Semiconductor Corporation.
   22.10 -// The entire notice above must be reproduced on all authorized copies and
   22.11 -// copies may only be made to the extent permitted by a licensing agreement from
   22.12 -// Lattice Semiconductor Corporation.
   22.13 -//
   22.14 -// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   22.15 -// 5555 NE Moore Court                            408-826-6000 (other locations)
   22.16 -// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   22.17 -// U.S.A                                   email: techsupport@latticesemi.com
   22.18 -// =============================================================================/
   22.19 -//                         FILE DETAILS
   22.20 -// Project          : LatticeMico32
   22.21 -// File             : lm32_cpu.v
   22.22 -// Title            : Top-level of CPU.
   22.23 -// Dependencies     : lm32_include.v
   22.24 -//
   22.25 -// Version 3.4
   22.26 -// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
   22.27 -//    never serviced.
   22.28 -//    
   22.29 -// Version 3.3
   22.30 -// 1. Feature: Support for memory that is tightly coupled to processor core, and 
   22.31 -//    has a single-cycle access latency (same as caches). Instruction port has
   22.32 -//    access to a dedicated physically-mapped memory. Data port has access to
   22.33 -//    a dedicated physically-mapped memory. In order to be able to manipulate
   22.34 -//    values in both these memories via the debugger, these memories also
   22.35 -//    interface with the data port of LM32.
   22.36 -// 2. Feature: Extended Configuration Register
   22.37 -// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
   22.38 -//    Verilog.
   22.39 -//
   22.40 -// Version 3.2
   22.41 -// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
   22.42 -//    hang. At the same time CPU fails to register data bus error exception. Bug
   22.43 -//    is caused because (a) data bus error exception occurs after load/store has
   22.44 -//    passed X stage and next sequential instruction (e.g., brk) is already in X
   22.45 -//    stage, and (b) data bus error exception had lower priority than, say, brk
   22.46 -//    exception.
   22.47 -// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
   22.48 -//    invalid location, CPU will fail to register data bus error exception. The
   22.49 -//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
   22.50 -//    until load/store has completed.
   22.51 -// 3. Feature: Enable precise identification of load/store that causes seg fault.
   22.52 -// 4. SYNC resets used for register file when implemented in EBRs.
   22.53 -//
   22.54 -// Version 3.1
   22.55 -// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
   22.56 -//    instead of distributed memory by enabling the option in LM32 GUI. 
   22.57 -// 2. Feature: LM32 also adds a static branch predictor to improve branch 
   22.58 -//    performance. All immediate-based forward-pointing branches are predicted 
   22.59 -//    not-taken. All immediate-based backward-pointing branches are predicted taken.
   22.60 -// 
   22.61 -// Version 7.0SP2, 3.0
   22.62 -// No Change
   22.63 -//
   22.64 -// Version 6.1.17
   22.65 -// Initial Release
   22.66 -// =============================================================================
   22.67 -
   22.68 -`include "lm32_include.v"
   22.69 -
   22.70 -/////////////////////////////////////////////////////
   22.71 -// Module interface
   22.72 -/////////////////////////////////////////////////////
   22.73 -
   22.74 -module lm32_cpu (
   22.75 -    // ----- Inputs -------
   22.76 -    clk_i,
   22.77 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   22.78 -    clk_n_i,
   22.79 -`endif    
   22.80 -    rst_i,
   22.81 -    // From external devices
   22.82 -`ifdef CFG_INTERRUPTS_ENABLED
   22.83 -    interrupt,
   22.84 -`endif
   22.85 -    // From user logic
   22.86 -`ifdef CFG_USER_ENABLED
   22.87 -    user_result,
   22.88 -    user_complete,
   22.89 -`endif     
   22.90 -`ifdef CFG_JTAG_ENABLED
   22.91 -    // From JTAG
   22.92 -    jtag_clk,
   22.93 -    jtag_update, 
   22.94 -    jtag_reg_q,
   22.95 -    jtag_reg_addr_q,
   22.96 -`endif
   22.97 -`ifdef CFG_IWB_ENABLED
   22.98 -    // Instruction Wishbone master
   22.99 -    I_DAT_I,
  22.100 -    I_ACK_I,
  22.101 -    I_ERR_I,
  22.102 -    I_RTY_I,
  22.103 -`endif
  22.104 -    // Data Wishbone master
  22.105 -    D_DAT_I,
  22.106 -    D_ACK_I,
  22.107 -    D_ERR_I,
  22.108 -    D_RTY_I,
  22.109 -    // ----- Outputs -------
  22.110 -`ifdef CFG_TRACE_ENABLED
  22.111 -    trace_pc,
  22.112 -    trace_pc_valid,
  22.113 -    trace_exception,
  22.114 -    trace_eid,
  22.115 -    trace_eret,
  22.116 -`ifdef CFG_DEBUG_ENABLED
  22.117 -    trace_bret,
  22.118 -`endif
  22.119 -`endif
  22.120 -`ifdef CFG_JTAG_ENABLED
  22.121 -    jtag_reg_d,
  22.122 -    jtag_reg_addr_d,
  22.123 -`endif
  22.124 -`ifdef CFG_USER_ENABLED    
  22.125 -    user_valid,
  22.126 -    user_opcode,
  22.127 -    user_operand_0,
  22.128 -    user_operand_1,
  22.129 -`endif    
  22.130 -`ifdef CFG_IWB_ENABLED
  22.131 -    // Instruction Wishbone master
  22.132 -    I_DAT_O,
  22.133 -    I_ADR_O,
  22.134 -    I_CYC_O,
  22.135 -    I_SEL_O,
  22.136 -    I_STB_O,
  22.137 -    I_WE_O,
  22.138 -    I_CTI_O,
  22.139 -    I_LOCK_O,
  22.140 -    I_BTE_O,
  22.141 -`endif
  22.142 -    // Data Wishbone master
  22.143 -    D_DAT_O,
  22.144 -    D_ADR_O,
  22.145 -    D_CYC_O,
  22.146 -    D_SEL_O,
  22.147 -    D_STB_O,
  22.148 -    D_WE_O,
  22.149 -    D_CTI_O,
  22.150 -    D_LOCK_O,
  22.151 -    D_BTE_O
  22.152 -    );
  22.153 -
  22.154 -/////////////////////////////////////////////////////
  22.155 -// Parameters
  22.156 -/////////////////////////////////////////////////////
  22.157 -
  22.158 -parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
  22.159 -`ifdef CFG_DEBUG_ENABLED
  22.160 -parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
  22.161 -`endif
  22.162 -
  22.163 -`ifdef CFG_ICACHE_ENABLED
  22.164 -parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  22.165 -parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
  22.166 -parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  22.167 -parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
  22.168 -parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
  22.169 -`else
  22.170 -parameter icache_associativity = 1;    
  22.171 -parameter icache_sets = 512;                      
  22.172 -parameter icache_bytes_per_line = 16;  
  22.173 -parameter icache_base_address = 0;      
  22.174 -parameter icache_limit = 0;                    
  22.175 -`endif
  22.176 -
  22.177 -`ifdef CFG_DCACHE_ENABLED
  22.178 -parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
  22.179 -parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
  22.180 -parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
  22.181 -parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
  22.182 -parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
  22.183 -`else
  22.184 -parameter dcache_associativity = 1;    
  22.185 -parameter dcache_sets = 512;                      
  22.186 -parameter dcache_bytes_per_line = 16;  
  22.187 -parameter dcache_base_address = 0;      
  22.188 -parameter dcache_limit = 0;                    
  22.189 -`endif
  22.190 -
  22.191 -`ifdef CFG_DEBUG_ENABLED
  22.192 -parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
  22.193 -`else
  22.194 -parameter watchpoints = 0;
  22.195 -`endif
  22.196 -`ifdef CFG_ROM_DEBUG_ENABLED
  22.197 -parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
  22.198 -`else
  22.199 -parameter breakpoints = 0;
  22.200 -`endif
  22.201 -
  22.202 -`ifdef CFG_INTERRUPTS_ENABLED
  22.203 -parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
  22.204 -`else
  22.205 -parameter interrupts = 0;
  22.206 -`endif
  22.207 -
  22.208 -/////////////////////////////////////////////////////
  22.209 -// Inputs
  22.210 -/////////////////////////////////////////////////////
  22.211 -
  22.212 -input clk_i;                                    // Clock
  22.213 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  22.214 -input clk_n_i;                                  // Inverted clock
  22.215 -`endif    
  22.216 -input rst_i;                                    // Reset
  22.217 -
  22.218 -`ifdef CFG_INTERRUPTS_ENABLED
  22.219 -input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
  22.220 -`endif
  22.221 -
  22.222 -`ifdef CFG_USER_ENABLED
  22.223 -input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
  22.224 -input user_complete;                            // User-defined instruction execution is complete
  22.225 -`endif    
  22.226 -
  22.227 -`ifdef CFG_JTAG_ENABLED
  22.228 -input jtag_clk;                                 // JTAG clock
  22.229 -input jtag_update;                              // JTAG state machine is in data register update state
  22.230 -input [`LM32_BYTE_RNG] jtag_reg_q;              
  22.231 -input [2:0] jtag_reg_addr_q;
  22.232 -`endif
  22.233 -
  22.234 -`ifdef CFG_IWB_ENABLED
  22.235 -input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
  22.236 -input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
  22.237 -input I_ERR_I;                                  // Instruction Wishbone interface error
  22.238 -input I_RTY_I;                                  // Instruction Wishbone interface retry
  22.239 -`endif
  22.240 -
  22.241 -input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
  22.242 -input D_ACK_I;                                  // Data Wishbone interface acknowledgement
  22.243 -input D_ERR_I;                                  // Data Wishbone interface error
  22.244 -input D_RTY_I;                                  // Data Wishbone interface retry
  22.245 -
  22.246 -/////////////////////////////////////////////////////
  22.247 -// Outputs
  22.248 -/////////////////////////////////////////////////////
  22.249 -
  22.250 -`ifdef CFG_TRACE_ENABLED
  22.251 -output [`LM32_PC_RNG] trace_pc;                 // PC to trace
  22.252 -reg    [`LM32_PC_RNG] trace_pc;
  22.253 -output trace_pc_valid;                          // Indicates that a new trace PC is valid
  22.254 -reg    trace_pc_valid;
  22.255 -output trace_exception;                         // Indicates an exception has occured
  22.256 -reg    trace_exception;
  22.257 -output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
  22.258 -reg    [`LM32_EID_RNG] trace_eid;
  22.259 -output trace_eret;                              // Indicates an eret instruction has been executed
  22.260 -reg    trace_eret;
  22.261 -`ifdef CFG_DEBUG_ENABLED
  22.262 -output trace_bret;                              // Indicates a bret instruction has been executed
  22.263 -reg    trace_bret;
  22.264 -`endif
  22.265 -`endif
  22.266 -
  22.267 -`ifdef CFG_JTAG_ENABLED
  22.268 -output [`LM32_BYTE_RNG] jtag_reg_d;
  22.269 -wire   [`LM32_BYTE_RNG] jtag_reg_d;
  22.270 -output [2:0] jtag_reg_addr_d;
  22.271 -wire   [2:0] jtag_reg_addr_d;
  22.272 -`endif
  22.273 -
  22.274 -`ifdef CFG_USER_ENABLED
  22.275 -output user_valid;                              // Indicates if user_opcode is valid
  22.276 -wire   user_valid;
  22.277 -output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
  22.278 -reg    [`LM32_USER_OPCODE_RNG] user_opcode;
  22.279 -output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
  22.280 -wire   [`LM32_WORD_RNG] user_operand_0;
  22.281 -output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
  22.282 -wire   [`LM32_WORD_RNG] user_operand_1;
  22.283 -`endif
  22.284 -
  22.285 -`ifdef CFG_IWB_ENABLED
  22.286 -output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
  22.287 -wire   [`LM32_WORD_RNG] I_DAT_O;
  22.288 -output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
  22.289 -wire   [`LM32_WORD_RNG] I_ADR_O;
  22.290 -output I_CYC_O;                                 // Instruction Wishbone interface cycle
  22.291 -wire   I_CYC_O;
  22.292 -output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
  22.293 -wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
  22.294 -output I_STB_O;                                 // Instruction Wishbone interface strobe
  22.295 -wire   I_STB_O;
  22.296 -output I_WE_O;                                  // Instruction Wishbone interface write enable
  22.297 -wire   I_WE_O;
  22.298 -output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
  22.299 -wire   [`LM32_CTYPE_RNG] I_CTI_O;
  22.300 -output I_LOCK_O;                                // Instruction Wishbone interface lock bus
  22.301 -wire   I_LOCK_O;
  22.302 -output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
  22.303 -wire   [`LM32_BTYPE_RNG] I_BTE_O;
  22.304 -`endif
  22.305 -
  22.306 -output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
  22.307 -wire   [`LM32_WORD_RNG] D_DAT_O;
  22.308 -output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
  22.309 -wire   [`LM32_WORD_RNG] D_ADR_O;
  22.310 -output D_CYC_O;                                 // Data Wishbone interface cycle
  22.311 -wire   D_CYC_O;
  22.312 -output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
  22.313 -wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
  22.314 -output D_STB_O;                                 // Data Wishbone interface strobe
  22.315 -wire   D_STB_O;
  22.316 -output D_WE_O;                                  // Data Wishbone interface write enable
  22.317 -wire   D_WE_O;
  22.318 -output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
  22.319 -wire   [`LM32_CTYPE_RNG] D_CTI_O;
  22.320 -output D_LOCK_O;                                // Date Wishbone interface lock bus
  22.321 -wire   D_LOCK_O;
  22.322 -output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
  22.323 -wire   [`LM32_BTYPE_RNG] D_BTE_O;
  22.324 -
  22.325 -/////////////////////////////////////////////////////
  22.326 -// Internal nets and registers 
  22.327 -/////////////////////////////////////////////////////
  22.328 -
  22.329 -// Pipeline registers
  22.330 -
  22.331 -`ifdef LM32_CACHE_ENABLED
  22.332 -reg valid_a;                                    // Instruction in A stage is valid
  22.333 -`endif
  22.334 -reg valid_f;                                    // Instruction in F stage is valid
  22.335 -reg valid_d;                                    // Instruction in D stage is valid
  22.336 -reg valid_x;                                    // Instruction in X stage is valid
  22.337 -reg valid_m;                                    // Instruction in M stage is valid
  22.338 -reg valid_w;                                    // Instruction in W stage is valid
  22.339 -   
  22.340 -wire q_x;
  22.341 -wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
  22.342 -wire load_d;                                    // Indicates a load instruction
  22.343 -reg load_x;                                     
  22.344 -reg load_m;
  22.345 -wire load_q_x;
  22.346 -wire store_q_x;
  22.347 -wire store_d;                                   // Indicates a store instruction
  22.348 -reg store_x;
  22.349 -reg store_m;
  22.350 -wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
  22.351 -reg [`LM32_SIZE_RNG] size_x;
  22.352 -wire branch_d;                                  // Indicates a branch instruction
  22.353 -wire branch_predict_d;                          // Indicates a branch is predicted
  22.354 -wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
  22.355 -wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
  22.356 -wire [`LM32_PC_RNG] branch_target_d;
  22.357 -wire bi_unconditional;
  22.358 -wire bi_conditional;
  22.359 -reg branch_x;                                   
  22.360 -reg branch_predict_x;
  22.361 -reg branch_predict_taken_x;
  22.362 -reg branch_m;
  22.363 -reg branch_predict_m;
  22.364 -reg branch_predict_taken_m;
  22.365 -wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
  22.366 -wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
  22.367 -wire branch_reg_d;                              // Branch to register or immediate
  22.368 -wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
  22.369 -reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
  22.370 -reg [`LM32_PC_RNG] branch_target_m;
  22.371 -wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
  22.372 -wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
  22.373 -
  22.374 -wire x_result_sel_csr_d;                        // Select X stage result from CSRs
  22.375 -reg x_result_sel_csr_x;
  22.376 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.377 -wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
  22.378 -reg x_result_sel_mc_arith_x;
  22.379 -`endif
  22.380 -`ifdef LM32_NO_BARREL_SHIFT    
  22.381 -wire x_result_sel_shift_d;                      // Select X stage result from shifter
  22.382 -reg x_result_sel_shift_x;
  22.383 -`endif
  22.384 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.385 -wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
  22.386 -reg x_result_sel_sext_x;
  22.387 -`endif
  22.388 -wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
  22.389 -reg x_result_sel_logic_x;
  22.390 -`ifdef CFG_USER_ENABLED
  22.391 -wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
  22.392 -reg x_result_sel_user_x;
  22.393 -`endif
  22.394 -wire x_result_sel_add_d;                        // Select X stage result from adder
  22.395 -reg x_result_sel_add_x;
  22.396 -wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
  22.397 -reg m_result_sel_compare_x;
  22.398 -reg m_result_sel_compare_m;
  22.399 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.400 -wire m_result_sel_shift_d;                      // Select M stage result from shifter
  22.401 -reg m_result_sel_shift_x;
  22.402 -reg m_result_sel_shift_m;
  22.403 -`endif
  22.404 -wire w_result_sel_load_d;                       // Select W stage result from load/store unit
  22.405 -reg w_result_sel_load_x;
  22.406 -reg w_result_sel_load_m;
  22.407 -reg w_result_sel_load_w;
  22.408 -`ifdef CFG_PL_MULTIPLY_ENABLED
  22.409 -wire w_result_sel_mul_d;                        // Select W stage result from multiplier
  22.410 -reg w_result_sel_mul_x;
  22.411 -reg w_result_sel_mul_m;
  22.412 -reg w_result_sel_mul_w;
  22.413 -`endif
  22.414 -wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
  22.415 -reg x_bypass_enable_x;                          
  22.416 -wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
  22.417 -reg m_bypass_enable_x;                          
  22.418 -reg m_bypass_enable_m;
  22.419 -wire sign_extend_d;                             // Whether to sign-extend or zero-extend
  22.420 -reg sign_extend_x;
  22.421 -wire write_enable_d;                            // Register file write enable
  22.422 -reg write_enable_x;
  22.423 -wire write_enable_q_x;
  22.424 -reg write_enable_m;
  22.425 -wire write_enable_q_m;
  22.426 -reg write_enable_w;
  22.427 -wire write_enable_q_w;
  22.428 -wire read_enable_0_d;                           // Register file read enable 0
  22.429 -wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
  22.430 -wire read_enable_1_d;                           // Register file read enable 1
  22.431 -wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
  22.432 -wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
  22.433 -reg [`LM32_REG_IDX_RNG] write_idx_x;            
  22.434 -reg [`LM32_REG_IDX_RNG] write_idx_m;
  22.435 -reg [`LM32_REG_IDX_RNG] write_idx_w;
  22.436 -wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
  22.437 -reg  [`LM32_CSR_RNG] csr_x;                  
  22.438 -wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
  22.439 -reg [`LM32_CONDITION_RNG] condition_x;          
  22.440 -`ifdef CFG_DEBUG_ENABLED
  22.441 -wire break_d;                                   // Indicates a break instruction
  22.442 -reg break_x;                                    
  22.443 -`endif
  22.444 -wire scall_d;                                   // Indicates a scall instruction
  22.445 -reg scall_x;    
  22.446 -wire eret_d;                                    // Indicates an eret instruction
  22.447 -reg eret_x;
  22.448 -wire eret_q_x;
  22.449 -reg eret_m;
  22.450 -`ifdef CFG_TRACE_ENABLED
  22.451 -reg eret_w;
  22.452 -`endif
  22.453 -`ifdef CFG_DEBUG_ENABLED
  22.454 -wire bret_d;                                    // Indicates a bret instruction
  22.455 -reg bret_x;
  22.456 -wire bret_q_x;
  22.457 -reg bret_m;
  22.458 -`ifdef CFG_TRACE_ENABLED
  22.459 -reg bret_w;
  22.460 -`endif
  22.461 -`endif
  22.462 -wire csr_write_enable_d;                        // CSR write enable
  22.463 -reg csr_write_enable_x;
  22.464 -wire csr_write_enable_q_x;
  22.465 -`ifdef CFG_USER_ENABLED
  22.466 -wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
  22.467 -`endif
  22.468 -
  22.469 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.470 -wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
  22.471 -reg bus_error_x;
  22.472 -reg data_bus_error_exception_m;
  22.473 -reg [`LM32_PC_RNG] memop_pc_w;
  22.474 -`endif
  22.475 -
  22.476 -reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
  22.477 -reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
  22.478 -reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
  22.479 -reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
  22.480 -reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
  22.481 -
  22.482 -reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
  22.483 -reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
  22.484 -reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
  22.485 -reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
  22.486 -reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
  22.487 -
  22.488 -// To/from register file
  22.489 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.490 -reg [`LM32_WORD_RNG] reg_data_live_0;          
  22.491 -reg [`LM32_WORD_RNG] reg_data_live_1;  
  22.492 -reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
  22.493 -reg [`LM32_WORD_RNG] reg_data_buf_0;
  22.494 -reg [`LM32_WORD_RNG] reg_data_buf_1;
  22.495 -`endif
  22.496 -`ifdef LM32_EBR_REGISTER_FILE
  22.497 -`else
  22.498 -reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
  22.499 -`endif
  22.500 -wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
  22.501 -wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
  22.502 -reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
  22.503 -reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
  22.504 -wire reg_write_enable_q_w;
  22.505 -
  22.506 -reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
  22.507 -
  22.508 -wire stall_a;                                   // Stall instruction in A pipeline stage
  22.509 -wire stall_f;                                   // Stall instruction in F pipeline stage
  22.510 -wire stall_d;                                   // Stall instruction in D pipeline stage
  22.511 -wire stall_x;                                   // Stall instruction in X pipeline stage
  22.512 -wire stall_m;                                   // Stall instruction in M pipeline stage
  22.513 -
  22.514 -// To/from adder
  22.515 -wire adder_op_d;                                // Whether to add or subtract
  22.516 -reg adder_op_x;                                 
  22.517 -reg adder_op_x_n;                               // Inverted version of adder_op_x
  22.518 -wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
  22.519 -wire adder_overflow_x;                          // Whether a signed overflow occured
  22.520 -wire adder_carry_n_x;                           // Whether a carry was generated
  22.521 -
  22.522 -// To/from logical operations unit
  22.523 -wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
  22.524 -reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
  22.525 -wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
  22.526 -
  22.527 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.528 -// From sign-extension unit
  22.529 -wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
  22.530 -wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
  22.531 -wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
  22.532 -`endif
  22.533 -
  22.534 -// To/from shifter
  22.535 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.536 -`ifdef CFG_ROTATE_ENABLED
  22.537 -wire rotate_d;                                  // Whether we should rotate or shift
  22.538 -reg rotate_x;                                    
  22.539 -`endif
  22.540 -wire direction_d;                               // Which direction to shift in
  22.541 -reg direction_x;                                        
  22.542 -wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
  22.543 -`endif
  22.544 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  22.545 -wire shift_left_d;                              // Indicates whether to perform a left shift or not
  22.546 -wire shift_left_q_d;
  22.547 -wire shift_right_d;                             // Indicates whether to perform a right shift or not
  22.548 -wire shift_right_q_d;
  22.549 -`endif
  22.550 -`ifdef LM32_NO_BARREL_SHIFT
  22.551 -wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
  22.552 -`endif
  22.553 -
  22.554 -// To/from multiplier
  22.555 -`ifdef LM32_MULTIPLY_ENABLED
  22.556 -wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
  22.557 -`endif
  22.558 -`ifdef CFG_MC_MULTIPLY_ENABLED
  22.559 -wire multiply_d;                                // Indicates whether to perform a multiply or not
  22.560 -wire multiply_q_d;
  22.561 -`endif
  22.562 -
  22.563 -// To/from divider
  22.564 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.565 -wire divide_d;                                  // Indicates whether to perform a divider or not
  22.566 -wire divide_q_d;
  22.567 -wire modulus_d;
  22.568 -wire modulus_q_d;
  22.569 -wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
  22.570 -`endif
  22.571 -
  22.572 -// To from multi-cycle arithmetic unit
  22.573 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.574 -wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
  22.575 -wire [`LM32_WORD_RNG] mc_result_x;
  22.576 -`endif
  22.577 -
  22.578 -// From CSRs
  22.579 -`ifdef CFG_INTERRUPTS_ENABLED
  22.580 -wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
  22.581 -`endif
  22.582 -wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
  22.583 -wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
  22.584 -`ifdef CFG_CYCLE_COUNTER_ENABLED
  22.585 -reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
  22.586 -`endif
  22.587 -reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
  22.588 -
  22.589 -// To/from instruction unit
  22.590 -wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
  22.591 -wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
  22.592 -wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
  22.593 -wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
  22.594 -wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
  22.595 -`ifdef CFG_TRACE_ENABLED
  22.596 -reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
  22.597 -`endif
  22.598 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.599 -wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
  22.600 -`endif
  22.601 -//pragma attribute instruction_d preserve_signal true
  22.602 -//pragma attribute instruction_d preserve_driver true
  22.603 -wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
  22.604 -`ifdef CFG_ICACHE_ENABLED
  22.605 -wire iflush;                                    // Flush instruction cache
  22.606 -wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
  22.607 -wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
  22.608 -wire icache_refill_request;                     // Request to refill instruction cache
  22.609 -wire icache_refilling;                          // Indicates the instruction cache is being refilled
  22.610 -`endif
  22.611 -`ifdef CFG_IROM_ENABLED
  22.612 -wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
  22.613 -wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
  22.614 -wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
  22.615 -wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
  22.616 -wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
  22.617 -`endif
  22.618 -
  22.619 -// To/from load/store unit
  22.620 -`ifdef CFG_DCACHE_ENABLED
  22.621 -wire dflush_x;                                  // Flush data cache    
  22.622 -reg dflush_m;                                    
  22.623 -wire dcache_stall_request;                      // Stall pipeline because data cache is busy
  22.624 -wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
  22.625 -wire dcache_refill_request;                     // Request to refill data cache
  22.626 -wire dcache_refilling;                          // Indicates the data cache is being refilled
  22.627 -`endif
  22.628 -wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
  22.629 -wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
  22.630 -
  22.631 -// To/from JTAG interface
  22.632 -`ifdef CFG_JTAG_ENABLED
  22.633 -`ifdef CFG_JTAG_UART_ENABLED
  22.634 -wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
  22.635 -wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
  22.636 -`endif
  22.637 -`ifdef CFG_HW_DEBUG_ENABLED
  22.638 -wire jtag_csr_write_enable;                     // Debugger CSR write enable
  22.639 -wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
  22.640 -wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
  22.641 -wire jtag_read_enable;                          
  22.642 -wire [`LM32_BYTE_RNG] jtag_read_data;
  22.643 -wire jtag_write_enable;
  22.644 -wire [`LM32_BYTE_RNG] jtag_write_data;
  22.645 -wire [`LM32_WORD_RNG] jtag_address;
  22.646 -wire jtag_access_complete;
  22.647 -`endif
  22.648 -`ifdef CFG_DEBUG_ENABLED
  22.649 -wire jtag_break;                                // Request from debugger to raise a breakpoint
  22.650 -`endif
  22.651 -`endif
  22.652 -
  22.653 -// Hazzard detection
  22.654 -wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
  22.655 -wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
  22.656 -wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
  22.657 -wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
  22.658 -wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
  22.659 -wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
  22.660 -
  22.661 -// Control flow
  22.662 -wire cmp_zero;                                  // Result of comparison is zero
  22.663 -wire cmp_negative;                              // Result of comparison is negative
  22.664 -wire cmp_overflow;                              // Comparison produced an overflow
  22.665 -wire cmp_carry_n;                               // Comparison produced a carry, inverted
  22.666 -reg condition_met_x;                            // Condition of branch instruction is met
  22.667 -reg condition_met_m;
  22.668 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  22.669 -wire branch_taken_x;                            // Branch is taken in X stage
  22.670 -`endif
  22.671 -wire branch_taken_m;                            // Branch is taken in M stage
  22.672 -
  22.673 -wire kill_f;                                    // Kill instruction in F stage
  22.674 -wire kill_d;                                    // Kill instruction in D stage
  22.675 -wire kill_x;                                    // Kill instruction in X stage
  22.676 -wire kill_m;                                    // Kill instruction in M stage
  22.677 -wire kill_w;                                    // Kill instruction in W stage
  22.678 -
  22.679 -reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
  22.680 -`ifdef CFG_DEBUG_ENABLED
  22.681 -reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
  22.682 -`endif
  22.683 -reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
  22.684 -`ifdef CFG_TRACE_ENABLED
  22.685 -reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
  22.686 -reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
  22.687 -`endif
  22.688 -
  22.689 -`ifdef CFG_DEBUG_ENABLED
  22.690 -`ifdef LM32_SINGLE_STEP_ENABLED
  22.691 -wire dc_ss;                                     // Is single-step enabled
  22.692 -`endif
  22.693 -wire dc_re;                                     // Remap all exceptions
  22.694 -wire exception_x;                               // An exception occured in the X stage
  22.695 -reg exception_m;                                // An instruction that caused an exception is in the M stage
  22.696 -wire debug_exception_x;                         // Indicates if a debug exception has occured
  22.697 -reg debug_exception_m;
  22.698 -reg debug_exception_w;
  22.699 -wire debug_exception_q_w;
  22.700 -wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
  22.701 -reg non_debug_exception_m;
  22.702 -reg non_debug_exception_w;
  22.703 -wire non_debug_exception_q_w;
  22.704 -`else
  22.705 -wire exception_x;                               // Indicates if a debug exception has occured
  22.706 -reg exception_m;
  22.707 -reg exception_w;
  22.708 -wire exception_q_w;
  22.709 -`endif
  22.710 -
  22.711 -`ifdef CFG_DEBUG_ENABLED
  22.712 -`ifdef CFG_JTAG_ENABLED
  22.713 -wire reset_exception;                           // Indicates if a reset exception has occured
  22.714 -`endif
  22.715 -`endif
  22.716 -`ifdef CFG_INTERRUPTS_ENABLED
  22.717 -wire interrupt_exception;                       // Indicates if an interrupt exception has occured
  22.718 -`endif
  22.719 -`ifdef CFG_DEBUG_ENABLED
  22.720 -wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
  22.721 -wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
  22.722 -`endif
  22.723 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.724 -wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
  22.725 -wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
  22.726 -`endif
  22.727 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.728 -wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
  22.729 -`endif
  22.730 -wire system_call_exception;                     // Indicates if a system call exception has occured
  22.731 -
  22.732 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.733 -reg data_bus_error_seen;                        // Indicates if a data bus error was seen
  22.734 -`endif
  22.735 -
  22.736 -/////////////////////////////////////////////////////
  22.737 -// Functions
  22.738 -/////////////////////////////////////////////////////
  22.739 -
  22.740 -`include "lm32_functions.v"
  22.741 -
  22.742 -/////////////////////////////////////////////////////
  22.743 -// Instantiations
  22.744 -///////////////////////////////////////////////////// 
  22.745 -
  22.746 -// Instruction unit
  22.747 -lm32_instruction_unit #(
  22.748 -    .associativity          (icache_associativity),
  22.749 -    .sets                   (icache_sets),
  22.750 -    .bytes_per_line         (icache_bytes_per_line),
  22.751 -    .base_address           (icache_base_address),
  22.752 -    .limit                  (icache_limit)
  22.753 -  ) instruction_unit (
  22.754 -    // ----- Inputs -------
  22.755 -    .clk_i                  (clk_i),
  22.756 -    .rst_i                  (rst_i),
  22.757 -    // From pipeline
  22.758 -    .stall_a                (stall_a),
  22.759 -    .stall_f                (stall_f),
  22.760 -    .stall_d                (stall_d),
  22.761 -    .stall_x                (stall_x),
  22.762 -    .stall_m                (stall_m),
  22.763 -    .valid_f                (valid_f),
  22.764 -    .valid_d                (valid_d),
  22.765 -    .kill_f                 (kill_f),
  22.766 -    .branch_predict_taken_d (branch_predict_taken_d),
  22.767 -    .branch_predict_address_d (branch_predict_address_d),
  22.768 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  22.769 -    .branch_taken_x         (branch_taken_x),
  22.770 -    .branch_target_x        (branch_target_x),
  22.771 -`endif
  22.772 -    .exception_m            (exception_m),
  22.773 -    .branch_taken_m         (branch_taken_m),
  22.774 -    .branch_mispredict_taken_m (branch_mispredict_taken_m),
  22.775 -    .branch_target_m        (branch_target_m),
  22.776 -`ifdef CFG_ICACHE_ENABLED
  22.777 -    .iflush                 (iflush),
  22.778 -`endif
  22.779 -`ifdef CFG_IROM_ENABLED
  22.780 -    .irom_store_data_m      (irom_store_data_m),
  22.781 -    .irom_address_xm        (irom_address_xm),
  22.782 -    .irom_we_xm             (irom_we_xm),
  22.783 -`endif
  22.784 -`ifdef CFG_DCACHE_ENABLED
  22.785 -    .dcache_restart_request (dcache_restart_request),
  22.786 -    .dcache_refill_request  (dcache_refill_request),
  22.787 -    .dcache_refilling       (dcache_refilling),
  22.788 -`endif        
  22.789 -`ifdef CFG_IWB_ENABLED
  22.790 -    // From Wishbone
  22.791 -    .i_dat_i                (I_DAT_I),
  22.792 -    .i_ack_i                (I_ACK_I),
  22.793 -    .i_err_i                (I_ERR_I),
  22.794 -`endif
  22.795 -`ifdef CFG_HW_DEBUG_ENABLED
  22.796 -    .jtag_read_enable       (jtag_read_enable),
  22.797 -    .jtag_write_enable      (jtag_write_enable),
  22.798 -    .jtag_write_data        (jtag_write_data),
  22.799 -    .jtag_address           (jtag_address),
  22.800 -`endif
  22.801 -    // ----- Outputs -------
  22.802 -    // To pipeline
  22.803 -    .pc_f                   (pc_f),
  22.804 -    .pc_d                   (pc_d),
  22.805 -    .pc_x                   (pc_x),
  22.806 -    .pc_m                   (pc_m),
  22.807 -    .pc_w                   (pc_w),
  22.808 -`ifdef CFG_ICACHE_ENABLED
  22.809 -    .icache_stall_request   (icache_stall_request),
  22.810 -    .icache_restart_request (icache_restart_request),
  22.811 -    .icache_refill_request  (icache_refill_request),
  22.812 -    .icache_refilling       (icache_refilling),
  22.813 -`endif
  22.814 -`ifdef CFG_IROM_ENABLED
  22.815 -    .irom_data_m            (irom_data_m),
  22.816 -`endif
  22.817 -`ifdef CFG_IWB_ENABLED
  22.818 -    // To Wishbone
  22.819 -    .i_dat_o                (I_DAT_O),
  22.820 -    .i_adr_o                (I_ADR_O),
  22.821 -    .i_cyc_o                (I_CYC_O),
  22.822 -    .i_sel_o                (I_SEL_O),
  22.823 -    .i_stb_o                (I_STB_O),
  22.824 -    .i_we_o                 (I_WE_O),
  22.825 -    .i_cti_o                (I_CTI_O),
  22.826 -    .i_lock_o               (I_LOCK_O),
  22.827 -    .i_bte_o                (I_BTE_O),
  22.828 -`endif
  22.829 -`ifdef CFG_HW_DEBUG_ENABLED
  22.830 -    .jtag_read_data         (jtag_read_data),
  22.831 -    .jtag_access_complete   (jtag_access_complete),
  22.832 -`endif
  22.833 -`ifdef CFG_BUS_ERRORS_ENABLED
  22.834 -    .bus_error_d            (bus_error_d),
  22.835 -`endif
  22.836 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  22.837 -    .instruction_f          (instruction_f),
  22.838 -`endif
  22.839 -    .instruction_d          (instruction_d)
  22.840 -    );
  22.841 -
  22.842 -// Instruction decoder
  22.843 -lm32_decoder decoder (
  22.844 -    // ----- Inputs -------
  22.845 -    .instruction            (instruction_d),
  22.846 -    // ----- Outputs -------
  22.847 -    .d_result_sel_0         (d_result_sel_0_d),
  22.848 -    .d_result_sel_1         (d_result_sel_1_d),
  22.849 -    .x_result_sel_csr       (x_result_sel_csr_d),
  22.850 -`ifdef LM32_MC_ARITHMETIC_ENABLED
  22.851 -    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
  22.852 -`endif
  22.853 -`ifdef LM32_NO_BARREL_SHIFT    
  22.854 -    .x_result_sel_shift     (x_result_sel_shift_d),
  22.855 -`endif
  22.856 -`ifdef CFG_SIGN_EXTEND_ENABLED
  22.857 -    .x_result_sel_sext      (x_result_sel_sext_d),
  22.858 -`endif    
  22.859 -    .x_result_sel_logic     (x_result_sel_logic_d),
  22.860 -`ifdef CFG_USER_ENABLED
  22.861 -    .x_result_sel_user      (x_result_sel_user_d),
  22.862 -`endif
  22.863 -    .x_result_sel_add       (x_result_sel_add_d),
  22.864 -    .m_result_sel_compare   (m_result_sel_compare_d),
  22.865 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.866 -    .m_result_sel_shift     (m_result_sel_shift_d),  
  22.867 -`endif    
  22.868 -    .w_result_sel_load      (w_result_sel_load_d),
  22.869 -`ifdef CFG_PL_MULTIPLY_ENABLED
  22.870 -    .w_result_sel_mul       (w_result_sel_mul_d),
  22.871 -`endif
  22.872 -    .x_bypass_enable        (x_bypass_enable_d),
  22.873 -    .m_bypass_enable        (m_bypass_enable_d),
  22.874 -    .read_enable_0          (read_enable_0_d),
  22.875 -    .read_idx_0             (read_idx_0_d),
  22.876 -    .read_enable_1          (read_enable_1_d),
  22.877 -    .read_idx_1             (read_idx_1_d),
  22.878 -    .write_enable           (write_enable_d),
  22.879 -    .write_idx              (write_idx_d),
  22.880 -    .immediate              (immediate_d),
  22.881 -    .branch_offset          (branch_offset_d),
  22.882 -    .load                   (load_d),
  22.883 -    .store                  (store_d),
  22.884 -    .size                   (size_d),
  22.885 -    .sign_extend            (sign_extend_d),
  22.886 -    .adder_op               (adder_op_d),
  22.887 -    .logic_op               (logic_op_d),
  22.888 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  22.889 -    .direction              (direction_d),
  22.890 -`endif
  22.891 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  22.892 -    .shift_left             (shift_left_d),
  22.893 -    .shift_right            (shift_right_d),
  22.894 -`endif
  22.895 -`ifdef CFG_MC_MULTIPLY_ENABLED
  22.896 -    .multiply               (multiply_d),
  22.897 -`endif
  22.898 -`ifdef CFG_MC_DIVIDE_ENABLED
  22.899 -    .divide                 (divide_d),
  22.900 -    .modulus                (modulus_d),
  22.901 -`endif
  22.902 -    .branch                 (branch_d),
  22.903 -    .bi_unconditional       (bi_unconditional),
  22.904 -    .bi_conditional         (bi_conditional),
  22.905 -    .branch_reg             (branch_reg_d),
  22.906 -    .condition              (condition_d),
  22.907 -`ifdef CFG_DEBUG_ENABLED
  22.908 -    .break_opcode           (break_d),
  22.909 -`endif
  22.910 -    .scall                  (scall_d),
  22.911 -    .eret                   (eret_d),
  22.912 -`ifdef CFG_DEBUG_ENABLED
  22.913 -    .bret                   (bret_d),
  22.914 -`endif
  22.915 -`ifdef CFG_USER_ENABLED
  22.916 -    .user_opcode            (user_opcode_d),
  22.917 -`endif
  22.918 -    .csr_write_enable       (csr_write_enable_d)
  22.919 -    ); 
  22.920 -
  22.921 -// Load/store unit       
  22.922 -lm32_load_store_unit #(
  22.923 -    .associativity          (dcache_associativity),
  22.924 -    .sets                   (dcache_sets),
  22.925 -    .bytes_per_line         (dcache_bytes_per_line),
  22.926 -    .base_address           (dcache_base_address),
  22.927 -    .limit                  (dcache_limit)
  22.928 -  ) load_store_unit (
  22.929 -    // ----- Inputs -------
  22.930 -    .clk_i                  (clk_i),
  22.931 -    .rst_i                  (rst_i),
  22.932 -    // From pipeline
  22.933 -    .stall_a                (stall_a),
  22.934 -    .stall_x                (stall_x),
  22.935 -    .stall_m                (stall_m),
  22.936 -    .kill_m                 (kill_m),
  22.937 -    .exception_m            (exception_m),
  22.938 -    .store_operand_x        (store_operand_x),
  22.939 -    .load_store_address_x   (adder_result_x),
  22.940 -    .load_store_address_m   (operand_m),
  22.941 -    .load_store_address_w   (operand_w[1:0]),
  22.942 -    .load_x                 (load_x),
  22.943 -    .store_x                (store_x),
  22.944 -    .load_q_x               (load_q_x),
  22.945 -    .store_q_x              (store_q_x),
  22.946 -    .load_q_m               (load_q_m),
  22.947 -    .store_q_m              (store_q_m),
  22.948 -    .sign_extend_x          (sign_extend_x),
  22.949 -    .size_x                 (size_x),
  22.950 -`ifdef CFG_DCACHE_ENABLED
  22.951 -    .dflush                 (dflush_m),
  22.952 -`endif
  22.953 -`ifdef CFG_IROM_ENABLED
  22.954 -    .irom_data_m            (irom_data_m),
  22.955 -`endif
  22.956 -    // From Wishbone
  22.957 -    .d_dat_i                (D_DAT_I),
  22.958 -    .d_ack_i                (D_ACK_I),
  22.959 -    .d_err_i                (D_ERR_I),
  22.960 -    .d_rty_i                (D_RTY_I),
  22.961 -    // ----- Outputs -------
  22.962 -    // To pipeline
  22.963 -`ifdef CFG_DCACHE_ENABLED
  22.964 -    .dcache_refill_request  (dcache_refill_request),
  22.965 -    .dcache_restart_request (dcache_restart_request),
  22.966 -    .dcache_stall_request   (dcache_stall_request),
  22.967 -    .dcache_refilling       (dcache_refilling),
  22.968 -`endif    
  22.969 -`ifdef CFG_IROM_ENABLED
  22.970 -    .irom_store_data_m      (irom_store_data_m),
  22.971 -    .irom_address_xm        (irom_address_xm),
  22.972 -    .irom_we_xm             (irom_we_xm),
  22.973 -    .irom_stall_request_x   (irom_stall_request_x),
  22.974 -`endif
  22.975 -    .load_data_w            (load_data_w),
  22.976 -    .stall_wb_load          (stall_wb_load),
  22.977 -    // To Wishbone
  22.978 -    .d_dat_o                (D_DAT_O),
  22.979 -    .d_adr_o                (D_ADR_O),
  22.980 -    .d_cyc_o                (D_CYC_O),
  22.981 -    .d_sel_o                (D_SEL_O),
  22.982 -    .d_stb_o                (D_STB_O),
  22.983 -    .d_we_o                 (D_WE_O),
  22.984 -    .d_cti_o                (D_CTI_O),
  22.985 -    .d_lock_o               (D_LOCK_O),
  22.986 -    .d_bte_o                (D_BTE_O)
  22.987 -    );      
  22.988 -       
  22.989 -// Adder       
  22.990 -lm32_adder adder (
  22.991 -    // ----- Inputs -------
  22.992 -    .adder_op_x             (adder_op_x),
  22.993 -    .adder_op_x_n           (adder_op_x_n),
  22.994 -    .operand_0_x            (operand_0_x),
  22.995 -    .operand_1_x            (operand_1_x),
  22.996 -    // ----- Outputs -------
  22.997 -    .adder_result_x         (adder_result_x),
  22.998 -    .adder_carry_n_x        (adder_carry_n_x),
  22.999 -    .adder_overflow_x       (adder_overflow_x)
 22.1000 -    );
 22.1001 -
 22.1002 -// Logic operations
 22.1003 -lm32_logic_op logic_op (
 22.1004 -    // ----- Inputs -------
 22.1005 -    .logic_op_x             (logic_op_x),
 22.1006 -    .operand_0_x            (operand_0_x),
 22.1007 -
 22.1008 -    .operand_1_x            (operand_1_x),
 22.1009 -    // ----- Outputs -------
 22.1010 -    .logic_result_x         (logic_result_x)
 22.1011 -    );
 22.1012 -              
 22.1013 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.1014 -// Pipelined barrel-shifter
 22.1015 -lm32_shifter shifter (
 22.1016 -    // ----- Inputs -------
 22.1017 -    .clk_i                  (clk_i),
 22.1018 -    .rst_i                  (rst_i),
 22.1019 -    .stall_x                (stall_x),
 22.1020 -    .direction_x            (direction_x),
 22.1021 -    .sign_extend_x          (sign_extend_x),
 22.1022 -    .operand_0_x            (operand_0_x),
 22.1023 -    .operand_1_x            (operand_1_x),
 22.1024 -    // ----- Outputs -------
 22.1025 -    .shifter_result_m       (shifter_result_m)
 22.1026 -    );
 22.1027 -`endif
 22.1028 -
 22.1029 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.1030 -// Pipeline fixed-point multiplier
 22.1031 -lm32_multiplier multiplier (
 22.1032 -    // ----- Inputs -------
 22.1033 -    .clk_i                  (clk_i),
 22.1034 -    .rst_i                  (rst_i),
 22.1035 -    .stall_x                (stall_x),
 22.1036 -    .stall_m                (stall_m),
 22.1037 -    .operand_0              (d_result_0),
 22.1038 -    .operand_1              (d_result_1),
 22.1039 -    // ----- Outputs -------
 22.1040 -    .result                 (multiplier_result_w)    
 22.1041 -    );
 22.1042 -`endif
 22.1043 -
 22.1044 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1045 -// Multi-cycle arithmetic
 22.1046 -lm32_mc_arithmetic mc_arithmetic (
 22.1047 -    // ----- Inputs -------
 22.1048 -    .clk_i                  (clk_i),
 22.1049 -    .rst_i                  (rst_i),
 22.1050 -    .stall_d                (stall_d),
 22.1051 -    .kill_x                 (kill_x),
 22.1052 -`ifdef CFG_MC_DIVIDE_ENABLED                  
 22.1053 -    .divide_d               (divide_q_d),
 22.1054 -    .modulus_d              (modulus_q_d),
 22.1055 -`endif
 22.1056 -`ifdef CFG_MC_MULTIPLY_ENABLED        
 22.1057 -    .multiply_d             (multiply_q_d),
 22.1058 -`endif
 22.1059 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 22.1060 -    .shift_left_d           (shift_left_q_d),
 22.1061 -    .shift_right_d          (shift_right_q_d),
 22.1062 -    .sign_extend_d          (sign_extend_d),
 22.1063 -`endif    
 22.1064 -    .operand_0_d            (d_result_0),
 22.1065 -    .operand_1_d            (d_result_1),
 22.1066 -    // ----- Outputs -------
 22.1067 -    .result_x               (mc_result_x),
 22.1068 -`ifdef CFG_MC_DIVIDE_ENABLED                  
 22.1069 -    .divide_by_zero_x       (divide_by_zero_x),
 22.1070 -`endif
 22.1071 -    .stall_request_x        (mc_stall_request_x)
 22.1072 -    );
 22.1073 -`endif
 22.1074 -              
 22.1075 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1076 -// Interrupt unit
 22.1077 -lm32_interrupt interrupt_unit (
 22.1078 -    // ----- Inputs -------
 22.1079 -    .clk_i                  (clk_i),
 22.1080 -    .rst_i                  (rst_i),
 22.1081 -    // From external devices
 22.1082 -    .interrupt              (interrupt),
 22.1083 -    // From pipeline
 22.1084 -    .stall_x                (stall_x),
 22.1085 -`ifdef CFG_DEBUG_ENABLED
 22.1086 -    .non_debug_exception    (non_debug_exception_q_w),
 22.1087 -    .debug_exception        (debug_exception_q_w),
 22.1088 -`else
 22.1089 -    .exception              (exception_q_w),
 22.1090 -`endif
 22.1091 -    .eret_q_x               (eret_q_x),
 22.1092 -`ifdef CFG_DEBUG_ENABLED
 22.1093 -    .bret_q_x               (bret_q_x),
 22.1094 -`endif
 22.1095 -    .csr                    (csr_x),
 22.1096 -    .csr_write_data         (operand_1_x),
 22.1097 -    .csr_write_enable       (csr_write_enable_q_x),
 22.1098 -    // ----- Outputs -------
 22.1099 -    .interrupt_exception    (interrupt_exception),
 22.1100 -    // To pipeline
 22.1101 -    .csr_read_data          (interrupt_csr_read_data_x)
 22.1102 -    );
 22.1103 -`endif
 22.1104 -
 22.1105 -`ifdef CFG_JTAG_ENABLED
 22.1106 -// JTAG interface
 22.1107 -lm32_jtag jtag (
 22.1108 -    // ----- Inputs -------
 22.1109 -    .clk_i                  (clk_i),
 22.1110 -    .rst_i                  (rst_i),
 22.1111 -    // From JTAG
 22.1112 -    .jtag_clk               (jtag_clk),
 22.1113 -    .jtag_update            (jtag_update),
 22.1114 -    .jtag_reg_q             (jtag_reg_q),
 22.1115 -    .jtag_reg_addr_q        (jtag_reg_addr_q),
 22.1116 -    // From pipeline
 22.1117 -`ifdef CFG_JTAG_UART_ENABLED
 22.1118 -    .csr                    (csr_x),
 22.1119 -    .csr_write_data         (operand_1_x),
 22.1120 -    .csr_write_enable       (csr_write_enable_q_x),
 22.1121 -    .stall_x                (stall_x),
 22.1122 -`endif
 22.1123 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1124 -    .jtag_read_data         (jtag_read_data),
 22.1125 -    .jtag_access_complete   (jtag_access_complete),
 22.1126 -`endif
 22.1127 -`ifdef CFG_DEBUG_ENABLED
 22.1128 -    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
 22.1129 -`endif    
 22.1130 -    // ----- Outputs -------
 22.1131 -    // To pipeline
 22.1132 -`ifdef CFG_JTAG_UART_ENABLED
 22.1133 -    .jtx_csr_read_data      (jtx_csr_read_data),
 22.1134 -    .jrx_csr_read_data      (jrx_csr_read_data),
 22.1135 -`endif
 22.1136 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1137 -    .jtag_csr_write_enable  (jtag_csr_write_enable),
 22.1138 -    .jtag_csr_write_data    (jtag_csr_write_data),
 22.1139 -    .jtag_csr               (jtag_csr),
 22.1140 -    .jtag_read_enable       (jtag_read_enable),
 22.1141 -    .jtag_write_enable      (jtag_write_enable),
 22.1142 -    .jtag_write_data        (jtag_write_data),
 22.1143 -    .jtag_address           (jtag_address),
 22.1144 -`endif
 22.1145 -`ifdef CFG_DEBUG_ENABLED
 22.1146 -    .jtag_break             (jtag_break),
 22.1147 -    .jtag_reset             (reset_exception),
 22.1148 -`endif
 22.1149 -    // To JTAG 
 22.1150 -    .jtag_reg_d             (jtag_reg_d),
 22.1151 -    .jtag_reg_addr_d        (jtag_reg_addr_d)
 22.1152 -    );
 22.1153 -`endif
 22.1154 -
 22.1155 -`ifdef CFG_DEBUG_ENABLED
 22.1156 -// Debug unit
 22.1157 -lm32_debug #(
 22.1158 -    .breakpoints            (breakpoints),
 22.1159 -    .watchpoints            (watchpoints)
 22.1160 -  ) hw_debug (
 22.1161 -    // ----- Inputs -------
 22.1162 -    .clk_i                  (clk_i), 
 22.1163 -    .rst_i                  (rst_i),
 22.1164 -    .pc_x                   (pc_x),
 22.1165 -    .load_x                 (load_x),
 22.1166 -    .store_x                (store_x),
 22.1167 -    .load_store_address_x   (adder_result_x),
 22.1168 -    .csr_write_enable_x     (csr_write_enable_q_x),
 22.1169 -    .csr_write_data         (operand_1_x),
 22.1170 -    .csr_x                  (csr_x),
 22.1171 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1172 -    .jtag_csr_write_enable  (jtag_csr_write_enable),
 22.1173 -    .jtag_csr_write_data    (jtag_csr_write_data),
 22.1174 -    .jtag_csr               (jtag_csr),
 22.1175 -`endif
 22.1176 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1177 -    .eret_q_x               (eret_q_x),
 22.1178 -    .bret_q_x               (bret_q_x),
 22.1179 -    .stall_x                (stall_x),
 22.1180 -    .exception_x            (exception_x),
 22.1181 -    .q_x                    (q_x),
 22.1182 -`ifdef CFG_DCACHE_ENABLED
 22.1183 -    .dcache_refill_request  (dcache_refill_request),
 22.1184 -`endif
 22.1185 -`endif
 22.1186 -    // ----- Outputs -------
 22.1187 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1188 -    .dc_ss                  (dc_ss),
 22.1189 -`endif
 22.1190 -    .dc_re                  (dc_re),
 22.1191 -    .bp_match               (bp_match),
 22.1192 -    .wp_match               (wp_match)
 22.1193 -    );
 22.1194 -`endif
 22.1195 -
 22.1196 -// Register file
 22.1197 -
 22.1198 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.1199 -   /*----------------------------------------------------------------------
 22.1200 -    Register File is implemented using EBRs. There can be three accesses to
 22.1201 -    the register file in each cycle: two reads and one write. On-chip block
 22.1202 -    RAM has two read/write ports. To accomodate three accesses, two on-chip
 22.1203 -    block RAMs are used (each register file "write" is made to both block
 22.1204 -    RAMs).
 22.1205 -    
 22.1206 -    One limitation of the on-chip block RAMs is that one cannot perform a 
 22.1207 -    read and write to same location in a cycle (if this is done, then the
 22.1208 -    data read out is indeterminate).
 22.1209 -    ----------------------------------------------------------------------*/
 22.1210 -   wire [31:0] regfile_data_0, regfile_data_1;
 22.1211 -   reg [31:0]  w_result_d;
 22.1212 -   reg 	       regfile_raw_0, regfile_raw_0_nxt;
 22.1213 -   reg 	       regfile_raw_1, regfile_raw_1_nxt;
 22.1214 -   
 22.1215 -   /*----------------------------------------------------------------------
 22.1216 -    Check if read and write is being performed to same register in current 
 22.1217 -    cycle? This is done by comparing the read and write IDXs.
 22.1218 -    ----------------------------------------------------------------------*/
 22.1219 -   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
 22.1220 -     begin
 22.1221 -	if (reg_write_enable_q_w
 22.1222 -	    && (write_idx_w == instruction_f[25:21]))
 22.1223 -	  regfile_raw_0_nxt = 1'b1;
 22.1224 -	else
 22.1225 -	  regfile_raw_0_nxt = 1'b0;
 22.1226 -	
 22.1227 -	if (reg_write_enable_q_w
 22.1228 -	    && (write_idx_w == instruction_f[20:16]))
 22.1229 -	  regfile_raw_1_nxt = 1'b1;
 22.1230 -	else
 22.1231 -	  regfile_raw_1_nxt = 1'b0;
 22.1232 -     end
 22.1233 -   
 22.1234 -   /*----------------------------------------------------------------------
 22.1235 -    Select latched (delayed) write value or data from register file. If 
 22.1236 -    read in previous cycle was performed to register written to in same
 22.1237 -    cycle, then latched (delayed) write value is selected.
 22.1238 -    ----------------------------------------------------------------------*/
 22.1239 -   always @(regfile_raw_0 or w_result_d or regfile_data_0)
 22.1240 -     if (regfile_raw_0)
 22.1241 -       reg_data_live_0 = w_result_d;
 22.1242 -     else
 22.1243 -       reg_data_live_0 = regfile_data_0;
 22.1244 -   
 22.1245 -   /*----------------------------------------------------------------------
 22.1246 -    Select latched (delayed) write value or data from register file. If 
 22.1247 -    read in previous cycle was performed to register written to in same
 22.1248 -    cycle, then latched (delayed) write value is selected.
 22.1249 -    ----------------------------------------------------------------------*/
 22.1250 -   always @(regfile_raw_1 or w_result_d or regfile_data_1)
 22.1251 -     if (regfile_raw_1)
 22.1252 -       reg_data_live_1 = w_result_d;
 22.1253 -     else
 22.1254 -       reg_data_live_1 = regfile_data_1;
 22.1255 -   
 22.1256 -   /*----------------------------------------------------------------------
 22.1257 -    Latch value written to register file
 22.1258 -    ----------------------------------------------------------------------*/
 22.1259 -   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.1260 -     if (rst_i == `TRUE)
 22.1261 -       begin
 22.1262 -	  regfile_raw_0 <= 1'b0;
 22.1263 -	  regfile_raw_1 <= 1'b0;
 22.1264 -	  w_result_d <= 32'b0;
 22.1265 -       end
 22.1266 -     else
 22.1267 -       begin
 22.1268 -	  regfile_raw_0 <= regfile_raw_0_nxt;
 22.1269 -	  regfile_raw_1 <= regfile_raw_1_nxt;
 22.1270 -	  w_result_d <= w_result;
 22.1271 -       end
 22.1272 -   
 22.1273 -   /*----------------------------------------------------------------------
 22.1274 -    Register file instantiation as Pseudo-Dual Port EBRs.
 22.1275 -    ----------------------------------------------------------------------*/
 22.1276 -   // Modified by GSI: removed non-portable RAM instantiation
 22.1277 -   lm32_dp_ram
 22.1278 -     #(
 22.1279 -       // ----- Parameters -----
 22.1280 -       .addr_depth(1<<5),
 22.1281 -       .addr_width(5),
 22.1282 -       .data_width(32)
 22.1283 -       )
 22.1284 -   reg_0
 22.1285 -     (
 22.1286 -      // ----- Inputs -----
 22.1287 -      .clk_i	(clk_i),
 22.1288 -      .rst_i	(rst_i), 
 22.1289 -      .we_i	(reg_write_enable_q_w),
 22.1290 -      .wdata_i	(w_result),
 22.1291 -      .waddr_i	(write_idx_w),
 22.1292 -      .raddr_i	(instruction_f[25:21]),
 22.1293 -      // ----- Outputs -----
 22.1294 -      .rdata_o	(regfile_data_0)
 22.1295 -      );
 22.1296 -
 22.1297 -   lm32_dp_ram
 22.1298 -     #(
 22.1299 -       .addr_depth(1<<5),
 22.1300 -       .addr_width(5),
 22.1301 -       .data_width(32)
 22.1302 -       )
 22.1303 -   reg_1
 22.1304 -     (
 22.1305 -      // ----- Inputs -----
 22.1306 -      .clk_i	(clk_i),
 22.1307 -      .rst_i	(rst_i), 
 22.1308 -      .we_i	(reg_write_enable_q_w),
 22.1309 -      .wdata_i	(w_result),
 22.1310 -      .waddr_i	(write_idx_w),
 22.1311 -      .raddr_i	(instruction_f[20:16]),
 22.1312 -      // ----- Outputs -----
 22.1313 -      .rdata_o	(regfile_data_1)
 22.1314 -      );
 22.1315 -`endif
 22.1316 -
 22.1317 -`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
 22.1318 -   pmi_ram_dp
 22.1319 -     #(
 22.1320 -       // ----- Parameters -----
 22.1321 -       .pmi_wr_addr_depth(1<<5),
 22.1322 -       .pmi_wr_addr_width(5),
 22.1323 -       .pmi_wr_data_width(32),
 22.1324 -       .pmi_rd_addr_depth(1<<5),
 22.1325 -       .pmi_rd_addr_width(5),
 22.1326 -       .pmi_rd_data_width(32),
 22.1327 -       .pmi_regmode("noreg"),
 22.1328 -       .pmi_gsr("enable"),
 22.1329 -       .pmi_resetmode("sync"),
 22.1330 -       .pmi_init_file("none"),
 22.1331 -       .pmi_init_file_format("binary"),
 22.1332 -       .pmi_family(`LATTICE_FAMILY),
 22.1333 -       .module_type("pmi_ram_dp")
 22.1334 -       )
 22.1335 -   reg_0
 22.1336 -     (
 22.1337 -      // ----- Inputs -----
 22.1338 -      .Data(w_result),
 22.1339 -      .WrAddress(write_idx_w),
 22.1340 -      .RdAddress(read_idx_0_d),
 22.1341 -      .WrClock(clk_i),
 22.1342 -      .RdClock(clk_n_i),
 22.1343 -      .WrClockEn(`TRUE),
 22.1344 -      .RdClockEn(stall_f == `FALSE),
 22.1345 -      .WE(reg_write_enable_q_w),
 22.1346 -      .Reset(rst_i), 
 22.1347 -      // ----- Outputs -----
 22.1348 -      .Q(reg_data_0)
 22.1349 -      );
 22.1350 -   
 22.1351 -   pmi_ram_dp
 22.1352 -     #(
 22.1353 -       // ----- Parameters -----
 22.1354 -       .pmi_wr_addr_depth(1<<5),
 22.1355 -       .pmi_wr_addr_width(5),
 22.1356 -       .pmi_wr_data_width(32),
 22.1357 -       .pmi_rd_addr_depth(1<<5),
 22.1358 -       .pmi_rd_addr_width(5),
 22.1359 -       .pmi_rd_data_width(32),
 22.1360 -       .pmi_regmode("noreg"),
 22.1361 -       .pmi_gsr("enable"),
 22.1362 -       .pmi_resetmode("sync"),
 22.1363 -       .pmi_init_file("none"),
 22.1364 -       .pmi_init_file_format("binary"),
 22.1365 -       .pmi_family(`LATTICE_FAMILY),
 22.1366 -       .module_type("pmi_ram_dp")
 22.1367 -       )
 22.1368 -   reg_1
 22.1369 -     (
 22.1370 -      // ----- Inputs -----
 22.1371 -      .Data(w_result),
 22.1372 -      .WrAddress(write_idx_w),
 22.1373 -      .RdAddress(read_idx_1_d),
 22.1374 -      .WrClock(clk_i),
 22.1375 -      .RdClock(clk_n_i),
 22.1376 -      .WrClockEn(`TRUE),
 22.1377 -      .RdClockEn(stall_f == `FALSE),
 22.1378 -      .WE(reg_write_enable_q_w),
 22.1379 -      .Reset(rst_i), 
 22.1380 -      // ----- Outputs -----
 22.1381 -      .Q(reg_data_1)
 22.1382 -      );
 22.1383 -`endif
 22.1384 -
 22.1385 -
 22.1386 -/////////////////////////////////////////////////////
 22.1387 -// Combinational Logic
 22.1388 -/////////////////////////////////////////////////////
 22.1389 -
 22.1390 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.1391 -// Select between buffered and live data from register file
 22.1392 -assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
 22.1393 -assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
 22.1394 -`endif
 22.1395 -`ifdef LM32_EBR_REGISTER_FILE
 22.1396 -`else
 22.1397 -// Register file read ports
 22.1398 -assign reg_data_0 = registers[read_idx_0_d];
 22.1399 -assign reg_data_1 = registers[read_idx_1_d];
 22.1400 -`endif
 22.1401 -
 22.1402 -// Detect read-after-write hazzards
 22.1403 -assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
 22.1404 -assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
 22.1405 -assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
 22.1406 -assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
 22.1407 -assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
 22.1408 -assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
 22.1409 -
 22.1410 -// Interlock detection - Raise an interlock for RAW hazzards 
 22.1411 -always @(*)
 22.1412 -begin
 22.1413 -    if (   (   (x_bypass_enable_x == `FALSE)
 22.1414 -            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
 22.1415 -                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
 22.1416 -               )
 22.1417 -           )
 22.1418 -        || (   (m_bypass_enable_m == `FALSE)
 22.1419 -            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
 22.1420 -                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
 22.1421 -               )
 22.1422 -           )
 22.1423 -       )
 22.1424 -        interlock = `TRUE;
 22.1425 -    else
 22.1426 -        interlock = `FALSE;
 22.1427 -end
 22.1428 -
 22.1429 -// Bypass for reg port 0
 22.1430 -always @(*)
 22.1431 -begin
 22.1432 -    if (raw_x_0 == `TRUE)        
 22.1433 -        bypass_data_0 = x_result;
 22.1434 -    else if (raw_m_0 == `TRUE)
 22.1435 -        bypass_data_0 = m_result;
 22.1436 -    else if (raw_w_0 == `TRUE)
 22.1437 -        bypass_data_0 = w_result;
 22.1438 -    else
 22.1439 -        bypass_data_0 = reg_data_0;
 22.1440 -end
 22.1441 -
 22.1442 -// Bypass for reg port 1
 22.1443 -always @(*)
 22.1444 -begin
 22.1445 -    if (raw_x_1 == `TRUE)
 22.1446 -        bypass_data_1 = x_result;
 22.1447 -    else if (raw_m_1 == `TRUE)
 22.1448 -        bypass_data_1 = m_result;
 22.1449 -    else if (raw_w_1 == `TRUE)
 22.1450 -        bypass_data_1 = w_result;
 22.1451 -    else
 22.1452 -        bypass_data_1 = reg_data_1;
 22.1453 -end
 22.1454 -
 22.1455 -   /*----------------------------------------------------------------------
 22.1456 -    Branch prediction is performed in D stage of pipeline. Only PC-relative
 22.1457 -    branches are predicted: forward-pointing conditional branches are not-
 22.1458 -    taken, while backward-pointing conditional branches are taken. 
 22.1459 -    Unconditional branches are always predicted taken!
 22.1460 -    ----------------------------------------------------------------------*/
 22.1461 -   assign branch_predict_d = bi_unconditional | bi_conditional;
 22.1462 -   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
 22.1463 -   
 22.1464 -   // Compute branch target address: Branch PC PLUS Offset
 22.1465 -   assign branch_target_d = pc_d + branch_offset_d;
 22.1466 -
 22.1467 -   // Compute fetch address. Address of instruction sequentially after the
 22.1468 -   // branch if branch is not taken. Target address of branch is branch is
 22.1469 -   // taken
 22.1470 -   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
 22.1471 -
 22.1472 -// D stage result selection
 22.1473 -always @(*)
 22.1474 -begin
 22.1475 -    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
 22.1476 -    case (d_result_sel_1_d)
 22.1477 -    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
 22.1478 -    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
 22.1479 -    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
 22.1480 -    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
 22.1481 -    endcase
 22.1482 -end
 22.1483 -
 22.1484 -`ifdef CFG_USER_ENABLED    
 22.1485 -// Operands for user-defined instructions
 22.1486 -assign user_operand_0 = operand_0_x;
 22.1487 -assign user_operand_1 = operand_1_x;
 22.1488 -`endif
 22.1489 -
 22.1490 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1491 -// Sign-extension
 22.1492 -assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
 22.1493 -assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
 22.1494 -assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
 22.1495 -`endif
 22.1496 -
 22.1497 -`ifdef LM32_NO_BARREL_SHIFT
 22.1498 -// Only single bit shift operations are supported when barrel-shifter isn't implemented
 22.1499 -assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
 22.1500 -`endif
 22.1501 -
 22.1502 -// Condition evaluation
 22.1503 -assign cmp_zero = operand_0_x == operand_1_x;
 22.1504 -assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
 22.1505 -assign cmp_overflow = adder_overflow_x;
 22.1506 -assign cmp_carry_n = adder_carry_n_x;
 22.1507 -always @(*)
 22.1508 -begin
 22.1509 -    case (condition_x)
 22.1510 -    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
 22.1511 -    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
 22.1512 -    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
 22.1513 -    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
 22.1514 -    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
 22.1515 -    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
 22.1516 -    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
 22.1517 -    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
 22.1518 -    default:              condition_met_x = 1'bx;
 22.1519 -    endcase 
 22.1520 -end
 22.1521 -
 22.1522 -// X stage result selection
 22.1523 -always @(*)
 22.1524 -begin
 22.1525 -    x_result =   x_result_sel_add_x ? adder_result_x 
 22.1526 -               : x_result_sel_csr_x ? csr_read_data_x
 22.1527 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1528 -               : x_result_sel_sext_x ? sext_result_x
 22.1529 -`endif
 22.1530 -`ifdef CFG_USER_ENABLED
 22.1531 -               : x_result_sel_user_x ? user_result
 22.1532 -`endif
 22.1533 -`ifdef LM32_NO_BARREL_SHIFT
 22.1534 -               : x_result_sel_shift_x ? shifter_result_x
 22.1535 -`endif
 22.1536 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1537 -               : x_result_sel_mc_arith_x ? mc_result_x
 22.1538 -`endif
 22.1539 -               : logic_result_x;
 22.1540 -end
 22.1541 -
 22.1542 -// M stage result selection
 22.1543 -always @(*)
 22.1544 -begin
 22.1545 -    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
 22.1546 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.1547 -               : m_result_sel_shift_m ? shifter_result_m
 22.1548 -`endif
 22.1549 -               : operand_m; 
 22.1550 -end
 22.1551 -
 22.1552 -// W stage result selection
 22.1553 -always @(*)
 22.1554 -begin
 22.1555 -    w_result =    w_result_sel_load_w ? load_data_w
 22.1556 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.1557 -                : w_result_sel_mul_w ? multiplier_result_w
 22.1558 -`endif
 22.1559 -                : operand_w;
 22.1560 -end
 22.1561 -
 22.1562 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1563 -// Indicate when a branch should be taken in X stage
 22.1564 -assign branch_taken_x =      (stall_x == `FALSE)
 22.1565 -                          && (   (branch_x == `TRUE)
 22.1566 -                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
 22.1567 -                              && (valid_x == `TRUE)
 22.1568 -                              && (branch_predict_x == `FALSE)
 22.1569 -                             ); 
 22.1570 -`endif
 22.1571 -
 22.1572 -// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
 22.1573 -assign branch_taken_m =      (stall_m == `FALSE) 
 22.1574 -                          && (   (   (branch_m == `TRUE) 
 22.1575 -                                  && (valid_m == `TRUE)
 22.1576 -                                  && (   (   (condition_met_m == `TRUE)
 22.1577 -					  && (branch_predict_taken_m == `FALSE)
 22.1578 -					 )
 22.1579 -				      || (   (condition_met_m == `FALSE)
 22.1580 -					  && (branch_predict_m == `TRUE)
 22.1581 -					  && (branch_predict_taken_m == `TRUE)
 22.1582 -					 )
 22.1583 -				     )
 22.1584 -                                 ) 
 22.1585 -                              || (exception_m == `TRUE)
 22.1586 -                             );
 22.1587 -
 22.1588 -// Indicate when a branch in M stage is mispredicted as being taken
 22.1589 -assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
 22.1590 -                                   && (branch_predict_m == `TRUE)
 22.1591 -	   			   && (branch_predict_taken_m == `TRUE);
 22.1592 -   
 22.1593 -// Indicate when a branch in M stage will cause flush in X stage
 22.1594 -assign branch_flushX_m =    (stall_m == `FALSE)
 22.1595 -                         && (   (   (branch_m == `TRUE) 
 22.1596 -                                 && (valid_m == `TRUE)
 22.1597 -			         && (   (condition_met_m == `TRUE)
 22.1598 -				     || (   (condition_met_m == `FALSE)
 22.1599 -					 && (branch_predict_m == `TRUE)
 22.1600 -					 && (branch_predict_taken_m == `TRUE)
 22.1601 -					)
 22.1602 -				    )
 22.1603 -			        )
 22.1604 -			     || (exception_m == `TRUE)
 22.1605 -			    );
 22.1606 -
 22.1607 -// Generate signal that will kill instructions in each pipeline stage when necessary
 22.1608 -assign kill_f =    (   (valid_d == `TRUE)
 22.1609 -                    && (branch_predict_taken_d == `TRUE)
 22.1610 -		   )
 22.1611 -                || (branch_taken_m == `TRUE) 
 22.1612 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1613 -                || (branch_taken_x == `TRUE)
 22.1614 -`endif
 22.1615 -`ifdef CFG_ICACHE_ENABLED
 22.1616 -                || (icache_refill_request == `TRUE) 
 22.1617 -`endif
 22.1618 -`ifdef CFG_DCACHE_ENABLED                
 22.1619 -                || (dcache_refill_request == `TRUE)
 22.1620 -`endif
 22.1621 -                ;
 22.1622 -assign kill_d =    (branch_taken_m == `TRUE) 
 22.1623 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.1624 -                || (branch_taken_x == `TRUE)
 22.1625 -`endif
 22.1626 -`ifdef CFG_ICACHE_ENABLED
 22.1627 -                || (icache_refill_request == `TRUE)     
 22.1628 -`endif                
 22.1629 -`ifdef CFG_DCACHE_ENABLED                
 22.1630 -                || (dcache_refill_request == `TRUE)
 22.1631 -`endif
 22.1632 -                ;
 22.1633 -assign kill_x =    (branch_flushX_m == `TRUE) 
 22.1634 -`ifdef CFG_DCACHE_ENABLED                
 22.1635 -                || (dcache_refill_request == `TRUE)
 22.1636 -`endif
 22.1637 -                ;
 22.1638 -assign kill_m =    `FALSE
 22.1639 -`ifdef CFG_DCACHE_ENABLED                
 22.1640 -                || (dcache_refill_request == `TRUE)
 22.1641 -`endif
 22.1642 -                ;                
 22.1643 -assign kill_w =    `FALSE
 22.1644 -`ifdef CFG_DCACHE_ENABLED                
 22.1645 -                || (dcache_refill_request == `TRUE)
 22.1646 -`endif                
 22.1647 -                ;
 22.1648 -
 22.1649 -// Exceptions
 22.1650 -
 22.1651 -`ifdef CFG_DEBUG_ENABLED
 22.1652 -assign breakpoint_exception =    (   (   (break_x == `TRUE)
 22.1653 -				      || (bp_match == `TRUE)
 22.1654 -				     )
 22.1655 -				  && (valid_x == `TRUE)
 22.1656 -				 )
 22.1657 -`ifdef CFG_JTAG_ENABLED
 22.1658 -                              || (jtag_break == `TRUE)
 22.1659 -`endif
 22.1660 -                              ;
 22.1661 -`endif
 22.1662 -
 22.1663 -`ifdef CFG_DEBUG_ENABLED
 22.1664 -assign watchpoint_exception = wp_match == `TRUE;
 22.1665 -`endif
 22.1666 -
 22.1667 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1668 -assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
 22.1669 -                                          && (valid_x == `TRUE)
 22.1670 -                                         );
 22.1671 -assign data_bus_error_exception = data_bus_error_seen == `TRUE;
 22.1672 -`endif
 22.1673 -
 22.1674 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1675 -assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
 22.1676 -`endif
 22.1677 -
 22.1678 -assign system_call_exception = (   (scall_x == `TRUE)
 22.1679 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1680 -                                && (valid_x == `TRUE)
 22.1681 -`endif
 22.1682 -			       );
 22.1683 -
 22.1684 -`ifdef CFG_DEBUG_ENABLED
 22.1685 -assign debug_exception_x =  (breakpoint_exception == `TRUE)
 22.1686 -                         || (watchpoint_exception == `TRUE)
 22.1687 -                         ;
 22.1688 -
 22.1689 -assign non_debug_exception_x = (system_call_exception == `TRUE)
 22.1690 -`ifdef CFG_JTAG_ENABLED
 22.1691 -                            || (reset_exception == `TRUE)
 22.1692 -`endif
 22.1693 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1694 -                            || (instruction_bus_error_exception == `TRUE)
 22.1695 -                            || (data_bus_error_exception == `TRUE)
 22.1696 -`endif
 22.1697 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1698 -                            || (divide_by_zero_exception == `TRUE)
 22.1699 -`endif
 22.1700 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1701 -                            || (   (interrupt_exception == `TRUE)
 22.1702 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1703 -                                && (dc_ss == `FALSE)
 22.1704 -`endif                            
 22.1705 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1706 - 				&& (store_q_m == `FALSE)
 22.1707 -				&& (D_CYC_O == `FALSE)
 22.1708 -`endif
 22.1709 -                               )
 22.1710 -`endif
 22.1711 -                            ;
 22.1712 -
 22.1713 -assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
 22.1714 -`else
 22.1715 -assign exception_x =           (system_call_exception == `TRUE)
 22.1716 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1717 -                            || (instruction_bus_error_exception == `TRUE)
 22.1718 -                            || (data_bus_error_exception == `TRUE)
 22.1719 -`endif
 22.1720 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1721 -                            || (divide_by_zero_exception == `TRUE)
 22.1722 -`endif
 22.1723 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1724 -                            || (   (interrupt_exception == `TRUE)
 22.1725 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1726 -                                && (dc_ss == `FALSE)
 22.1727 -`endif                            
 22.1728 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1729 - 				&& (store_q_m == `FALSE)
 22.1730 -				&& (D_CYC_O == `FALSE)
 22.1731 -`endif
 22.1732 -                               )
 22.1733 -`endif
 22.1734 -                            ;
 22.1735 -`endif
 22.1736 -
 22.1737 -// Exception ID
 22.1738 -always @(*)
 22.1739 -begin
 22.1740 -`ifdef CFG_DEBUG_ENABLED
 22.1741 -`ifdef CFG_JTAG_ENABLED
 22.1742 -    if (reset_exception == `TRUE)
 22.1743 -        eid_x = `LM32_EID_RESET;
 22.1744 -    else
 22.1745 -`endif     
 22.1746 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1747 -         if (data_bus_error_exception == `TRUE)
 22.1748 -        eid_x = `LM32_EID_DATA_BUS_ERROR;
 22.1749 -    else
 22.1750 -`endif
 22.1751 -         if (breakpoint_exception == `TRUE)
 22.1752 -        eid_x = `LM32_EID_BREAKPOINT;
 22.1753 -    else
 22.1754 -`endif
 22.1755 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1756 -         if (data_bus_error_exception == `TRUE)
 22.1757 -        eid_x = `LM32_EID_DATA_BUS_ERROR;
 22.1758 -    else
 22.1759 -         if (instruction_bus_error_exception == `TRUE)
 22.1760 -        eid_x = `LM32_EID_INST_BUS_ERROR;
 22.1761 -    else
 22.1762 -`endif
 22.1763 -`ifdef CFG_DEBUG_ENABLED
 22.1764 -         if (watchpoint_exception == `TRUE)
 22.1765 -        eid_x = `LM32_EID_WATCHPOINT;
 22.1766 -    else 
 22.1767 -`endif
 22.1768 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1769 -         if (divide_by_zero_exception == `TRUE)
 22.1770 -        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
 22.1771 -    else
 22.1772 -`endif
 22.1773 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1774 -         if (   (interrupt_exception == `TRUE)
 22.1775 -`ifdef LM32_SINGLE_STEP_ENABLED
 22.1776 -             && (dc_ss == `FALSE)
 22.1777 -`endif                            
 22.1778 -            )
 22.1779 -        eid_x = `LM32_EID_INTERRUPT;
 22.1780 -    else
 22.1781 -`endif
 22.1782 -        eid_x = `LM32_EID_SCALL;
 22.1783 -end
 22.1784 -
 22.1785 -// Stall generation
 22.1786 -
 22.1787 -assign stall_a = (stall_f == `TRUE);
 22.1788 -                
 22.1789 -assign stall_f = (stall_d == `TRUE);
 22.1790 -                
 22.1791 -assign stall_d =   (stall_x == `TRUE) 
 22.1792 -                || (   (interlock == `TRUE)
 22.1793 -                    && (kill_d == `FALSE)
 22.1794 -                   ) 
 22.1795 -		|| (   (   (eret_d == `TRUE)
 22.1796 -			|| (scall_d == `TRUE)
 22.1797 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.1798 -			|| (bus_error_d == `TRUE)
 22.1799 -`endif
 22.1800 -		       )
 22.1801 -		    && (   (load_q_x == `TRUE)
 22.1802 -			|| (load_q_m == `TRUE)
 22.1803 -			|| (store_q_x == `TRUE)
 22.1804 -			|| (store_q_m == `TRUE)
 22.1805 -			|| (D_CYC_O == `TRUE)
 22.1806 -		       )
 22.1807 -                    && (kill_d == `FALSE)
 22.1808 -		   )
 22.1809 -`ifdef CFG_DEBUG_ENABLED
 22.1810 -		|| (   (   (break_d == `TRUE)
 22.1811 -			|| (bret_d == `TRUE)
 22.1812 -		       )
 22.1813 -		    && (   (load_q_x == `TRUE)
 22.1814 -			|| (store_q_x == `TRUE)
 22.1815 -			|| (load_q_m == `TRUE)
 22.1816 -			|| (store_q_m == `TRUE)
 22.1817 -			|| (D_CYC_O == `TRUE)
 22.1818 -		       )
 22.1819 -                    && (kill_d == `FALSE)
 22.1820 -		   )
 22.1821 -`endif                   
 22.1822 -                || (   (csr_write_enable_d == `TRUE)
 22.1823 -                    && (load_q_x == `TRUE)
 22.1824 -                   )                      
 22.1825 -                ;
 22.1826 -                
 22.1827 -assign stall_x =    (stall_m == `TRUE)
 22.1828 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1829 -                 || (   (mc_stall_request_x == `TRUE)
 22.1830 -                     && (kill_x == `FALSE)
 22.1831 -                    ) 
 22.1832 -`endif
 22.1833 -`ifdef CFG_IROM_ENABLED
 22.1834 -                 // Stall load/store instruction in D stage if there is an ongoing store
 22.1835 -                 // operation to instruction ROM in M stage
 22.1836 -                 || (   (irom_stall_request_x == `TRUE)
 22.1837 -		     && (   (load_d == `TRUE)
 22.1838 -			 || (store_d == `TRUE)
 22.1839 -			)
 22.1840 -		    )
 22.1841 -`endif
 22.1842 -                 ;
 22.1843 -
 22.1844 -assign stall_m =    (stall_wb_load == `TRUE)
 22.1845 -`ifdef CFG_SIZE_OVER_SPEED
 22.1846 -                 || (D_CYC_O == `TRUE)
 22.1847 -`else
 22.1848 -                 || (   (D_CYC_O == `TRUE)
 22.1849 -                     && (   (store_m == `TRUE)
 22.1850 -		         /*
 22.1851 -			  Bug: Following loop does not allow interrupts to be services since
 22.1852 -			  either D_CYC_O or store_m is always high during entire duration of
 22.1853 -			  loop.
 22.1854 -		          L1:	addi	r1, r1, 1
 22.1855 -			  	sw	(r2,0), r1
 22.1856 -			  	bi	L1
 22.1857 -			  
 22.1858 -			  Introduce a single-cycle stall when a wishbone cycle is in progress
 22.1859 -			  and a new store instruction is in Execute stage and a interrupt
 22.1860 -			  exception has occured. This stall will ensure that D_CYC_O and 
 22.1861 -			  store_m will both be low for one cycle.
 22.1862 -			  */
 22.1863 -`ifdef CFG_INTERRUPTS_ENABLED
 22.1864 -		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
 22.1865 -`endif
 22.1866 -                         || (load_m == `TRUE)
 22.1867 -                         || (load_x == `TRUE)
 22.1868 -                        ) 
 22.1869 -                    ) 
 22.1870 -`endif                 
 22.1871 -`ifdef CFG_DCACHE_ENABLED
 22.1872 -                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
 22.1873 -`endif                                    
 22.1874 -`ifdef CFG_ICACHE_ENABLED
 22.1875 -                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
 22.1876 -                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
 22.1877 -`else
 22.1878 -`ifdef CFG_IWB_ENABLED
 22.1879 -                 || (I_CYC_O == `TRUE)            
 22.1880 -`endif
 22.1881 -`endif                               
 22.1882 -`ifdef CFG_USER_ENABLED
 22.1883 -                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
 22.1884 -                     && (user_complete == `FALSE)
 22.1885 -                    )
 22.1886 -`endif
 22.1887 -                 ;      
 22.1888 -
 22.1889 -// Qualify state changing control signals
 22.1890 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.1891 -assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
 22.1892 -`endif
 22.1893 -`ifdef CFG_MC_BARREL_SHIFT_ENABLED
 22.1894 -assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
 22.1895 -assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
 22.1896 -`endif
 22.1897 -`ifdef CFG_MC_MULTIPLY_ENABLED
 22.1898 -assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
 22.1899 -`endif
 22.1900 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1901 -assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
 22.1902 -assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
 22.1903 -`endif
 22.1904 -assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
 22.1905 -assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
 22.1906 -assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
 22.1907 -`ifdef CFG_DEBUG_ENABLED
 22.1908 -assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
 22.1909 -`endif
 22.1910 -assign load_q_x = (load_x == `TRUE) 
 22.1911 -               && (q_x == `TRUE)
 22.1912 -`ifdef CFG_DEBUG_ENABLED
 22.1913 -               && (bp_match == `FALSE)
 22.1914 -`endif
 22.1915 -                  ;
 22.1916 -assign store_q_x = (store_x == `TRUE) 
 22.1917 -               && (q_x == `TRUE)
 22.1918 -`ifdef CFG_DEBUG_ENABLED
 22.1919 -               && (bp_match == `FALSE)
 22.1920 -`endif
 22.1921 -                  ;
 22.1922 -`ifdef CFG_USER_ENABLED
 22.1923 -assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
 22.1924 -`endif                              
 22.1925 -assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
 22.1926 -assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
 22.1927 -assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
 22.1928 -`ifdef CFG_DEBUG_ENABLED
 22.1929 -assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
 22.1930 -assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
 22.1931 -`else
 22.1932 -assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
 22.1933 -`endif
 22.1934 -// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
 22.1935 -assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
 22.1936 -assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
 22.1937 -assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
 22.1938 -// The enable that actually does write the registers needs to be qualified with kill
 22.1939 -assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
 22.1940 -
 22.1941 -// Configuration (CFG) CSR
 22.1942 -assign cfg = {
 22.1943 -              `LM32_REVISION,
 22.1944 -              watchpoints[3:0],
 22.1945 -              breakpoints[3:0],
 22.1946 -              interrupts[5:0],
 22.1947 -`ifdef CFG_JTAG_UART_ENABLED
 22.1948 -              `TRUE,
 22.1949 -`else
 22.1950 -              `FALSE,
 22.1951 -`endif
 22.1952 -`ifdef CFG_ROM_DEBUG_ENABLED
 22.1953 -              `TRUE,
 22.1954 -`else
 22.1955 -              `FALSE,
 22.1956 -`endif
 22.1957 -`ifdef CFG_HW_DEBUG_ENABLED
 22.1958 -              `TRUE,
 22.1959 -`else
 22.1960 -              `FALSE,
 22.1961 -`endif
 22.1962 -`ifdef CFG_DEBUG_ENABLED
 22.1963 -              `TRUE,
 22.1964 -`else
 22.1965 -              `FALSE,
 22.1966 -`endif
 22.1967 -`ifdef CFG_ICACHE_ENABLED
 22.1968 -              `TRUE,
 22.1969 -`else
 22.1970 -              `FALSE,
 22.1971 -`endif
 22.1972 -`ifdef CFG_DCACHE_ENABLED
 22.1973 -              `TRUE,
 22.1974 -`else
 22.1975 -              `FALSE,
 22.1976 -`endif
 22.1977 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.1978 -              `TRUE,
 22.1979 -`else
 22.1980 -              `FALSE,
 22.1981 -`endif
 22.1982 -`ifdef CFG_USER_ENABLED
 22.1983 -              `TRUE,
 22.1984 -`else
 22.1985 -              `FALSE,
 22.1986 -`endif
 22.1987 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.1988 -              `TRUE,
 22.1989 -`else
 22.1990 -              `FALSE,
 22.1991 -`endif
 22.1992 -`ifdef LM32_BARREL_SHIFT_ENABLED
 22.1993 -              `TRUE,
 22.1994 -`else
 22.1995 -              `FALSE,
 22.1996 -`endif
 22.1997 -`ifdef CFG_MC_DIVIDE_ENABLED
 22.1998 -              `TRUE,
 22.1999 -`else
 22.2000 -              `FALSE,
 22.2001 -`endif
 22.2002 -`ifdef LM32_MULTIPLY_ENABLED 
 22.2003 -              `TRUE
 22.2004 -`else
 22.2005 -              `FALSE
 22.2006 -`endif
 22.2007 -              };
 22.2008 -
 22.2009 -assign cfg2 = {
 22.2010 -		     30'b0,
 22.2011 -`ifdef CFG_IROM_ENABLED
 22.2012 -		     `TRUE,
 22.2013 -`else
 22.2014 -		     `FALSE,
 22.2015 -`endif
 22.2016 -`ifdef CFG_DRAM_ENABLED
 22.2017 -		     `TRUE
 22.2018 -`else
 22.2019 -		     `FALSE
 22.2020 -`endif
 22.2021 -		     };
 22.2022 -   
 22.2023 -// Cache flush
 22.2024 -`ifdef CFG_ICACHE_ENABLED
 22.2025 -assign iflush = (   (csr_write_enable_d == `TRUE) 
 22.2026 -                 && (csr_d == `LM32_CSR_ICC)
 22.2027 -                 && (stall_d == `FALSE)
 22.2028 -                 && (kill_d == `FALSE)
 22.2029 -                 && (valid_d == `TRUE))
 22.2030 -// Added by GSI: needed to flush cache after loading firmware per JTAG
 22.2031 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2032 -             ||
 22.2033 -                (   (jtag_csr_write_enable == `TRUE)
 22.2034 -		 && (jtag_csr == `LM32_CSR_ICC))
 22.2035 -`endif
 22.2036 -		 ;
 22.2037 -`endif 
 22.2038 -`ifdef CFG_DCACHE_ENABLED
 22.2039 -assign dflush_x = (   (csr_write_enable_q_x == `TRUE) 
 22.2040 -                   && (csr_x == `LM32_CSR_DCC))
 22.2041 -// Added by GSI: needed to flush cache after loading firmware per JTAG
 22.2042 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2043 -               ||
 22.2044 -                  (   (jtag_csr_write_enable == `TRUE)
 22.2045 -		   && (jtag_csr == `LM32_CSR_DCC))
 22.2046 -`endif
 22.2047 -		   ;
 22.2048 -`endif 
 22.2049 -
 22.2050 -// Extract CSR index
 22.2051 -assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
 22.2052 -
 22.2053 -// CSR reads
 22.2054 -always @(*)
 22.2055 -begin
 22.2056 -    case (csr_x)
 22.2057 -`ifdef CFG_INTERRUPTS_ENABLED
 22.2058 -    `LM32_CSR_IE,
 22.2059 -    `LM32_CSR_IM,
 22.2060 -    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
 22.2061 -`endif
 22.2062 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.2063 -    `LM32_CSR_CC:   csr_read_data_x = cc;
 22.2064 -`endif
 22.2065 -    `LM32_CSR_CFG:  csr_read_data_x = cfg;
 22.2066 -    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
 22.2067 -`ifdef CFG_DEBUG_ENABLED
 22.2068 -    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
 22.2069 -`endif
 22.2070 -`ifdef CFG_JTAG_UART_ENABLED
 22.2071 -    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
 22.2072 -    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
 22.2073 -`endif
 22.2074 -    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
 22.2075 -      
 22.2076 -    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
 22.2077 -    endcase
 22.2078 -end
 22.2079 -
 22.2080 -/////////////////////////////////////////////////////
 22.2081 -// Sequential Logic
 22.2082 -/////////////////////////////////////////////////////
 22.2083 -
 22.2084 -// Exception Base Address (EBA) CSR
 22.2085 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2086 -begin
 22.2087 -    if (rst_i == `TRUE)
 22.2088 -        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
 22.2089 -    else
 22.2090 -    begin
 22.2091 -        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
 22.2092 -            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 22.2093 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2094 -        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
 22.2095 -            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 22.2096 -`endif
 22.2097 -    end
 22.2098 -end
 22.2099 -
 22.2100 -`ifdef CFG_DEBUG_ENABLED
 22.2101 -// Debug Exception Base Address (DEBA) CSR
 22.2102 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2103 -begin
 22.2104 -    if (rst_i == `TRUE)
 22.2105 -        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
 22.2106 -    else
 22.2107 -    begin
 22.2108 -        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
 22.2109 -            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
 22.2110 -`ifdef CFG_HW_DEBUG_ENABLED
 22.2111 -        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
 22.2112 -            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
 22.2113 -`endif
 22.2114 -    end
 22.2115 -end
 22.2116 -`endif
 22.2117 -
 22.2118 -// Cycle Counter (CC) CSR
 22.2119 -`ifdef CFG_CYCLE_COUNTER_ENABLED
 22.2120 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2121 -begin
 22.2122 -    if (rst_i == `TRUE)
 22.2123 -        cc <= {`LM32_WORD_WIDTH{1'b0}};
 22.2124 -    else
 22.2125 -        cc <= cc + 1'b1;
 22.2126 -end
 22.2127 -`endif
 22.2128 -
 22.2129 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2130 -// Watch for data bus errors
 22.2131 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2132 -begin
 22.2133 -    if (rst_i == `TRUE)
 22.2134 -        data_bus_error_seen <= `FALSE;
 22.2135 -    else
 22.2136 -    begin
 22.2137 -        // Set flag when bus error is detected
 22.2138 -        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
 22.2139 -            data_bus_error_seen <= `TRUE;
 22.2140 -        // Clear flag when exception is taken
 22.2141 -        if ((exception_m == `TRUE) && (kill_m == `FALSE))
 22.2142 -            data_bus_error_seen <= `FALSE;
 22.2143 -    end
 22.2144 -end
 22.2145 -`endif
 22.2146 - 
 22.2147 -// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
 22.2148 -
 22.2149 -`ifdef CFG_ICACHE_ENABLED
 22.2150 -`ifdef CFG_DCACHE_ENABLED
 22.2151 -always @(*)
 22.2152 -begin
 22.2153 -    if (   (icache_refill_request == `TRUE) 
 22.2154 -        || (dcache_refill_request == `TRUE)
 22.2155 -       )
 22.2156 -        valid_a = `FALSE;
 22.2157 -    else if (   (icache_restart_request == `TRUE) 
 22.2158 -             || (dcache_restart_request == `TRUE) 
 22.2159 -            ) 
 22.2160 -        valid_a = `TRUE;
 22.2161 -    else 
 22.2162 -        valid_a = !icache_refilling && !dcache_refilling;
 22.2163 -end 
 22.2164 -`else
 22.2165 -always @(*)
 22.2166 -begin
 22.2167 -    if (icache_refill_request == `TRUE) 
 22.2168 -        valid_a = `FALSE;
 22.2169 -    else if (icache_restart_request == `TRUE) 
 22.2170 -        valid_a = `TRUE;
 22.2171 -    else 
 22.2172 -        valid_a = !icache_refilling;
 22.2173 -end 
 22.2174 -`endif
 22.2175 -`else
 22.2176 -`ifdef CFG_DCACHE_ENABLED
 22.2177 -always @(*)
 22.2178 -begin
 22.2179 -    if (dcache_refill_request == `TRUE) 
 22.2180 -        valid_a = `FALSE;
 22.2181 -    else if (dcache_restart_request == `TRUE) 
 22.2182 -        valid_a = `TRUE;
 22.2183 -    else 
 22.2184 -        valid_a = !dcache_refilling;
 22.2185 -end 
 22.2186 -`endif
 22.2187 -`endif
 22.2188 -
 22.2189 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2190 -begin
 22.2191 -    if (rst_i == `TRUE)
 22.2192 -    begin
 22.2193 -        valid_f <= `FALSE;
 22.2194 -        valid_d <= `FALSE;
 22.2195 -        valid_x <= `FALSE;
 22.2196 -        valid_m <= `FALSE;
 22.2197 -        valid_w <= `FALSE;
 22.2198 -    end
 22.2199 -    else
 22.2200 -    begin    
 22.2201 -        if ((kill_f == `TRUE) || (stall_a == `FALSE))
 22.2202 -`ifdef LM32_CACHE_ENABLED
 22.2203 -            valid_f <= valid_a;    
 22.2204 -`else
 22.2205 -            valid_f <= `TRUE;
 22.2206 -`endif            
 22.2207 -        else if (stall_f == `FALSE)
 22.2208 -            valid_f <= `FALSE;            
 22.2209 -
 22.2210 -        if (kill_d == `TRUE)
 22.2211 -            valid_d <= `FALSE;
 22.2212 -        else if (stall_f == `FALSE)
 22.2213 -            valid_d <= valid_f & !kill_f;
 22.2214 -        else if (stall_d == `FALSE)
 22.2215 -            valid_d <= `FALSE;
 22.2216 -       
 22.2217 -        if (stall_d == `FALSE)
 22.2218 -            valid_x <= valid_d & !kill_d;
 22.2219 -        else if (kill_x == `TRUE)
 22.2220 -            valid_x <= `FALSE;
 22.2221 -        else if (stall_x == `FALSE)
 22.2222 -            valid_x <= `FALSE;
 22.2223 -
 22.2224 -        if (kill_m == `TRUE)
 22.2225 -            valid_m <= `FALSE;
 22.2226 -        else if (stall_x == `FALSE)
 22.2227 -            valid_m <= valid_x & !kill_x;
 22.2228 -        else if (stall_m == `FALSE)
 22.2229 -            valid_m <= `FALSE;
 22.2230 -
 22.2231 -        if (stall_m == `FALSE)
 22.2232 -            valid_w <= valid_m & !kill_m;
 22.2233 -        else 
 22.2234 -            valid_w <= `FALSE;        
 22.2235 -    end
 22.2236 -end
 22.2237 -
 22.2238 -// Microcode pipeline registers
 22.2239 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2240 -begin
 22.2241 -    if (rst_i == `TRUE)
 22.2242 -    begin
 22.2243 -`ifdef CFG_USER_ENABLED
 22.2244 -        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
 22.2245 -`endif        
 22.2246 -        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2247 -        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2248 -        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
 22.2249 -        branch_target_x <= {`LM32_PC_WIDTH{1'b0}};        
 22.2250 -        x_result_sel_csr_x <= `FALSE;
 22.2251 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.2252 -        x_result_sel_mc_arith_x <= `FALSE;
 22.2253 -`endif
 22.2254 -`ifdef LM32_NO_BARREL_SHIFT    
 22.2255 -        x_result_sel_shift_x <= `FALSE;
 22.2256 -`endif
 22.2257 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.2258 -        x_result_sel_sext_x <= `FALSE;
 22.2259 -`endif  
 22.2260 -	x_result_sel_logic_x <= `FALSE;
 22.2261 -`ifdef CFG_USER_ENABLED
 22.2262 -        x_result_sel_user_x <= `FALSE;
 22.2263 -`endif
 22.2264 -        x_result_sel_add_x <= `FALSE;
 22.2265 -        m_result_sel_compare_x <= `FALSE;
 22.2266 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2267 -        m_result_sel_shift_x <= `FALSE;
 22.2268 -`endif    
 22.2269 -        w_result_sel_load_x <= `FALSE;
 22.2270 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2271 -        w_result_sel_mul_x <= `FALSE;
 22.2272 -`endif
 22.2273 -        x_bypass_enable_x <= `FALSE;
 22.2274 -        m_bypass_enable_x <= `FALSE;
 22.2275 -        write_enable_x <= `FALSE;
 22.2276 -        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
 22.2277 -        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
 22.2278 -        load_x <= `FALSE;
 22.2279 -        store_x <= `FALSE;
 22.2280 -        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
 22.2281 -        sign_extend_x <= `FALSE;
 22.2282 -        adder_op_x <= `FALSE;
 22.2283 -        adder_op_x_n <= `FALSE;
 22.2284 -        logic_op_x <= 4'h0;
 22.2285 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2286 -        direction_x <= `FALSE;
 22.2287 -`endif
 22.2288 -`ifdef CFG_ROTATE_ENABLED
 22.2289 -        rotate_x <= `FALSE;
 22.2290 -
 22.2291 -`endif
 22.2292 -        branch_x <= `FALSE;
 22.2293 -        branch_predict_x <= `FALSE;
 22.2294 -        branch_predict_taken_x <= `FALSE;
 22.2295 -        condition_x <= `LM32_CONDITION_U1;
 22.2296 -`ifdef CFG_DEBUG_ENABLED
 22.2297 -        break_x <= `FALSE;
 22.2298 -`endif
 22.2299 -        scall_x <= `FALSE;
 22.2300 -        eret_x <= `FALSE;
 22.2301 -`ifdef CFG_DEBUG_ENABLED
 22.2302 -        bret_x <= `FALSE;
 22.2303 -`endif
 22.2304 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2305 -        bus_error_x <= `FALSE;
 22.2306 -        data_bus_error_exception_m <= `FALSE;
 22.2307 -`endif
 22.2308 -        csr_write_enable_x <= `FALSE;
 22.2309 -        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
 22.2310 -        branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
 22.2311 -        m_result_sel_compare_m <= `FALSE;
 22.2312 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2313 -        m_result_sel_shift_m <= `FALSE;
 22.2314 -`endif    
 22.2315 -        w_result_sel_load_m <= `FALSE;
 22.2316 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2317 -        w_result_sel_mul_m <= `FALSE;
 22.2318 -`endif
 22.2319 -        m_bypass_enable_m <= `FALSE;
 22.2320 -        branch_m <= `FALSE;
 22.2321 -        branch_predict_m <= `FALSE;
 22.2322 -	branch_predict_taken_m <= `FALSE;
 22.2323 -        exception_m <= `FALSE;
 22.2324 -        load_m <= `FALSE;
 22.2325 -        store_m <= `FALSE;
 22.2326 -        write_enable_m <= `FALSE;            
 22.2327 -        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
 22.2328 -        condition_met_m <= `FALSE;
 22.2329 -`ifdef CFG_DCACHE_ENABLED
 22.2330 -        dflush_m <= `FALSE;
 22.2331 -`endif
 22.2332 -`ifdef CFG_DEBUG_ENABLED
 22.2333 -        debug_exception_m <= `FALSE;
 22.2334 -        non_debug_exception_m <= `FALSE;        
 22.2335 -`endif
 22.2336 -        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
 22.2337 -        w_result_sel_load_w <= `FALSE;
 22.2338 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2339 -        w_result_sel_mul_w <= `FALSE;
 22.2340 -`endif
 22.2341 -        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
 22.2342 -        write_enable_w <= `FALSE;
 22.2343 -`ifdef CFG_DEBUG_ENABLED
 22.2344 -        debug_exception_w <= `FALSE;
 22.2345 -        non_debug_exception_w <= `FALSE;        
 22.2346 -`else
 22.2347 -        exception_w <= `FALSE;
 22.2348 -`endif
 22.2349 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2350 -        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
 22.2351 -`endif
 22.2352 -    end
 22.2353 -    else
 22.2354 -    begin
 22.2355 -        // D/X stage registers
 22.2356 -       
 22.2357 -        if (stall_x == `FALSE)
 22.2358 -        begin
 22.2359 -`ifdef CFG_USER_ENABLED
 22.2360 -            user_opcode <= user_opcode_d;       
 22.2361 -`endif        
 22.2362 -            operand_0_x <= d_result_0;
 22.2363 -            operand_1_x <= d_result_1;
 22.2364 -            store_operand_x <= bypass_data_1;
 22.2365 -            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
 22.2366 -            x_result_sel_csr_x <= x_result_sel_csr_d;
 22.2367 -`ifdef LM32_MC_ARITHMETIC_ENABLED
 22.2368 -            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
 22.2369 -`endif
 22.2370 -`ifdef LM32_NO_BARREL_SHIFT    
 22.2371 -            x_result_sel_shift_x <= x_result_sel_shift_d;
 22.2372 -`endif
 22.2373 -`ifdef CFG_SIGN_EXTEND_ENABLED
 22.2374 -            x_result_sel_sext_x <= x_result_sel_sext_d;
 22.2375 -`endif    
 22.2376 -	    x_result_sel_logic_x <= x_result_sel_logic_d;
 22.2377 -`ifdef CFG_USER_ENABLED
 22.2378 -            x_result_sel_user_x <= x_result_sel_user_d;
 22.2379 -`endif
 22.2380 -            x_result_sel_add_x <= x_result_sel_add_d;
 22.2381 -            m_result_sel_compare_x <= m_result_sel_compare_d;
 22.2382 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2383 -            m_result_sel_shift_x <= m_result_sel_shift_d;
 22.2384 -`endif    
 22.2385 -            w_result_sel_load_x <= w_result_sel_load_d;
 22.2386 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2387 -            w_result_sel_mul_x <= w_result_sel_mul_d;
 22.2388 -`endif
 22.2389 -            x_bypass_enable_x <= x_bypass_enable_d;
 22.2390 -            m_bypass_enable_x <= m_bypass_enable_d;
 22.2391 -            load_x <= load_d;
 22.2392 -            store_x <= store_d;
 22.2393 -            branch_x <= branch_d;
 22.2394 -	    branch_predict_x <= branch_predict_d;
 22.2395 -	    branch_predict_taken_x <= branch_predict_taken_d;
 22.2396 -	    write_idx_x <= write_idx_d;
 22.2397 -            csr_x <= csr_d;
 22.2398 -            size_x <= size_d;
 22.2399 -            sign_extend_x <= sign_extend_d;
 22.2400 -            adder_op_x <= adder_op_d;
 22.2401 -            adder_op_x_n <= ~adder_op_d;
 22.2402 -            logic_op_x <= logic_op_d;
 22.2403 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2404 -            direction_x <= direction_d;
 22.2405 -`endif
 22.2406 -`ifdef CFG_ROTATE_ENABLED
 22.2407 -            rotate_x <= rotate_d;
 22.2408 -`endif
 22.2409 -            condition_x <= condition_d;
 22.2410 -            csr_write_enable_x <= csr_write_enable_d;
 22.2411 -`ifdef CFG_DEBUG_ENABLED
 22.2412 -            break_x <= break_d;
 22.2413 -`endif
 22.2414 -            scall_x <= scall_d;
 22.2415 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2416 -            bus_error_x <= bus_error_d;
 22.2417 -`endif
 22.2418 -            eret_x <= eret_d;
 22.2419 -`ifdef CFG_DEBUG_ENABLED
 22.2420 -            bret_x <= bret_d; 
 22.2421 -`endif
 22.2422 -            write_enable_x <= write_enable_d;
 22.2423 -        end
 22.2424 -        
 22.2425 -        // X/M stage registers
 22.2426 -
 22.2427 -        if (stall_m == `FALSE)
 22.2428 -        begin
 22.2429 -            operand_m <= x_result;
 22.2430 -            m_result_sel_compare_m <= m_result_sel_compare_x;
 22.2431 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2432 -            m_result_sel_shift_m <= m_result_sel_shift_x;
 22.2433 -`endif    
 22.2434 -            if (exception_x == `TRUE)
 22.2435 -            begin
 22.2436 -                w_result_sel_load_m <= `FALSE;
 22.2437 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2438 -                w_result_sel_mul_m <= `FALSE;
 22.2439 -`endif
 22.2440 -            end
 22.2441 -            else
 22.2442 -            begin
 22.2443 -                w_result_sel_load_m <= w_result_sel_load_x;
 22.2444 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2445 -                w_result_sel_mul_m <= w_result_sel_mul_x;
 22.2446 -`endif
 22.2447 -            end
 22.2448 -            m_bypass_enable_m <= m_bypass_enable_x;
 22.2449 -`ifdef CFG_PL_BARREL_SHIFT_ENABLED
 22.2450 -`endif
 22.2451 -            load_m <= load_x;
 22.2452 -            store_m <= store_x;
 22.2453 -`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
 22.2454 -            branch_m <= branch_x && !branch_taken_x;
 22.2455 -`else
 22.2456 -            branch_m <= branch_x;
 22.2457 -	    branch_predict_m <= branch_predict_x;
 22.2458 -	    branch_predict_taken_m <= branch_predict_taken_x;
 22.2459 -`endif
 22.2460 -`ifdef CFG_DEBUG_ENABLED
 22.2461 -	   // Data bus errors are generated by the wishbone and are
 22.2462 -	   // made known to the processor only in next cycle (as a
 22.2463 -	   // non-debug exception). A break instruction can be seen
 22.2464 -	   // in same cycle (causing a debug exception). Handle non
 22.2465 -	   // -debug exception first!
 22.2466 -            if (non_debug_exception_x == `TRUE) 
 22.2467 -                write_idx_m <= `LM32_EA_REG;
 22.2468 -            else if (debug_exception_x == `TRUE)
 22.2469 -                write_idx_m <= `LM32_BA_REG;
 22.2470 -            else 
 22.2471 -                write_idx_m <= write_idx_x;
 22.2472 -`else
 22.2473 -            if (exception_x == `TRUE)
 22.2474 -                write_idx_m <= `LM32_EA_REG;
 22.2475 -            else 
 22.2476 -                write_idx_m <= write_idx_x;
 22.2477 -`endif
 22.2478 -            condition_met_m <= condition_met_x;
 22.2479 -`ifdef CFG_DEBUG_ENABLED
 22.2480 -	   if (exception_x == `TRUE)
 22.2481 -	     if ((dc_re == `TRUE)
 22.2482 -		 || ((debug_exception_x == `TRUE) 
 22.2483 -		     && (non_debug_exception_x == `FALSE)))
 22.2484 -	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
 22.2485 -	     else
 22.2486 -	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
 22.2487 -	   else
 22.2488 -	     branch_target_m <= branch_target_x;
 22.2489 -`else
 22.2490 -            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
 22.2491 -`endif
 22.2492 -`ifdef CFG_TRACE_ENABLED
 22.2493 -            eid_m <= eid_x;
 22.2494 -`endif
 22.2495 -`ifdef CFG_DCACHE_ENABLED
 22.2496 -            dflush_m <= dflush_x;
 22.2497 -`endif
 22.2498 -            eret_m <= eret_q_x;
 22.2499 -`ifdef CFG_DEBUG_ENABLED
 22.2500 -            bret_m <= bret_q_x; 
 22.2501 -`endif
 22.2502 -            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
 22.2503 -`ifdef CFG_DEBUG_ENABLED
 22.2504 -            debug_exception_m <= debug_exception_x;
 22.2505 -            non_debug_exception_m <= non_debug_exception_x;        
 22.2506 -`endif
 22.2507 -        end
 22.2508 -        
 22.2509 -        // State changing regs
 22.2510 -        if (stall_m == `FALSE)
 22.2511 -        begin
 22.2512 -            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
 22.2513 -                exception_m <= `TRUE;
 22.2514 -            else 
 22.2515 -                exception_m <= `FALSE;
 22.2516 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2517 -	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
 22.2518 -`ifdef CFG_DEBUG_ENABLED
 22.2519 -					 && (reset_exception == `FALSE)
 22.2520 -`endif
 22.2521 -					 ;
 22.2522 -`endif
 22.2523 -	end
 22.2524 -                
 22.2525 -        // M/W stage registers
 22.2526 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2527 -        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
 22.2528 -`else
 22.2529 -        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
 22.2530 -`endif
 22.2531 -        w_result_sel_load_w <= w_result_sel_load_m;
 22.2532 -`ifdef CFG_PL_MULTIPLY_ENABLED
 22.2533 -        w_result_sel_mul_w <= w_result_sel_mul_m;
 22.2534 -`endif
 22.2535 -        write_idx_w <= write_idx_m;
 22.2536 -`ifdef CFG_TRACE_ENABLED
 22.2537 -        eid_w <= eid_m;
 22.2538 -        eret_w <= eret_m;
 22.2539 -`ifdef CFG_DEBUG_ENABLED
 22.2540 -        bret_w <= bret_m; 
 22.2541 -`endif
 22.2542 -`endif
 22.2543 -        write_enable_w <= write_enable_m;
 22.2544 -`ifdef CFG_DEBUG_ENABLED
 22.2545 -        debug_exception_w <= debug_exception_m;
 22.2546 -        non_debug_exception_w <= non_debug_exception_m;
 22.2547 -`else
 22.2548 -        exception_w <= exception_m;
 22.2549 -`endif
 22.2550 -`ifdef CFG_BUS_ERRORS_ENABLED
 22.2551 -        if (   (stall_m == `FALSE)
 22.2552 -            && (   (load_q_m == `TRUE) 
 22.2553 -                || (store_q_m == `TRUE)
 22.2554 -               )
 22.2555 -	   )
 22.2556 -          memop_pc_w <= pc_m;
 22.2557 -`endif
 22.2558 -    end
 22.2559 -end
 22.2560 -
 22.2561 -`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
 22.2562 -// Buffer data read from register file, in case a stall occurs, and watch for
 22.2563 -// any writes to the modified registers
 22.2564 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2565 -begin
 22.2566 -    if (rst_i == `TRUE)
 22.2567 -    begin
 22.2568 -        use_buf <= `FALSE;
 22.2569 -        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
 22.2570 -        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
 22.2571 -    end
 22.2572 -    else
 22.2573 -    begin
 22.2574 -        if (stall_d == `FALSE)
 22.2575 -            use_buf <= `FALSE;
 22.2576 -        else if (use_buf == `FALSE)
 22.2577 -        begin        
 22.2578 -            reg_data_buf_0 <= reg_data_live_0;
 22.2579 -            reg_data_buf_1 <= reg_data_live_1;
 22.2580 -            use_buf <= `TRUE;
 22.2581 -        end        
 22.2582 -        if (reg_write_enable_q_w == `TRUE)
 22.2583 -        begin
 22.2584 -            if (write_idx_w == read_idx_0_d)
 22.2585 -                reg_data_buf_0 <= w_result;
 22.2586 -            if (write_idx_w == read_idx_1_d)
 22.2587 -                reg_data_buf_1 <= w_result;
 22.2588 -        end
 22.2589 -    end
 22.2590 -end
 22.2591 -`endif
 22.2592 -
 22.2593 -`ifdef LM32_EBR_REGISTER_FILE
 22.2594 -`else
 22.2595 -// Register file write port
 22.2596 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2597 -begin
 22.2598 -    if (rst_i == `TRUE) begin
 22.2599 -        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2600 -        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2601 -        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2602 -        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2603 -        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2604 -        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2605 -        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2606 -        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2607 -        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2608 -        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2609 -        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2610 -        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2611 -        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2612 -        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2613 -        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2614 -        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2615 -        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2616 -        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2617 -        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2618 -        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2619 -        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2620 -        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2621 -        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2622 -        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2623 -        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2624 -        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2625 -        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2626 -        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2627 -        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2628 -        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2629 -        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
 22.2630 -        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
 22.2631 -        end
 22.2632 -    else begin
 22.2633 -        if (reg_write_enable_q_w == `TRUE)
 22.2634 -          registers[write_idx_w] <= w_result;
 22.2635 -        end
 22.2636 -end
 22.2637 -`endif
 22.2638 -
 22.2639 -`ifdef CFG_TRACE_ENABLED
 22.2640 -// PC tracing logic
 22.2641 -always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 22.2642 -begin
 22.2643 -    if (rst_i == `TRUE)
 22.2644 -    begin
 22.2645 -        trace_pc_valid <= `FALSE;
 22.2646 -        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
 22.2647 -        trace_exception <= `FALSE;
 22.2648 -        trace_eid <= `LM32_EID_RESET;
 22.2649 -        trace_eret <= `FALSE;
 22.2650 -`ifdef CFG_DEBUG_ENABLED
 22.2651 -        trace_bret <= `FALSE;
 22.2652 -`endif
 22.2653 -        pc_c <= `CFG_EBA_RESET/4;
 22.2654 -    end
 22.2655 -    else
 22.2656 -    begin
 22.2657 -        trace_pc_valid <= `FALSE;
 22.2658 -        // Has an exception occured
 22.2659 -`ifdef CFG_DEBUG_ENABLED
 22.2660 -        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
 22.2661 -`else
 22.2662 -        if (exception_q_w == `TRUE)
 22.2663 -`endif
 22.2664 -        begin        
 22.2665 -            trace_exception <= `TRUE;
 22.2666 -            trace_pc_valid <= `TRUE;
 22.2667 -            trace_pc <= pc_w;
 22.2668 -            trace_eid <= eid_w;
 22.2669 -        end
 22.2670 -        else
 22.2671 -            trace_exception <= `FALSE;
 22.2672 -        
 22.2673 -        if ((valid_w == `TRUE) && (!kill_w))
 22.2674 -        begin
 22.2675 -            // An instruction is commiting. Determine if it is non-sequential
 22.2676 -            if (pc_c + 1'b1 != pc_w)
 22.2677 -            begin
 22.2678 -                // Non-sequential instruction
 22.2679 -                trace_pc_valid <= `TRUE;
 22.2680 -                trace_pc <= pc_w;
 22.2681 -            end
 22.2682 -            // Record PC so we can determine if next instruction is sequential or not
 22.2683 -            pc_c <= pc_w;
 22.2684 -            // Indicate if it was an eret/bret instruction
 22.2685 -            trace_eret <= eret_w;
 22.2686 -`ifdef CFG_DEBUG_ENABLED
 22.2687 -            trace_bret <= bret_w;
 22.2688 -`endif
 22.2689 -        end
 22.2690 -        else
 22.2691 -        begin
 22.2692 -            trace_eret <= `FALSE;
 22.2693 -`ifdef CFG_DEBUG_ENABLED
 22.2694 -            trace_bret <= `FALSE;
 22.2695 -`endif
 22.2696 -        end
 22.2697 -    end
 22.2698 -end
 22.2699 -`endif
 22.2700 -      
 22.2701 -/////////////////////////////////////////////////////
 22.2702 -// Behavioural Logic
 22.2703 -/////////////////////////////////////////////////////
 22.2704 -
 22.2705 -// synthesis translate_off            
 22.2706 -
 22.2707 -// Reset register 0. Only needed for simulation. 
 22.2708 -initial
 22.2709 -begin
 22.2710 -`ifdef LM32_EBR_REGISTER_FILE
 22.2711 -    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2712 -    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2713 -`else
 22.2714 -    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
 22.2715 -`endif
 22.2716 -end
 22.2717 -
 22.2718 -// synthesis translate_on
 22.2719 -        
 22.2720 -endmodule