add lm32 source

Sun, 04 Apr 2010 20:40:03 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 20:40:03 +0100
changeset 0
cd0b58aa6f83
child 1
ae6035050124
child 8
07be9df9fee8

add lm32 source

JTAGB.v file | annotate | diff | revisions
er1.v file | annotate | diff | revisions
jtag_cores.v file | annotate | diff | revisions
jtag_lm32.v file | annotate | diff | revisions
lm32_adder.v file | annotate | diff | revisions
lm32_addsub.v file | annotate | diff | revisions
lm32_cpu.v file | annotate | diff | revisions
lm32_dcache.v file | annotate | diff | revisions
lm32_debug.v file | annotate | diff | revisions
lm32_decoder.v file | annotate | diff | revisions
lm32_functions.v file | annotate | diff | revisions
lm32_icache.v file | annotate | diff | revisions
lm32_include.v file | annotate | diff | revisions
lm32_instruction_unit.v file | annotate | diff | revisions
lm32_interrupt.v file | annotate | diff | revisions
lm32_jtag.v file | annotate | diff | revisions
lm32_load_store_unit.v file | annotate | diff | revisions
lm32_logic_op.v file | annotate | diff | revisions
lm32_mc_arithmetic.v file | annotate | diff | revisions
lm32_monitor.v file | annotate | diff | revisions
lm32_monitor_ram.v file | annotate | diff | revisions
lm32_multiplier.v file | annotate | diff | revisions
lm32_ram.v file | annotate | diff | revisions
lm32_shifter.v file | annotate | diff | revisions
lm32_top.v file | annotate | diff | revisions
lm32_trace.v file | annotate | diff | revisions
spiprog.v file | annotate | diff | revisions
typea.v file | annotate | diff | revisions
typeb.v file | annotate | diff | revisions
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/JTAGB.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,42 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : JTAGB.v
    1.22 +// Title            : JTAGB Black Box
    1.23 +// Dependencies     : None
    1.24 +// Version          : 6.0.14
    1.25 +//                  : Initial Release
    1.26 +// Version          : 7.0SP2, 3.0
    1.27 +//                  : No Change
    1.28 +// Version          : 3.1
    1.29 +//                  : No Change
    1.30 +// =============================================================================
    1.31 +module JTAGB (
    1.32 +         output JTCK,
    1.33 +         output JRTI1,
    1.34 +         output JRTI2,
    1.35 +         output JTDI,
    1.36 +         output JSHIFT,
    1.37 +         output JUPDATE,
    1.38 +         output JRSTN,
    1.39 +         output JCE1,
    1.40 +         output JCE2,
    1.41 +         input JTDO1,
    1.42 +         input JTDO2
    1.43 +      ) /*synthesis syn_black_box */; 
    1.44 +      
    1.45 +endmodule
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/er1.v	Sun Apr 04 20:40:03 2010 +0100
     2.3 @@ -0,0 +1,230 @@
     2.4 +// =============================================================================
     2.5 +//                           COPYRIGHT NOTICE
     2.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     2.7 +// ALL RIGHTS RESERVED
     2.8 +// This confidential and proprietary software may be used only as authorised by
     2.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    2.10 +// The entire notice above must be reproduced on all authorized copies and
    2.11 +// copies may only be made to the extent permitted by a licensing agreement from
    2.12 +// Lattice Semiconductor Corporation.
    2.13 +//
    2.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    2.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    2.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    2.17 +// U.S.A                                   email: techsupport@latticesemi.com
    2.18 +// =============================================================================/
    2.19 +//                         FILE DETAILS
    2.20 +// Project          : LatticeMico32
    2.21 +// File             : er1.v
    2.22 +// Description:
    2.23 +//    This module is where the ER1 register implemented. ER1 and ER2 registers
    2.24 +//    can be registers implemented in Lattice FPGAs using normal FPGA's
    2.25 +//    programmable logic resources.  Once they are implemented, they can be
    2.26 +//    accessed as if they are JTAG data registers through the FPGA JTAG port.
    2.27 +//    In order to accessing these registers, JTAG instructions ER1(0x32) or
    2.28 +//    ER2(0x38) needs to be written to the JTAG IR register for enabling the
    2.29 +//    ER1/ER2 accessing logic.  The ER1 or ER2 accessing logic can only be
    2.30 +//    enabled one at a time.  Once they are enabled, they will be disabled if
    2.31 +//    another JTAG instruction is written into the JTAG instruction register.
    2.32 +//    The registers allow dynamically accessing the FPGA internal information
    2.33 +//    even when the device is running.  Therefore, they are very useful for some
    2.34 +//    of the IP cores.  In order to let ER1/ER2 registers shared by multiple IP
    2.35 +//    cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
    2.36 +//    The ER1/ER2 structure allows only one ER1 register but more than one ER2
    2.37 +//    registers in an FPGA device.  Please refer to the related document for
    2.38 +//    this patterned ER1/ER2 structure.
    2.39 +// Dependencies     : None
    2.40 +// Version          : 6.0.14
    2.41 +//                  : Initial Version
    2.42 +// Version          : 7.0SP2, 3.0
    2.43 +//                  : No Change
    2.44 +// Version          : 3.1
    2.45 +//                  : No Change
    2.46 +// =============================================================================
    2.47 +module ER1 (input  JTCK,
    2.48 +	    input  JTDI,
    2.49 +	    output JTDO1,
    2.50 +	    output reg JTDO2,
    2.51 +	    input  JSHIFT,
    2.52 +	    input  JUPDATE,
    2.53 +	    input  JRSTN,
    2.54 +	    input  JCE1,
    2.55 +	    input [14:0] ER2_TDO,
    2.56 +	    output reg [14:0] IP_ENABLE,
    2.57 +	    input  ISPTRACY_ER2_TDO,
    2.58 +	    output ISPTRACY_ENABLE,
    2.59 +	    output CONTROL_DATAN)/* synthesis syn_hier = hard */;
    2.60 +
    2.61 +
    2.62 +   wire 	   controlDataNBit;
    2.63 +   wire 	   ispTracyEnableBit;
    2.64 +   wire [3:0] 	   encodedIpEnableBits;
    2.65 +   wire [9:0] 	   er1TdiBit;
    2.66 +   wire 	   captureDrER1;
    2.67 +   
    2.68 +
    2.69 +   assign 	   JTDO1 = er1TdiBit[0];
    2.70 +   
    2.71 +   TYPEB BIT0 (.CLK(JTCK),
    2.72 +	       .RESET_N(JRSTN),
    2.73 +	       .CLKEN(JCE1),
    2.74 +	       .TDI(er1TdiBit[1]),
    2.75 +	       .TDO(er1TdiBit[0]),
    2.76 +	       .DATA_IN(1'b0),
    2.77 +	       .CAPTURE_DR(captureDrER1));
    2.78 +
    2.79 +   TYPEB BIT1 (.CLK(JTCK),
    2.80 +	       .RESET_N(JRSTN),
    2.81 +	       .CLKEN(JCE1),
    2.82 +	       .TDI(er1TdiBit[2]),
    2.83 +	       .TDO(er1TdiBit[1]),
    2.84 +	       .DATA_IN(1'b0),
    2.85 +	       .CAPTURE_DR(captureDrER1));
    2.86 +
    2.87 +   TYPEB BIT2 (.CLK(JTCK),
    2.88 +	       .RESET_N(JRSTN),
    2.89 +	       .CLKEN(JCE1),
    2.90 +	       .TDI(er1TdiBit[3]),
    2.91 +	       .TDO(er1TdiBit[2]),
    2.92 +	       .DATA_IN(1'b1),
    2.93 +	       .CAPTURE_DR(captureDrER1));
    2.94 +   
    2.95 +   TYPEA BIT3 (.CLK(JTCK),
    2.96 +	       .RESET_N(JRSTN),
    2.97 +	       .CLKEN(JCE1),
    2.98 +	       .TDI(er1TdiBit[4]),
    2.99 +	       .TDO(er1TdiBit[3]),
   2.100 +	       .DATA_OUT(controlDataNBit),
   2.101 +	       .DATA_IN(controlDataNBit),
   2.102 +	       .CAPTURE_DR(captureDrER1),
   2.103 +	       .UPDATE_DR(JUPDATE));
   2.104 +
   2.105 +   assign CONTROL_DATAN = controlDataNBit;
   2.106 +
   2.107 +   TYPEA BIT4 (.CLK(JTCK),
   2.108 +	       .RESET_N(JRSTN),
   2.109 +	       .CLKEN(JCE1),
   2.110 +	       .TDI(er1TdiBit[5]),
   2.111 +	       .TDO(er1TdiBit[4]),
   2.112 +	       .DATA_OUT(ispTracyEnableBit),
   2.113 +	       .DATA_IN(ispTracyEnableBit),
   2.114 +	       .CAPTURE_DR(captureDrER1),
   2.115 +	       .UPDATE_DR(JUPDATE)
   2.116 +	       );
   2.117 +
   2.118 +   assign ISPTRACY_ENABLE = ispTracyEnableBit;
   2.119 +
   2.120 +   TYPEA BIT5 (.CLK(JTCK),
   2.121 +	       .RESET_N(JRSTN),
   2.122 +	       .CLKEN(JCE1),
   2.123 +	       .TDI(er1TdiBit[6]),
   2.124 +	       .TDO(er1TdiBit[5]),
   2.125 +	       .DATA_OUT(encodedIpEnableBits[0]),
   2.126 +	       .DATA_IN(encodedIpEnableBits[0]),
   2.127 +	       .CAPTURE_DR(captureDrER1),
   2.128 +	       .UPDATE_DR(JUPDATE));
   2.129 +   
   2.130 +   TYPEA BIT6 (.CLK(JTCK),
   2.131 +	       .RESET_N(JRSTN),
   2.132 +	       .CLKEN(JCE1),
   2.133 +	       .TDI(er1TdiBit[7]),
   2.134 +	       .TDO(er1TdiBit[6]),
   2.135 +	       .DATA_OUT(encodedIpEnableBits[1]),
   2.136 +	       .DATA_IN(encodedIpEnableBits[1]),
   2.137 +	       .CAPTURE_DR(captureDrER1),
   2.138 +	       .UPDATE_DR(JUPDATE));
   2.139 +   
   2.140 +   TYPEA BIT7 (.CLK(JTCK),
   2.141 +	       .RESET_N(JRSTN),
   2.142 +	       .CLKEN(JCE1),
   2.143 +	       .TDI(er1TdiBit[8]),
   2.144 +	       .TDO(er1TdiBit[7]),
   2.145 +	       .DATA_OUT(encodedIpEnableBits[2]),
   2.146 +	       .DATA_IN(encodedIpEnableBits[2]),
   2.147 +	       .CAPTURE_DR(captureDrER1),
   2.148 +	       .UPDATE_DR(JUPDATE));
   2.149 +   
   2.150 +   TYPEA BIT8 (.CLK(JTCK),
   2.151 +	       .RESET_N(JRSTN),
   2.152 +	       .CLKEN(JCE1),
   2.153 +	       .TDI(er1TdiBit[9]),
   2.154 +	       .TDO(er1TdiBit[8]),
   2.155 +	       .DATA_OUT(encodedIpEnableBits[3]),
   2.156 +	       .DATA_IN(encodedIpEnableBits[3]),
   2.157 +	       .CAPTURE_DR(captureDrER1),
   2.158 +	       .UPDATE_DR(JUPDATE)
   2.159 +	       );
   2.160 +   
   2.161 +   assign er1TdiBit[9] = JTDI;
   2.162 +   assign captureDrER1  = !JSHIFT & JCE1;
   2.163 +   
   2.164 +   always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
   2.165 +   begin
   2.166 +    case (encodedIpEnableBits)
   2.167 +      4'h0: begin 
   2.168 +      		IP_ENABLE <= 15'b000000000000000;
   2.169 +      		JTDO2 <= ISPTRACY_ER2_TDO;
   2.170 +      	    end
   2.171 +      4'h1: begin
   2.172 +      		IP_ENABLE <= 15'b000000000000001;
   2.173 +      		JTDO2 <= ER2_TDO[0];
   2.174 +      	    end	
   2.175 +      4'h2: begin
   2.176 +      		IP_ENABLE <= 15'b000000000000010;
   2.177 +      		JTDO2 <= ER2_TDO[1];
   2.178 +      	    end
   2.179 +      4'h3: begin
   2.180 +      		IP_ENABLE <= 15'b000000000000100;
   2.181 +      		JTDO2 <= ER2_TDO[2];
   2.182 +      	    end
   2.183 +      4'h4: begin
   2.184 +      		IP_ENABLE <= 15'b000000000001000;
   2.185 +      		JTDO2 <= ER2_TDO[3];
   2.186 +      	    end
   2.187 +      4'h5: begin
   2.188 +      		IP_ENABLE <= 15'b000000000010000;
   2.189 +      		JTDO2 <= ER2_TDO[4];
   2.190 +      	    end
   2.191 +      4'h6: begin
   2.192 +      		IP_ENABLE <= 15'b000000000100000;
   2.193 +      		JTDO2 <= ER2_TDO[5];
   2.194 +      	    end
   2.195 +      4'h7: begin
   2.196 +      		IP_ENABLE <= 15'b000000001000000;
   2.197 +      		JTDO2 <= ER2_TDO[6];
   2.198 +      	    end
   2.199 +      4'h8: begin
   2.200 +      		IP_ENABLE <= 15'b000000010000000;
   2.201 +      		JTDO2 <= ER2_TDO[7];
   2.202 +      	    end
   2.203 +      4'h9: begin
   2.204 +      		IP_ENABLE <= 15'b000000100000000;
   2.205 +      		JTDO2 <= ER2_TDO[8];
   2.206 +      	    end
   2.207 +      4'hA: begin
   2.208 +      		IP_ENABLE <= 15'b000001000000000;
   2.209 +      		JTDO2 <= ER2_TDO[9];
   2.210 +      	    end
   2.211 +      4'hB: begin
   2.212 +      		IP_ENABLE <= 15'b000010000000000;
   2.213 +      		JTDO2 <= ER2_TDO[10];
   2.214 +      	    end
   2.215 +      4'hC: begin
   2.216 +      		IP_ENABLE <= 15'b000100000000000;
   2.217 +      		JTDO2 <= ER2_TDO[11];
   2.218 +      	    end
   2.219 +      4'hD: begin
   2.220 +      		IP_ENABLE <= 15'b001000000000000;
   2.221 +      		JTDO2 <= ER2_TDO[12];
   2.222 +      	    end
   2.223 +      4'hE: begin
   2.224 +      		IP_ENABLE <= 15'b010000000000000;
   2.225 +      		JTDO2 <= ER2_TDO[13];
   2.226 +      	    end
   2.227 +      4'hF: begin
   2.228 +      		IP_ENABLE <= 15'b100000000000000;
   2.229 +      		JTDO2 <= ER2_TDO[14];
   2.230 +      	    end
   2.231 +    endcase
   2.232 +  end
   2.233 +endmodule
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/jtag_cores.v	Sun Apr 04 20:40:03 2010 +0100
     3.3 @@ -0,0 +1,125 @@
     3.4 +// ============================================================================
     3.5 +//                           COPYRIGHT NOTICE
     3.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     3.7 +// ALL RIGHTS RESERVED
     3.8 +// This confidential and proprietary software may be used only as authorised by
     3.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    3.10 +// The entire notice above must be reproduced on all authorized copies and
    3.11 +// copies may only be made to the extent permitted by a licensing agreement from
    3.12 +// Lattice Semiconductor Corporation.
    3.13 +//
    3.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    3.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    3.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    3.17 +// U.S.A                                   email: techsupport@latticesemi.com
    3.18 +// ============================================================================/
    3.19 +//                         FILE DETAILS
    3.20 +// Project          : LatticeMico32
    3.21 +// File             : jtag_cores.v
    3.22 +// Title            : Instantiates all IP cores on JTAG chain.
    3.23 +// Dependencies     : system_conf.v
    3.24 +// Version          : 6.0.14
    3.25 +//                  : modified to use jtagconn for LM32,
    3.26 +//                  : all technologies 7/10/07
    3.27 +// Version          : 7.0SP2, 3.0
    3.28 +//                  : No Change
    3.29 +// Version          : 3.1
    3.30 +//                  : No Change
    3.31 +// ============================================================================
    3.32 +
    3.33 +`include "system_conf.v"
    3.34 +
    3.35 +/////////////////////////////////////////////////////
    3.36 +// jtagconn16 Module Definition
    3.37 +/////////////////////////////////////////////////////
    3.38 +
    3.39 +module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    3.40 +    input  er2_tdo ; 
    3.41 +    output jtck ; 
    3.42 +    output jtdi ; 
    3.43 +    output jshift ; 
    3.44 +    output jupdate ; 
    3.45 +    output jrstn ; 
    3.46 +    output jce2 ; 
    3.47 +    output ip_enable ; 
    3.48 +endmodule
    3.49 +
    3.50 +/////////////////////////////////////////////////////
    3.51 +// Module interface
    3.52 +/////////////////////////////////////////////////////
    3.53 +
    3.54 +(* syn_hier="hard" *) module jtag_cores (
    3.55 +    // ----- Inputs -------
    3.56 +    reg_d,
    3.57 +    reg_addr_d,
    3.58 +    // ----- Outputs -------    
    3.59 +    reg_update,
    3.60 +    reg_q,
    3.61 +    reg_addr_q,
    3.62 +    jtck,
    3.63 +    jrstn
    3.64 +    );
    3.65 +    
    3.66 +/////////////////////////////////////////////////////
    3.67 +// Inputs
    3.68 +/////////////////////////////////////////////////////
    3.69 +
    3.70 +input [7:0] reg_d;
    3.71 +input [2:0] reg_addr_d;
    3.72 +
    3.73 +/////////////////////////////////////////////////////
    3.74 +// Outputs
    3.75 +/////////////////////////////////////////////////////
    3.76 +   
    3.77 +output reg_update;
    3.78 +wire   reg_update;
    3.79 +output [7:0] reg_q;
    3.80 +wire   [7:0] reg_q;
    3.81 +output [2:0] reg_addr_q;
    3.82 +wire   [2:0] reg_addr_q;
    3.83 +
    3.84 +output jtck;
    3.85 +wire   jtck; 	/* synthesis syn_keep=1 */
    3.86 +output jrstn;
    3.87 +wire   jrstn;  /* synthesis syn_keep=1 */	
    3.88 +
    3.89 +/////////////////////////////////////////////////////
    3.90 +// Instantiations
    3.91 +/////////////////////////////////////////////////////
    3.92 +
    3.93 +wire jtdi;          /* synthesis syn_keep=1 */
    3.94 +wire er2_tdo2;      /* synthesis syn_keep=1 */
    3.95 +wire jshift;        /* synthesis syn_keep=1 */
    3.96 +wire jupdate;       /* synthesis syn_keep=1 */
    3.97 +wire jce2;          /* synthesis syn_keep=1 */
    3.98 +wire ip_enable;     /* synthesis syn_keep=1 */
    3.99 +    
   3.100 +(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
   3.101 +    .er2_tdo        (er2_tdo2),
   3.102 +    .jtck           (jtck),
   3.103 +    .jtdi           (jtdi),
   3.104 +    .jshift         (jshift),
   3.105 +    .jupdate        (jupdate),
   3.106 +    .jrstn          (jrstn),
   3.107 +    .jce2           (jce2),
   3.108 +    .ip_enable      (ip_enable)
   3.109 +);
   3.110 +    
   3.111 +(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   3.112 +    .JTCK           (jtck),
   3.113 +    .JTDI           (jtdi),
   3.114 +    .JTDO2          (er2_tdo2),
   3.115 +    .JSHIFT         (jshift),
   3.116 +    .JUPDATE        (jupdate),
   3.117 +    .JRSTN          (jrstn),
   3.118 +    .JCE2           (jce2),
   3.119 +    .JTAGREG_ENABLE (ip_enable),
   3.120 +    .CONTROL_DATAN  (),
   3.121 +    .REG_UPDATE     (reg_update),
   3.122 +    .REG_D          (reg_d),
   3.123 +    .REG_ADDR_D     (reg_addr_d),
   3.124 +    .REG_Q          (reg_q),
   3.125 +    .REG_ADDR_Q     (reg_addr_q)
   3.126 +    );
   3.127 +    
   3.128 +endmodule
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/jtag_lm32.v	Sun Apr 04 20:40:03 2010 +0100
     4.3 @@ -0,0 +1,200 @@
     4.4 +// =============================================================================
     4.5 +//                           COPYRIGHT NOTICE
     4.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     4.7 +// ALL RIGHTS RESERVED
     4.8 +// This confidential and proprietary software may be used only as authorised by
     4.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    4.10 +// The entire notice above must be reproduced on all authorized copies and
    4.11 +// copies may only be made to the extent permitted by a licensing agreement from
    4.12 +// Lattice Semiconductor Corporation.
    4.13 +//
    4.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    4.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    4.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    4.17 +// U.S.A                                   email: techsupport@latticesemi.com
    4.18 +// =============================================================================/
    4.19 +//                         FILE DETAILS
    4.20 +// Project          : LatticeMico32
    4.21 +// File             : jtag_lm32.v
    4.22 +// Title            : JTAG data register for LM32 CPU debug interface
    4.23 +// Version          : 6.0.13
    4.24 +//                  : Initial Release
    4.25 +// Version          : 7.0SP2, 3.0
    4.26 +//                  : No Change
    4.27 +// Version          : 3.1
    4.28 +//                  : No Change
    4.29 +// =============================================================================
    4.30 +
    4.31 +/////////////////////////////////////////////////////
    4.32 +// Module interface
    4.33 +/////////////////////////////////////////////////////
    4.34 +
    4.35 +module jtag_lm32 (
    4.36 +	input JTCK,
    4.37 +	input JTDI,
    4.38 +	output JTDO2,
    4.39 +	input JSHIFT,
    4.40 +	input JUPDATE,
    4.41 +	input JRSTN,
    4.42 +	input JCE2,
    4.43 +	input JTAGREG_ENABLE,
    4.44 +	input CONTROL_DATAN,
    4.45 +	output REG_UPDATE,
    4.46 +	input [7:0] REG_D,
    4.47 +	input [2:0] REG_ADDR_D,
    4.48 +	output [7:0] REG_Q,
    4.49 +	output [2:0] REG_ADDR_Q
    4.50 +	);
    4.51 +
    4.52 +/////////////////////////////////////////////////////
    4.53 +// Internal nets and registers 
    4.54 +/////////////////////////////////////////////////////
    4.55 +
    4.56 +wire [9:0] tdibus;
    4.57 +
    4.58 +/////////////////////////////////////////////////////
    4.59 +// Instantiations
    4.60 +/////////////////////////////////////////////////////
    4.61 +   
    4.62 +TYPEA DATA_BIT0 (
    4.63 +    .CLK(JTCK),
    4.64 +    .RESET_N(JRSTN),
    4.65 +    .CLKEN(clk_enable),
    4.66 +    .TDI(JTDI),
    4.67 +    .TDO(tdibus[0]),
    4.68 +    .DATA_OUT(REG_Q[0]),
    4.69 +    .DATA_IN(REG_D[0]),
    4.70 +    .CAPTURE_DR(captureDr),
    4.71 +    .UPDATE_DR(JUPDATE)
    4.72 +    );
    4.73 +
    4.74 +TYPEA DATA_BIT1 (
    4.75 +    .CLK(JTCK),
    4.76 +    .RESET_N(JRSTN),
    4.77 +    .CLKEN(clk_enable),
    4.78 +    .TDI(tdibus[0]),
    4.79 +    .TDO(tdibus[1]),
    4.80 +    .DATA_OUT(REG_Q[1]),
    4.81 +    .DATA_IN(REG_D[1]),
    4.82 +    .CAPTURE_DR(captureDr),
    4.83 +    .UPDATE_DR(JUPDATE)
    4.84 +    );
    4.85 +
    4.86 +TYPEA DATA_BIT2 (
    4.87 +    .CLK(JTCK),
    4.88 +    .RESET_N(JRSTN),
    4.89 +    .CLKEN(clk_enable),
    4.90 +    .TDI(tdibus[1]),
    4.91 +    .TDO(tdibus[2]),
    4.92 +    .DATA_OUT(REG_Q[2]),
    4.93 +    .DATA_IN(REG_D[2]),
    4.94 +    .CAPTURE_DR(captureDr),
    4.95 +    .UPDATE_DR(JUPDATE)
    4.96 +    );
    4.97 +
    4.98 +TYPEA DATA_BIT3 (
    4.99 +    .CLK(JTCK),
   4.100 +    .RESET_N(JRSTN),
   4.101 +    .CLKEN(clk_enable),
   4.102 +    .TDI(tdibus[2]),
   4.103 +    .TDO(tdibus[3]),
   4.104 +    .DATA_OUT(REG_Q[3]),
   4.105 +    .DATA_IN(REG_D[3]),
   4.106 +    .CAPTURE_DR(captureDr),
   4.107 +    .UPDATE_DR(JUPDATE)
   4.108 +    );
   4.109 +
   4.110 +TYPEA DATA_BIT4 (
   4.111 +    .CLK(JTCK),
   4.112 +    .RESET_N(JRSTN),
   4.113 +    .CLKEN(clk_enable),
   4.114 +    .TDI(tdibus[3]),
   4.115 +    .TDO(tdibus[4]),
   4.116 +    .DATA_OUT(REG_Q[4]),
   4.117 +    .DATA_IN(REG_D[4]),
   4.118 +    .CAPTURE_DR(captureDr),
   4.119 +    .UPDATE_DR(JUPDATE)
   4.120 +    );
   4.121 +
   4.122 +TYPEA DATA_BIT5 (
   4.123 +    .CLK(JTCK),
   4.124 +    .RESET_N(JRSTN),
   4.125 +    .CLKEN(clk_enable),
   4.126 +    .TDI(tdibus[4]),
   4.127 +    .TDO(tdibus[5]),
   4.128 +    .DATA_OUT(REG_Q[5]),
   4.129 +    .DATA_IN(REG_D[5]),
   4.130 +    .CAPTURE_DR(captureDr),
   4.131 +    .UPDATE_DR(JUPDATE)
   4.132 +    );
   4.133 +
   4.134 +TYPEA DATA_BIT6 (
   4.135 +    .CLK(JTCK),
   4.136 +    .RESET_N(JRSTN),
   4.137 +    .CLKEN(clk_enable),
   4.138 +    .TDI(tdibus[5]),
   4.139 +    .TDO(tdibus[6]),
   4.140 +    .DATA_OUT(REG_Q[6]),
   4.141 +    .DATA_IN(REG_D[6]),
   4.142 +    .CAPTURE_DR(captureDr),
   4.143 +    .UPDATE_DR(JUPDATE)
   4.144 +    );
   4.145 +
   4.146 +TYPEA DATA_BIT7 (
   4.147 +    .CLK(JTCK),
   4.148 +    .RESET_N(JRSTN),
   4.149 +    .CLKEN(clk_enable),
   4.150 +    .TDI(tdibus[6]),
   4.151 +    .TDO(tdibus[7]),
   4.152 +    .DATA_OUT(REG_Q[7]),
   4.153 +    .DATA_IN(REG_D[7]),
   4.154 +    .CAPTURE_DR(captureDr),
   4.155 +    .UPDATE_DR(JUPDATE)
   4.156 +    );
   4.157 +
   4.158 +TYPEA ADDR_BIT0 (
   4.159 +    .CLK(JTCK),
   4.160 +    .RESET_N(JRSTN),
   4.161 +    .CLKEN(clk_enable),
   4.162 +    .TDI(tdibus[7]),
   4.163 +    .TDO(tdibus[8]),
   4.164 +    .DATA_OUT(REG_ADDR_Q[0]),
   4.165 +    .DATA_IN(REG_ADDR_D[0]),
   4.166 +    .CAPTURE_DR(captureDr),
   4.167 +    .UPDATE_DR(JUPDATE)
   4.168 +    );
   4.169 +
   4.170 +TYPEA ADDR_BIT1 (
   4.171 +    .CLK(JTCK),
   4.172 +    .RESET_N(JRSTN),
   4.173 +    .CLKEN(clk_enable),
   4.174 +    .TDI(tdibus[8]),
   4.175 +    .TDO(tdibus[9]),
   4.176 +    .DATA_OUT(REG_ADDR_Q[1]),
   4.177 +    .DATA_IN(REG_ADDR_D[1]),
   4.178 +    .CAPTURE_DR(captureDr),
   4.179 +    .UPDATE_DR(JUPDATE)
   4.180 +    );
   4.181 +
   4.182 +TYPEA ADDR_BIT2 (
   4.183 +    .CLK(JTCK),
   4.184 +    .RESET_N(JRSTN),
   4.185 +    .CLKEN(clk_enable),
   4.186 +    .TDI(tdibus[9]),
   4.187 +    .TDO(JTDO2),
   4.188 +    .DATA_OUT(REG_ADDR_Q[2]),
   4.189 +    .DATA_IN(REG_ADDR_D[2]),
   4.190 +    .CAPTURE_DR(captureDr),
   4.191 +    .UPDATE_DR(JUPDATE)
   4.192 +    );
   4.193 +
   4.194 +/////////////////////////////////////////////////////
   4.195 +// Combinational logic
   4.196 +/////////////////////////////////////////////////////
   4.197 +
   4.198 +assign clk_enable = JTAGREG_ENABLE & JCE2;
   4.199 +assign captureDr = !JSHIFT & JCE2;
   4.200 +// JCE2 is only active during shift
   4.201 +assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   4.202 + 
   4.203 +endmodule
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/lm32_adder.v	Sun Apr 04 20:40:03 2010 +0100
     5.3 @@ -0,0 +1,115 @@
     5.4 +// =============================================================================
     5.5 +//                           COPYRIGHT NOTICE
     5.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     5.7 +// ALL RIGHTS RESERVED
     5.8 +// This confidential and proprietary software may be used only as authorised by
     5.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    5.10 +// The entire notice above must be reproduced on all authorized copies and
    5.11 +// copies may only be made to the extent permitted by a licensing agreement from
    5.12 +// Lattice Semiconductor Corporation.
    5.13 +//
    5.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    5.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    5.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    5.17 +// U.S.A                                   email: techsupport@latticesemi.com
    5.18 +// ============================================================================/
    5.19 +//                         FILE DETAILS
    5.20 +// Project          : LatticeMico32
    5.21 +// File             : lm32_adder.v
    5.22 +// Title            : Integer adder / subtractor with comparison flag generation 
    5.23 +// Dependencies     : lm32_include.v
    5.24 +// Version          : 6.1.17
    5.25 +//                  : Initial Release
    5.26 +// Version          : 7.0SP2, 3.0
    5.27 +//                  : No Change
    5.28 +// Version          : 3.1
    5.29 +//                  : No Change
    5.30 +// =============================================================================
    5.31 +
    5.32 +`include "lm32_include.v"
    5.33 +
    5.34 +/////////////////////////////////////////////////////
    5.35 +// Module interface
    5.36 +/////////////////////////////////////////////////////
    5.37 +
    5.38 +module lm32_adder (
    5.39 +    // ----- Inputs -------
    5.40 +    adder_op_x,
    5.41 +    adder_op_x_n,
    5.42 +    operand_0_x,
    5.43 +    operand_1_x,
    5.44 +    // ----- Outputs -------
    5.45 +    adder_result_x,
    5.46 +    adder_carry_n_x,
    5.47 +    adder_overflow_x
    5.48 +    );
    5.49 +
    5.50 +/////////////////////////////////////////////////////
    5.51 +// Inputs
    5.52 +/////////////////////////////////////////////////////
    5.53 +
    5.54 +input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
    5.55 +input adder_op_x_n;                                     // Inverted version of adder_op_x
    5.56 +input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
    5.57 +input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
    5.58 +
    5.59 +/////////////////////////////////////////////////////
    5.60 +// Outputs
    5.61 +/////////////////////////////////////////////////////
    5.62 +
    5.63 +output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
    5.64 +wire   [`LM32_WORD_RNG] adder_result_x;
    5.65 +output adder_carry_n_x;                                 // Inverted carry
    5.66 +wire   adder_carry_n_x;
    5.67 +output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
    5.68 +reg    adder_overflow_x;
    5.69 +    
    5.70 +/////////////////////////////////////////////////////
    5.71 +// Internal nets and registers 
    5.72 +/////////////////////////////////////////////////////
    5.73 +
    5.74 +wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
    5.75 +wire b_sign;                                            // Sign of operand 1
    5.76 +wire result_sign;                                       // Sign of result
    5.77 +
    5.78 +/////////////////////////////////////////////////////
    5.79 +// Instantiations 
    5.80 +/////////////////////////////////////////////////////
    5.81 +
    5.82 +lm32_addsub addsub (
    5.83 +    // ----- Inputs -----
    5.84 +    .DataA          (operand_0_x), 
    5.85 +    .DataB          (operand_1_x), 
    5.86 +    .Cin            (adder_op_x), 
    5.87 +    .Add_Sub        (adder_op_x_n), 
    5.88 +    // ----- Ouputs -----
    5.89 +    .Result         (adder_result_x), 
    5.90 +    .Cout           (adder_carry_n_x)
    5.91 +    );
    5.92 +
    5.93 +/////////////////////////////////////////////////////
    5.94 +// Combinational Logic
    5.95 +/////////////////////////////////////////////////////
    5.96 +
    5.97 +// Extract signs of operands and result
    5.98 +
    5.99 +assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
   5.100 +assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
   5.101 +assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
   5.102 +
   5.103 +// Determine whether an overflow occured when performing a subtraction
   5.104 +
   5.105 +always @(*)
   5.106 +begin    
   5.107 +    //  +ve - -ve = -ve -> overflow
   5.108 +    //  -ve - +ve = +ve -> overflow
   5.109 +    if  (   (!a_sign & b_sign & result_sign)
   5.110 +         || (a_sign & !b_sign & !result_sign)
   5.111 +        )
   5.112 +        adder_overflow_x = `TRUE;
   5.113 +    else
   5.114 +        adder_overflow_x = `FALSE;
   5.115 +end
   5.116 +    
   5.117 +endmodule
   5.118 +
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/lm32_addsub.v	Sun Apr 04 20:40:03 2010 +0100
     6.3 @@ -0,0 +1,93 @@
     6.4 +// =============================================================================
     6.5 +//                           COPYRIGHT NOTICE
     6.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     6.7 +// ALL RIGHTS RESERVED
     6.8 +// This confidential and proprietary software may be used only as authorised by
     6.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    6.10 +// The entire notice above must be reproduced on all authorized copies and
    6.11 +// copies may only be made to the extent permitted by a licensing agreement from
    6.12 +// Lattice Semiconductor Corporation.
    6.13 +//
    6.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    6.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    6.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    6.17 +// U.S.A                                   email: techsupport@latticesemi.com
    6.18 +// =============================================================================/
    6.19 +//                         FILE DETAILS
    6.20 +// Project          : LatticeMico32
    6.21 +// File             : lm32_addsub.v
    6.22 +// Title            : PMI adder/subtractor.
    6.23 +// Version          : 6.1.17
    6.24 +//                  : Initial Release
    6.25 +// Version          : 7.0SP2, 3.0
    6.26 +//                  : No Change
    6.27 +// Version          : 3.1
    6.28 +//                  : No Change
    6.29 +// =============================================================================
    6.30 +
    6.31 +`include "lm32_include.v"
    6.32 +
    6.33 +/////////////////////////////////////////////////////
    6.34 +// Module interface
    6.35 +/////////////////////////////////////////////////////
    6.36 +
    6.37 +module lm32_addsub (
    6.38 +    // ----- Inputs -------
    6.39 +    DataA, 
    6.40 +    DataB, 
    6.41 +    Cin, 
    6.42 +    Add_Sub, 
    6.43 +    // ----- Outputs -------
    6.44 +    Result, 
    6.45 +    Cout
    6.46 +    );
    6.47 +
    6.48 +/////////////////////////////////////////////////////
    6.49 +// Inputs
    6.50 +/////////////////////////////////////////////////////
    6.51 +
    6.52 +input [31:0] DataA;
    6.53 +input [31:0] DataB;
    6.54 +input Cin;
    6.55 +input Add_Sub;
    6.56 +
    6.57 +/////////////////////////////////////////////////////
    6.58 +// Outputs
    6.59 +/////////////////////////////////////////////////////
    6.60 +
    6.61 +output [31:0] Result;
    6.62 +wire   [31:0] Result;
    6.63 +output Cout;
    6.64 +wire   Cout;
    6.65 +
    6.66 +/////////////////////////////////////////////////////
    6.67 +// Instantiations
    6.68 +///////////////////////////////////////////////////// 
    6.69 +
    6.70 +       generate
    6.71 +	  if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
    6.72 +	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
    6.73 +	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
    6.74 +   
    6.75 +	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
    6.76 +	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
    6.77 +	  end else begin
    6.78 +	    pmi_addsub #(// ----- Parameters -------
    6.79 +			 .pmi_data_width     (32),
    6.80 +			 .pmi_result_width   (32),
    6.81 +			 .pmi_sign           ("off"),
    6.82 +			 .pmi_family         (`LATTICE_FAMILY),
    6.83 +			 .module_type        ("pmi_addsub")) 
    6.84 +	      addsub    (// ----- Inputs -------
    6.85 +			 .DataA              (DataA),
    6.86 +			 .DataB              (DataB),
    6.87 +			 .Cin                (Cin),
    6.88 +			 .Add_Sub            (Add_Sub),
    6.89 +			 // ----- Outputs -------
    6.90 +			 .Result             (Result),
    6.91 +			 .Cout               (Cout),
    6.92 +			 .Overflow           ());
    6.93 +	  end
    6.94 +       endgenerate 
    6.95 +
    6.96 +endmodule
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/lm32_cpu.v	Sun Apr 04 20:40:03 2010 +0100
     7.3 @@ -0,0 +1,2732 @@
     7.4 +// =============================================================================
     7.5 +//                           COPYRIGHT NOTICE
     7.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     7.7 +// ALL RIGHTS RESERVED
     7.8 +// This confidential and proprietary software may be used only as authorised by
     7.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    7.10 +// The entire notice above must be reproduced on all authorized copies and
    7.11 +// copies may only be made to the extent permitted by a licensing agreement from
    7.12 +// Lattice Semiconductor Corporation.
    7.13 +//
    7.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    7.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    7.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    7.17 +// U.S.A                                   email: techsupport@latticesemi.com
    7.18 +// =============================================================================/
    7.19 +//                         FILE DETAILS
    7.20 +// Project          : LatticeMico32
    7.21 +// File             : lm32_cpu.v
    7.22 +// Title            : Top-level of CPU.
    7.23 +// Dependencies     : lm32_include.v
    7.24 +//
    7.25 +// Version 3.4
    7.26 +// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    7.27 +//    never serviced.
    7.28 +//    
    7.29 +// Version 3.3
    7.30 +// 1. Feature: Support for memory that is tightly coupled to processor core, and 
    7.31 +//    has a single-cycle access latency (same as caches). Instruction port has
    7.32 +//    access to a dedicated physically-mapped memory. Data port has access to
    7.33 +//    a dedicated physically-mapped memory. In order to be able to manipulate
    7.34 +//    values in both these memories via the debugger, these memories also
    7.35 +//    interface with the data port of LM32.
    7.36 +// 2. Feature: Extended Configuration Register
    7.37 +// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
    7.38 +//    Verilog.
    7.39 +//
    7.40 +// Version 3.2
    7.41 +// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
    7.42 +//    hang. At the same time CPU fails to register data bus error exception. Bug
    7.43 +//    is caused because (a) data bus error exception occurs after load/store has
    7.44 +//    passed X stage and next sequential instruction (e.g., brk) is already in X
    7.45 +//    stage, and (b) data bus error exception had lower priority than, say, brk
    7.46 +//    exception.
    7.47 +// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
    7.48 +//    invalid location, CPU will fail to register data bus error exception. The
    7.49 +//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
    7.50 +//    until load/store has completed.
    7.51 +// 3. Feature: Enable precise identification of load/store that causes seg fault.
    7.52 +// 4. SYNC resets used for register file when implemented in EBRs.
    7.53 +//
    7.54 +// Version 3.1
    7.55 +// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
    7.56 +//    instead of distributed memory by enabling the option in LM32 GUI. 
    7.57 +// 2. Feature: LM32 also adds a static branch predictor to improve branch 
    7.58 +//    performance. All immediate-based forward-pointing branches are predicted 
    7.59 +//    not-taken. All immediate-based backward-pointing branches are predicted taken.
    7.60 +// 
    7.61 +// Version 7.0SP2, 3.0
    7.62 +// No Change
    7.63 +//
    7.64 +// Version 6.1.17
    7.65 +// Initial Release
    7.66 +// =============================================================================
    7.67 +
    7.68 +`include "lm32_include.v"
    7.69 +
    7.70 +/////////////////////////////////////////////////////
    7.71 +// Module interface
    7.72 +/////////////////////////////////////////////////////
    7.73 +
    7.74 +module lm32_cpu (
    7.75 +    // ----- Inputs -------
    7.76 +    clk_i,
    7.77 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    7.78 +    clk_n_i,
    7.79 +`endif    
    7.80 +    rst_i,
    7.81 +    // From external devices
    7.82 +`ifdef CFG_INTERRUPTS_ENABLED
    7.83 +    interrupt_n,
    7.84 +`endif
    7.85 +    // From user logic
    7.86 +`ifdef CFG_USER_ENABLED
    7.87 +    user_result,
    7.88 +    user_complete,
    7.89 +`endif     
    7.90 +`ifdef CFG_JTAG_ENABLED
    7.91 +    // From JTAG
    7.92 +    jtag_clk,
    7.93 +    jtag_update, 
    7.94 +    jtag_reg_q,
    7.95 +    jtag_reg_addr_q,
    7.96 +`endif
    7.97 +`ifdef CFG_IWB_ENABLED
    7.98 +    // Instruction Wishbone master
    7.99 +    I_DAT_I,
   7.100 +    I_ACK_I,
   7.101 +    I_ERR_I,
   7.102 +    I_RTY_I,
   7.103 +`endif
   7.104 +    // Data Wishbone master
   7.105 +    D_DAT_I,
   7.106 +    D_ACK_I,
   7.107 +    D_ERR_I,
   7.108 +    D_RTY_I,
   7.109 +    // ----- Outputs -------
   7.110 +`ifdef CFG_TRACE_ENABLED
   7.111 +    trace_pc,
   7.112 +    trace_pc_valid,
   7.113 +    trace_exception,
   7.114 +    trace_eid,
   7.115 +    trace_eret,
   7.116 +`ifdef CFG_DEBUG_ENABLED
   7.117 +    trace_bret,
   7.118 +`endif
   7.119 +`endif
   7.120 +`ifdef CFG_JTAG_ENABLED
   7.121 +    jtag_reg_d,
   7.122 +    jtag_reg_addr_d,
   7.123 +`endif
   7.124 +`ifdef CFG_USER_ENABLED    
   7.125 +    user_valid,
   7.126 +    user_opcode,
   7.127 +    user_operand_0,
   7.128 +    user_operand_1,
   7.129 +`endif    
   7.130 +`ifdef CFG_IWB_ENABLED
   7.131 +    // Instruction Wishbone master
   7.132 +    I_DAT_O,
   7.133 +    I_ADR_O,
   7.134 +    I_CYC_O,
   7.135 +    I_SEL_O,
   7.136 +    I_STB_O,
   7.137 +    I_WE_O,
   7.138 +    I_CTI_O,
   7.139 +    I_LOCK_O,
   7.140 +    I_BTE_O,
   7.141 +`endif
   7.142 +    // Data Wishbone master
   7.143 +    D_DAT_O,
   7.144 +    D_ADR_O,
   7.145 +    D_CYC_O,
   7.146 +    D_SEL_O,
   7.147 +    D_STB_O,
   7.148 +    D_WE_O,
   7.149 +    D_CTI_O,
   7.150 +    D_LOCK_O,
   7.151 +    D_BTE_O
   7.152 +    );
   7.153 +
   7.154 +/////////////////////////////////////////////////////
   7.155 +// Parameters
   7.156 +/////////////////////////////////////////////////////
   7.157 +
   7.158 +parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
   7.159 +`ifdef CFG_DEBUG_ENABLED
   7.160 +parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
   7.161 +`endif
   7.162 +
   7.163 +`ifdef CFG_ICACHE_ENABLED
   7.164 +parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   7.165 +parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
   7.166 +parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   7.167 +parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
   7.168 +parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
   7.169 +`else
   7.170 +parameter icache_associativity = 1;    
   7.171 +parameter icache_sets = 512;                      
   7.172 +parameter icache_bytes_per_line = 16;  
   7.173 +parameter icache_base_address = 0;      
   7.174 +parameter icache_limit = 0;                    
   7.175 +`endif
   7.176 +
   7.177 +`ifdef CFG_DCACHE_ENABLED
   7.178 +parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   7.179 +parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
   7.180 +parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   7.181 +parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
   7.182 +parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
   7.183 +`else
   7.184 +parameter dcache_associativity = 1;    
   7.185 +parameter dcache_sets = 512;                      
   7.186 +parameter dcache_bytes_per_line = 16;  
   7.187 +parameter dcache_base_address = 0;      
   7.188 +parameter dcache_limit = 0;                    
   7.189 +`endif
   7.190 +
   7.191 +`ifdef CFG_DEBUG_ENABLED
   7.192 +parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
   7.193 +`else
   7.194 +parameter watchpoints = 0;
   7.195 +`endif
   7.196 +`ifdef CFG_ROM_DEBUG_ENABLED
   7.197 +parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
   7.198 +`else
   7.199 +parameter breakpoints = 0;
   7.200 +`endif
   7.201 +
   7.202 +`ifdef CFG_INTERRUPTS_ENABLED
   7.203 +parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
   7.204 +`else
   7.205 +parameter interrupts = 0;
   7.206 +`endif
   7.207 +
   7.208 +/////////////////////////////////////////////////////
   7.209 +// Inputs
   7.210 +/////////////////////////////////////////////////////
   7.211 +
   7.212 +input clk_i;                                    // Clock
   7.213 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   7.214 +input clk_n_i;                                  // Inverted clock
   7.215 +`endif    
   7.216 +input rst_i;                                    // Reset
   7.217 +
   7.218 +`ifdef CFG_INTERRUPTS_ENABLED
   7.219 +input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
   7.220 +`endif
   7.221 +
   7.222 +`ifdef CFG_USER_ENABLED
   7.223 +input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   7.224 +input user_complete;                            // User-defined instruction execution is complete
   7.225 +`endif    
   7.226 +
   7.227 +`ifdef CFG_JTAG_ENABLED
   7.228 +input jtag_clk;                                 // JTAG clock
   7.229 +input jtag_update;                              // JTAG state machine is in data register update state
   7.230 +input [`LM32_BYTE_RNG] jtag_reg_q;              
   7.231 +input [2:0] jtag_reg_addr_q;
   7.232 +`endif
   7.233 +
   7.234 +`ifdef CFG_IWB_ENABLED
   7.235 +input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   7.236 +input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   7.237 +input I_ERR_I;                                  // Instruction Wishbone interface error
   7.238 +input I_RTY_I;                                  // Instruction Wishbone interface retry
   7.239 +`endif
   7.240 +
   7.241 +input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   7.242 +input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   7.243 +input D_ERR_I;                                  // Data Wishbone interface error
   7.244 +input D_RTY_I;                                  // Data Wishbone interface retry
   7.245 +
   7.246 +/////////////////////////////////////////////////////
   7.247 +// Outputs
   7.248 +/////////////////////////////////////////////////////
   7.249 +
   7.250 +`ifdef CFG_TRACE_ENABLED
   7.251 +output [`LM32_PC_RNG] trace_pc;                 // PC to trace
   7.252 +reg    [`LM32_PC_RNG] trace_pc;
   7.253 +output trace_pc_valid;                          // Indicates that a new trace PC is valid
   7.254 +reg    trace_pc_valid;
   7.255 +output trace_exception;                         // Indicates an exception has occured
   7.256 +reg    trace_exception;
   7.257 +output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
   7.258 +reg    [`LM32_EID_RNG] trace_eid;
   7.259 +output trace_eret;                              // Indicates an eret instruction has been executed
   7.260 +reg    trace_eret;
   7.261 +`ifdef CFG_DEBUG_ENABLED
   7.262 +output trace_bret;                              // Indicates a bret instruction has been executed
   7.263 +reg    trace_bret;
   7.264 +`endif
   7.265 +`endif
   7.266 +
   7.267 +`ifdef CFG_JTAG_ENABLED
   7.268 +output [`LM32_BYTE_RNG] jtag_reg_d;
   7.269 +wire   [`LM32_BYTE_RNG] jtag_reg_d;
   7.270 +output [2:0] jtag_reg_addr_d;
   7.271 +wire   [2:0] jtag_reg_addr_d;
   7.272 +`endif
   7.273 +
   7.274 +`ifdef CFG_USER_ENABLED
   7.275 +output user_valid;                              // Indicates if user_opcode is valid
   7.276 +wire   user_valid;
   7.277 +output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   7.278 +reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   7.279 +output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   7.280 +wire   [`LM32_WORD_RNG] user_operand_0;
   7.281 +output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   7.282 +wire   [`LM32_WORD_RNG] user_operand_1;
   7.283 +`endif
   7.284 +
   7.285 +`ifdef CFG_IWB_ENABLED
   7.286 +output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   7.287 +wire   [`LM32_WORD_RNG] I_DAT_O;
   7.288 +output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   7.289 +wire   [`LM32_WORD_RNG] I_ADR_O;
   7.290 +output I_CYC_O;                                 // Instruction Wishbone interface cycle
   7.291 +wire   I_CYC_O;
   7.292 +output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   7.293 +wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   7.294 +output I_STB_O;                                 // Instruction Wishbone interface strobe
   7.295 +wire   I_STB_O;
   7.296 +output I_WE_O;                                  // Instruction Wishbone interface write enable
   7.297 +wire   I_WE_O;
   7.298 +output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   7.299 +wire   [`LM32_CTYPE_RNG] I_CTI_O;
   7.300 +output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   7.301 +wire   I_LOCK_O;
   7.302 +output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   7.303 +wire   [`LM32_BTYPE_RNG] I_BTE_O;
   7.304 +`endif
   7.305 +
   7.306 +output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   7.307 +wire   [`LM32_WORD_RNG] D_DAT_O;
   7.308 +output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   7.309 +wire   [`LM32_WORD_RNG] D_ADR_O;
   7.310 +output D_CYC_O;                                 // Data Wishbone interface cycle
   7.311 +wire   D_CYC_O;
   7.312 +output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   7.313 +wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   7.314 +output D_STB_O;                                 // Data Wishbone interface strobe
   7.315 +wire   D_STB_O;
   7.316 +output D_WE_O;                                  // Data Wishbone interface write enable
   7.317 +wire   D_WE_O;
   7.318 +output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   7.319 +wire   [`LM32_CTYPE_RNG] D_CTI_O;
   7.320 +output D_LOCK_O;                                // Date Wishbone interface lock bus
   7.321 +wire   D_LOCK_O;
   7.322 +output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   7.323 +wire   [`LM32_BTYPE_RNG] D_BTE_O;
   7.324 +
   7.325 +/////////////////////////////////////////////////////
   7.326 +// Internal nets and registers 
   7.327 +/////////////////////////////////////////////////////
   7.328 +
   7.329 +// Pipeline registers
   7.330 +
   7.331 +`ifdef LM32_CACHE_ENABLED
   7.332 +reg valid_a;                                    // Instruction in A stage is valid
   7.333 +`endif
   7.334 +reg valid_f;                                    // Instruction in F stage is valid
   7.335 +reg valid_d;                                    // Instruction in D stage is valid
   7.336 +reg valid_x;                                    // Instruction in X stage is valid
   7.337 +reg valid_m;                                    // Instruction in M stage is valid
   7.338 +reg valid_w;                                    // Instruction in W stage is valid
   7.339 +   
   7.340 +wire q_x;
   7.341 +wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
   7.342 +wire load_d;                                    // Indicates a load instruction
   7.343 +reg load_x;                                     
   7.344 +reg load_m;
   7.345 +wire load_q_x;
   7.346 +wire store_q_x;
   7.347 +wire store_d;                                   // Indicates a store instruction
   7.348 +reg store_x;
   7.349 +reg store_m;
   7.350 +wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
   7.351 +reg [`LM32_SIZE_RNG] size_x;
   7.352 +wire branch_d;                                  // Indicates a branch instruction
   7.353 +wire branch_predict_d;                          // Indicates a branch is predicted
   7.354 +wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
   7.355 +wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
   7.356 +wire [`LM32_PC_RNG] branch_target_d;
   7.357 +wire bi_unconditional;
   7.358 +wire bi_conditional;
   7.359 +reg branch_x;                                   
   7.360 +reg branch_predict_x;
   7.361 +reg branch_predict_taken_x;
   7.362 +reg branch_m;
   7.363 +reg branch_predict_m;
   7.364 +reg branch_predict_taken_m;
   7.365 +wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
   7.366 +wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
   7.367 +wire branch_reg_d;                              // Branch to register or immediate
   7.368 +wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
   7.369 +reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
   7.370 +reg [`LM32_PC_RNG] branch_target_m;
   7.371 +wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
   7.372 +wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
   7.373 +
   7.374 +wire x_result_sel_csr_d;                        // Select X stage result from CSRs
   7.375 +reg x_result_sel_csr_x;
   7.376 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.377 +wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
   7.378 +reg x_result_sel_mc_arith_x;
   7.379 +`endif
   7.380 +`ifdef LM32_NO_BARREL_SHIFT    
   7.381 +wire x_result_sel_shift_d;                      // Select X stage result from shifter
   7.382 +reg x_result_sel_shift_x;
   7.383 +`endif
   7.384 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.385 +wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
   7.386 +reg x_result_sel_sext_x;
   7.387 +`endif
   7.388 +wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
   7.389 +reg x_result_sel_logic_x;
   7.390 +`ifdef CFG_USER_ENABLED
   7.391 +wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
   7.392 +reg x_result_sel_user_x;
   7.393 +`endif
   7.394 +wire x_result_sel_add_d;                        // Select X stage result from adder
   7.395 +reg x_result_sel_add_x;
   7.396 +wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
   7.397 +reg m_result_sel_compare_x;
   7.398 +reg m_result_sel_compare_m;
   7.399 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.400 +wire m_result_sel_shift_d;                      // Select M stage result from shifter
   7.401 +reg m_result_sel_shift_x;
   7.402 +reg m_result_sel_shift_m;
   7.403 +`endif
   7.404 +wire w_result_sel_load_d;                       // Select W stage result from load/store unit
   7.405 +reg w_result_sel_load_x;
   7.406 +reg w_result_sel_load_m;
   7.407 +reg w_result_sel_load_w;
   7.408 +`ifdef CFG_PL_MULTIPLY_ENABLED
   7.409 +wire w_result_sel_mul_d;                        // Select W stage result from multiplier
   7.410 +reg w_result_sel_mul_x;
   7.411 +reg w_result_sel_mul_m;
   7.412 +reg w_result_sel_mul_w;
   7.413 +`endif
   7.414 +wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
   7.415 +reg x_bypass_enable_x;                          
   7.416 +wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
   7.417 +reg m_bypass_enable_x;                          
   7.418 +reg m_bypass_enable_m;
   7.419 +wire sign_extend_d;                             // Whether to sign-extend or zero-extend
   7.420 +reg sign_extend_x;
   7.421 +wire write_enable_d;                            // Register file write enable
   7.422 +reg write_enable_x;
   7.423 +wire write_enable_q_x;
   7.424 +reg write_enable_m;
   7.425 +wire write_enable_q_m;
   7.426 +reg write_enable_w;
   7.427 +wire write_enable_q_w;
   7.428 +wire read_enable_0_d;                           // Register file read enable 0
   7.429 +wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
   7.430 +wire read_enable_1_d;                           // Register file read enable 1
   7.431 +wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
   7.432 +wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
   7.433 +reg [`LM32_REG_IDX_RNG] write_idx_x;            
   7.434 +reg [`LM32_REG_IDX_RNG] write_idx_m;
   7.435 +reg [`LM32_REG_IDX_RNG] write_idx_w;
   7.436 +wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
   7.437 +reg  [`LM32_CSR_RNG] csr_x;                  
   7.438 +wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
   7.439 +reg [`LM32_CONDITION_RNG] condition_x;          
   7.440 +`ifdef CFG_DEBUG_ENABLED
   7.441 +wire break_d;                                   // Indicates a break instruction
   7.442 +reg break_x;                                    
   7.443 +`endif
   7.444 +wire scall_d;                                   // Indicates a scall instruction
   7.445 +reg scall_x;    
   7.446 +wire eret_d;                                    // Indicates an eret instruction
   7.447 +reg eret_x;
   7.448 +wire eret_q_x;
   7.449 +reg eret_m;
   7.450 +`ifdef CFG_TRACE_ENABLED
   7.451 +reg eret_w;
   7.452 +`endif
   7.453 +`ifdef CFG_DEBUG_ENABLED
   7.454 +wire bret_d;                                    // Indicates a bret instruction
   7.455 +reg bret_x;
   7.456 +wire bret_q_x;
   7.457 +reg bret_m;
   7.458 +`ifdef CFG_TRACE_ENABLED
   7.459 +reg bret_w;
   7.460 +`endif
   7.461 +`endif
   7.462 +wire csr_write_enable_d;                        // CSR write enable
   7.463 +reg csr_write_enable_x;
   7.464 +wire csr_write_enable_q_x;
   7.465 +`ifdef CFG_USER_ENABLED
   7.466 +wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
   7.467 +`endif
   7.468 +
   7.469 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.470 +wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
   7.471 +reg bus_error_x;
   7.472 +reg data_bus_error_exception_m;
   7.473 +reg [`LM32_PC_RNG] memop_pc_w;
   7.474 +`endif
   7.475 +
   7.476 +reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
   7.477 +reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
   7.478 +reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
   7.479 +reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
   7.480 +reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
   7.481 +
   7.482 +reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
   7.483 +reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
   7.484 +reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
   7.485 +reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
   7.486 +reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
   7.487 +
   7.488 +// To/from register file
   7.489 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.490 +reg [`LM32_WORD_RNG] reg_data_live_0;          
   7.491 +reg [`LM32_WORD_RNG] reg_data_live_1;  
   7.492 +reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
   7.493 +reg [`LM32_WORD_RNG] reg_data_buf_0;
   7.494 +reg [`LM32_WORD_RNG] reg_data_buf_1;
   7.495 +`endif
   7.496 +`ifdef LM32_EBR_REGISTER_FILE
   7.497 +`else
   7.498 +reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
   7.499 +`endif
   7.500 +wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
   7.501 +wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
   7.502 +reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
   7.503 +reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
   7.504 +wire reg_write_enable_q_w;
   7.505 +
   7.506 +reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
   7.507 +
   7.508 +wire stall_a;                                   // Stall instruction in A pipeline stage
   7.509 +wire stall_f;                                   // Stall instruction in F pipeline stage
   7.510 +wire stall_d;                                   // Stall instruction in D pipeline stage
   7.511 +wire stall_x;                                   // Stall instruction in X pipeline stage
   7.512 +wire stall_m;                                   // Stall instruction in M pipeline stage
   7.513 +
   7.514 +// To/from adder
   7.515 +wire adder_op_d;                                // Whether to add or subtract
   7.516 +reg adder_op_x;                                 
   7.517 +reg adder_op_x_n;                               // Inverted version of adder_op_x
   7.518 +wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
   7.519 +wire adder_overflow_x;                          // Whether a signed overflow occured
   7.520 +wire adder_carry_n_x;                           // Whether a carry was generated
   7.521 +
   7.522 +// To/from logical operations unit
   7.523 +wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
   7.524 +reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
   7.525 +wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
   7.526 +
   7.527 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.528 +// From sign-extension unit
   7.529 +wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
   7.530 +wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
   7.531 +wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
   7.532 +`endif
   7.533 +
   7.534 +// To/from shifter
   7.535 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.536 +`ifdef CFG_ROTATE_ENABLED
   7.537 +wire rotate_d;                                  // Whether we should rotate or shift
   7.538 +reg rotate_x;                                    
   7.539 +`endif
   7.540 +wire direction_d;                               // Which direction to shift in
   7.541 +reg direction_x;                                        
   7.542 +reg direction_m;
   7.543 +wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
   7.544 +`endif
   7.545 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   7.546 +wire shift_left_d;                              // Indicates whether to perform a left shift or not
   7.547 +wire shift_left_q_d;
   7.548 +wire shift_right_d;                             // Indicates whether to perform a right shift or not
   7.549 +wire shift_right_q_d;
   7.550 +`endif
   7.551 +`ifdef LM32_NO_BARREL_SHIFT
   7.552 +wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
   7.553 +`endif
   7.554 +
   7.555 +// To/from multiplier
   7.556 +`ifdef LM32_MULTIPLY_ENABLED
   7.557 +wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
   7.558 +`endif
   7.559 +`ifdef CFG_MC_MULTIPLY_ENABLED
   7.560 +wire multiply_d;                                // Indicates whether to perform a multiply or not
   7.561 +wire multiply_q_d;
   7.562 +`endif
   7.563 +
   7.564 +// To/from divider
   7.565 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.566 +wire divide_d;                                  // Indicates whether to perform a divider or not
   7.567 +wire divide_q_d;
   7.568 +wire modulus_d;
   7.569 +wire modulus_q_d;
   7.570 +wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
   7.571 +`endif
   7.572 +
   7.573 +// To from multi-cycle arithmetic unit
   7.574 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.575 +wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
   7.576 +wire [`LM32_WORD_RNG] mc_result_x;
   7.577 +`endif
   7.578 +
   7.579 +// From CSRs
   7.580 +`ifdef CFG_INTERRUPTS_ENABLED
   7.581 +wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
   7.582 +`endif
   7.583 +wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
   7.584 +wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
   7.585 +`ifdef CFG_CYCLE_COUNTER_ENABLED
   7.586 +reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
   7.587 +`endif
   7.588 +reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
   7.589 +
   7.590 +// To/from instruction unit
   7.591 +wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
   7.592 +wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
   7.593 +wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
   7.594 +wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
   7.595 +wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
   7.596 +`ifdef CFG_TRACE_ENABLED
   7.597 +reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
   7.598 +`endif
   7.599 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.600 +wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
   7.601 +`endif
   7.602 +//pragma attribute instruction_d preserve_signal true
   7.603 +//pragma attribute instruction_d preserve_driver true
   7.604 +wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
   7.605 +`ifdef CFG_ICACHE_ENABLED
   7.606 +wire iflush;                                    // Flush instruction cache
   7.607 +wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
   7.608 +wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
   7.609 +wire icache_refill_request;                     // Request to refill instruction cache
   7.610 +wire icache_refilling;                          // Indicates the instruction cache is being refilled
   7.611 +`endif
   7.612 +`ifdef CFG_IROM_ENABLED
   7.613 +wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
   7.614 +wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
   7.615 +wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
   7.616 +wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
   7.617 +wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
   7.618 +`endif
   7.619 +
   7.620 +// To/from load/store unit
   7.621 +`ifdef CFG_DCACHE_ENABLED
   7.622 +wire dflush_x;                                  // Flush data cache    
   7.623 +reg dflush_m;                                    
   7.624 +wire dcache_stall_request;                      // Stall pipeline because data cache is busy
   7.625 +wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
   7.626 +wire dcache_refill_request;                     // Request to refill data cache
   7.627 +wire dcache_refilling;                          // Indicates the data cache is being refilled
   7.628 +`endif
   7.629 +wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
   7.630 +wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
   7.631 +
   7.632 +// To/from JTAG interface
   7.633 +`ifdef CFG_JTAG_ENABLED
   7.634 +`ifdef CFG_JTAG_UART_ENABLED
   7.635 +wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
   7.636 +wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
   7.637 +`endif
   7.638 +`ifdef CFG_HW_DEBUG_ENABLED
   7.639 +wire jtag_csr_write_enable;                     // Debugger CSR write enable
   7.640 +wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
   7.641 +wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
   7.642 +wire jtag_read_enable;                          
   7.643 +wire [`LM32_BYTE_RNG] jtag_read_data;
   7.644 +wire jtag_write_enable;
   7.645 +wire [`LM32_BYTE_RNG] jtag_write_data;
   7.646 +wire [`LM32_WORD_RNG] jtag_address;
   7.647 +wire jtag_access_complete;
   7.648 +`endif
   7.649 +`ifdef CFG_DEBUG_ENABLED
   7.650 +wire jtag_break;                                // Request from debugger to raise a breakpoint
   7.651 +`endif
   7.652 +`endif
   7.653 +
   7.654 +// Hazzard detection
   7.655 +wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
   7.656 +wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
   7.657 +wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
   7.658 +wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
   7.659 +wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
   7.660 +wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
   7.661 +
   7.662 +// Control flow
   7.663 +wire cmp_zero;                                  // Result of comparison is zero
   7.664 +wire cmp_negative;                              // Result of comparison is negative
   7.665 +wire cmp_overflow;                              // Comparison produced an overflow
   7.666 +wire cmp_carry_n;                               // Comparison produced a carry, inverted
   7.667 +reg condition_met_x;                            // Condition of branch instruction is met
   7.668 +reg condition_met_m;
   7.669 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   7.670 +wire branch_taken_x;                            // Branch is taken in X stage
   7.671 +`endif
   7.672 +wire branch_taken_m;                            // Branch is taken in M stage
   7.673 +
   7.674 +wire kill_f;                                    // Kill instruction in F stage
   7.675 +wire kill_d;                                    // Kill instruction in D stage
   7.676 +wire kill_x;                                    // Kill instruction in X stage
   7.677 +wire kill_m;                                    // Kill instruction in M stage
   7.678 +wire kill_w;                                    // Kill instruction in W stage
   7.679 +
   7.680 +reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
   7.681 +`ifdef CFG_DEBUG_ENABLED
   7.682 +reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
   7.683 +`endif
   7.684 +reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
   7.685 +`ifdef CFG_TRACE_ENABLED
   7.686 +reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
   7.687 +reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
   7.688 +`endif
   7.689 +
   7.690 +`ifdef CFG_DEBUG_ENABLED
   7.691 +`ifdef LM32_SINGLE_STEP_ENABLED
   7.692 +wire dc_ss;                                     // Is single-step enabled
   7.693 +`endif
   7.694 +wire dc_re;                                     // Remap all exceptions
   7.695 +wire exception_x;                               // An exception occured in the X stage
   7.696 +reg exception_m;                                // An instruction that caused an exception is in the M stage
   7.697 +wire debug_exception_x;                         // Indicates if a debug exception has occured
   7.698 +reg debug_exception_m;
   7.699 +reg debug_exception_w;
   7.700 +wire debug_exception_q_w;
   7.701 +wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
   7.702 +reg non_debug_exception_m;
   7.703 +reg non_debug_exception_w;
   7.704 +wire non_debug_exception_q_w;
   7.705 +`else
   7.706 +wire exception_x;                               // Indicates if a debug exception has occured
   7.707 +reg exception_m;
   7.708 +reg exception_w;
   7.709 +wire exception_q_w;
   7.710 +`endif
   7.711 +
   7.712 +`ifdef CFG_DEBUG_ENABLED
   7.713 +`ifdef CFG_JTAG_ENABLED
   7.714 +wire reset_exception;                           // Indicates if a reset exception has occured
   7.715 +`endif
   7.716 +`endif
   7.717 +`ifdef CFG_INTERRUPTS_ENABLED
   7.718 +wire interrupt_exception;                       // Indicates if an interrupt exception has occured
   7.719 +`endif
   7.720 +`ifdef CFG_DEBUG_ENABLED
   7.721 +wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
   7.722 +wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
   7.723 +`endif
   7.724 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.725 +wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
   7.726 +wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
   7.727 +`endif
   7.728 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.729 +wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
   7.730 +`endif
   7.731 +wire system_call_exception;                     // Indicates if a system call exception has occured
   7.732 +
   7.733 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.734 +reg data_bus_error_seen;                        // Indicates if a data bus error was seen
   7.735 +`endif
   7.736 +
   7.737 +/////////////////////////////////////////////////////
   7.738 +// Functions
   7.739 +/////////////////////////////////////////////////////
   7.740 +
   7.741 +`include "lm32_functions.v"
   7.742 +
   7.743 +/////////////////////////////////////////////////////
   7.744 +// Instantiations
   7.745 +///////////////////////////////////////////////////// 
   7.746 +
   7.747 +// Instruction unit
   7.748 +lm32_instruction_unit #(
   7.749 +    .associativity          (icache_associativity),
   7.750 +    .sets                   (icache_sets),
   7.751 +    .bytes_per_line         (icache_bytes_per_line),
   7.752 +    .base_address           (icache_base_address),
   7.753 +    .limit                  (icache_limit)
   7.754 +  ) instruction_unit (
   7.755 +    // ----- Inputs -------
   7.756 +    .clk_i                  (clk_i),
   7.757 +    .rst_i                  (rst_i),
   7.758 +    // From pipeline
   7.759 +    .stall_a                (stall_a),
   7.760 +    .stall_f                (stall_f),
   7.761 +    .stall_d                (stall_d),
   7.762 +    .stall_x                (stall_x),
   7.763 +    .stall_m                (stall_m),
   7.764 +    .valid_f                (valid_f),
   7.765 +    .valid_d                (valid_d),
   7.766 +    .kill_f                 (kill_f),
   7.767 +    .branch_predict_taken_d (branch_predict_taken_d),
   7.768 +    .branch_predict_address_d (branch_predict_address_d),
   7.769 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   7.770 +    .branch_taken_x         (branch_taken_x),
   7.771 +    .branch_target_x        (branch_target_x),
   7.772 +`endif
   7.773 +    .exception_m            (exception_m),
   7.774 +    .branch_taken_m         (branch_taken_m),
   7.775 +    .branch_mispredict_taken_m (branch_mispredict_taken_m),
   7.776 +    .branch_target_m        (branch_target_m),
   7.777 +`ifdef CFG_ICACHE_ENABLED
   7.778 +    .iflush                 (iflush),
   7.779 +`endif
   7.780 +`ifdef CFG_IROM_ENABLED
   7.781 +    .irom_store_data_m      (irom_store_data_m),
   7.782 +    .irom_address_xm        (irom_address_xm),
   7.783 +    .irom_we_xm             (irom_we_xm),
   7.784 +`endif
   7.785 +`ifdef CFG_DCACHE_ENABLED
   7.786 +    .dcache_restart_request (dcache_restart_request),
   7.787 +    .dcache_refill_request  (dcache_refill_request),
   7.788 +    .dcache_refilling       (dcache_refilling),
   7.789 +`endif        
   7.790 +`ifdef CFG_IWB_ENABLED
   7.791 +    // From Wishbone
   7.792 +    .i_dat_i                (I_DAT_I),
   7.793 +    .i_ack_i                (I_ACK_I),
   7.794 +    .i_err_i                (I_ERR_I),
   7.795 +    .i_rty_i                (I_RTY_I),
   7.796 +`endif
   7.797 +`ifdef CFG_HW_DEBUG_ENABLED
   7.798 +    .jtag_read_enable       (jtag_read_enable),
   7.799 +    .jtag_write_enable      (jtag_write_enable),
   7.800 +    .jtag_write_data        (jtag_write_data),
   7.801 +    .jtag_address           (jtag_address),
   7.802 +`endif
   7.803 +    // ----- Outputs -------
   7.804 +    // To pipeline
   7.805 +    .pc_f                   (pc_f),
   7.806 +    .pc_d                   (pc_d),
   7.807 +    .pc_x                   (pc_x),
   7.808 +    .pc_m                   (pc_m),
   7.809 +    .pc_w                   (pc_w),
   7.810 +`ifdef CFG_ICACHE_ENABLED
   7.811 +    .icache_stall_request   (icache_stall_request),
   7.812 +    .icache_restart_request (icache_restart_request),
   7.813 +    .icache_refill_request  (icache_refill_request),
   7.814 +    .icache_refilling       (icache_refilling),
   7.815 +`endif
   7.816 +`ifdef CFG_IROM_ENABLED
   7.817 +    .irom_data_m            (irom_data_m),
   7.818 +`endif
   7.819 +`ifdef CFG_IWB_ENABLED
   7.820 +    // To Wishbone
   7.821 +    .i_dat_o                (I_DAT_O),
   7.822 +    .i_adr_o                (I_ADR_O),
   7.823 +    .i_cyc_o                (I_CYC_O),
   7.824 +    .i_sel_o                (I_SEL_O),
   7.825 +    .i_stb_o                (I_STB_O),
   7.826 +    .i_we_o                 (I_WE_O),
   7.827 +    .i_cti_o                (I_CTI_O),
   7.828 +    .i_lock_o               (I_LOCK_O),
   7.829 +    .i_bte_o                (I_BTE_O),
   7.830 +`endif
   7.831 +`ifdef CFG_HW_DEBUG_ENABLED
   7.832 +    .jtag_read_data         (jtag_read_data),
   7.833 +    .jtag_access_complete   (jtag_access_complete),
   7.834 +`endif
   7.835 +`ifdef CFG_BUS_ERRORS_ENABLED
   7.836 +    .bus_error_d            (bus_error_d),
   7.837 +`endif
   7.838 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   7.839 +    .instruction_f          (instruction_f),
   7.840 +`endif
   7.841 +    .instruction_d          (instruction_d)
   7.842 +    );
   7.843 +
   7.844 +// Instruction decoder
   7.845 +lm32_decoder decoder (
   7.846 +    // ----- Inputs -------
   7.847 +    .instruction            (instruction_d),
   7.848 +    // ----- Outputs -------
   7.849 +    .d_result_sel_0         (d_result_sel_0_d),
   7.850 +    .d_result_sel_1         (d_result_sel_1_d),
   7.851 +    .x_result_sel_csr       (x_result_sel_csr_d),
   7.852 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   7.853 +    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
   7.854 +`endif
   7.855 +`ifdef LM32_NO_BARREL_SHIFT    
   7.856 +    .x_result_sel_shift     (x_result_sel_shift_d),
   7.857 +`endif
   7.858 +`ifdef CFG_SIGN_EXTEND_ENABLED
   7.859 +    .x_result_sel_sext      (x_result_sel_sext_d),
   7.860 +`endif    
   7.861 +    .x_result_sel_logic     (x_result_sel_logic_d),
   7.862 +`ifdef CFG_USER_ENABLED
   7.863 +    .x_result_sel_user      (x_result_sel_user_d),
   7.864 +`endif
   7.865 +    .x_result_sel_add       (x_result_sel_add_d),
   7.866 +    .m_result_sel_compare   (m_result_sel_compare_d),
   7.867 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.868 +    .m_result_sel_shift     (m_result_sel_shift_d),  
   7.869 +`endif    
   7.870 +    .w_result_sel_load      (w_result_sel_load_d),
   7.871 +`ifdef CFG_PL_MULTIPLY_ENABLED
   7.872 +    .w_result_sel_mul       (w_result_sel_mul_d),
   7.873 +`endif
   7.874 +    .x_bypass_enable        (x_bypass_enable_d),
   7.875 +    .m_bypass_enable        (m_bypass_enable_d),
   7.876 +    .read_enable_0          (read_enable_0_d),
   7.877 +    .read_idx_0             (read_idx_0_d),
   7.878 +    .read_enable_1          (read_enable_1_d),
   7.879 +    .read_idx_1             (read_idx_1_d),
   7.880 +    .write_enable           (write_enable_d),
   7.881 +    .write_idx              (write_idx_d),
   7.882 +    .immediate              (immediate_d),
   7.883 +    .branch_offset          (branch_offset_d),
   7.884 +    .load                   (load_d),
   7.885 +    .store                  (store_d),
   7.886 +    .size                   (size_d),
   7.887 +    .sign_extend            (sign_extend_d),
   7.888 +    .adder_op               (adder_op_d),
   7.889 +    .logic_op               (logic_op_d),
   7.890 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   7.891 +    .direction              (direction_d),
   7.892 +`endif
   7.893 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   7.894 +    .shift_left             (shift_left_d),
   7.895 +    .shift_right            (shift_right_d),
   7.896 +`endif
   7.897 +`ifdef CFG_MC_MULTIPLY_ENABLED
   7.898 +    .multiply               (multiply_d),
   7.899 +`endif
   7.900 +`ifdef CFG_MC_DIVIDE_ENABLED
   7.901 +    .divide                 (divide_d),
   7.902 +    .modulus                (modulus_d),
   7.903 +`endif
   7.904 +    .branch                 (branch_d),
   7.905 +    .bi_unconditional       (bi_unconditional),
   7.906 +    .bi_conditional         (bi_conditional),
   7.907 +    .branch_reg             (branch_reg_d),
   7.908 +    .condition              (condition_d),
   7.909 +`ifdef CFG_DEBUG_ENABLED
   7.910 +    .break_opcode           (break_d),
   7.911 +`endif
   7.912 +    .scall                  (scall_d),
   7.913 +    .eret                   (eret_d),
   7.914 +`ifdef CFG_DEBUG_ENABLED
   7.915 +    .bret                   (bret_d),
   7.916 +`endif
   7.917 +`ifdef CFG_USER_ENABLED
   7.918 +    .user_opcode            (user_opcode_d),
   7.919 +`endif
   7.920 +    .csr_write_enable       (csr_write_enable_d)
   7.921 +    ); 
   7.922 +
   7.923 +// Load/store unit       
   7.924 +lm32_load_store_unit #(
   7.925 +    .associativity          (dcache_associativity),
   7.926 +    .sets                   (dcache_sets),
   7.927 +    .bytes_per_line         (dcache_bytes_per_line),
   7.928 +    .base_address           (dcache_base_address),
   7.929 +    .limit                  (dcache_limit)
   7.930 +  ) load_store_unit (
   7.931 +    // ----- Inputs -------
   7.932 +    .clk_i                  (clk_i),
   7.933 +    .rst_i                  (rst_i),
   7.934 +    // From pipeline
   7.935 +    .stall_a                (stall_a),
   7.936 +    .stall_x                (stall_x),
   7.937 +    .stall_m                (stall_m),
   7.938 +    .kill_x                 (kill_x),
   7.939 +    .kill_m                 (kill_m),
   7.940 +    .exception_m            (exception_m),
   7.941 +    .store_operand_x        (store_operand_x),
   7.942 +    .load_store_address_x   (adder_result_x),
   7.943 +    .load_store_address_m   (operand_m),
   7.944 +    .load_store_address_w   (operand_w[1:0]),
   7.945 +    .load_x                 (load_x),
   7.946 +    .store_x                (store_x),
   7.947 +    .load_q_x               (load_q_x),
   7.948 +    .store_q_x              (store_q_x),
   7.949 +    .load_q_m               (load_q_m),
   7.950 +    .store_q_m              (store_q_m),
   7.951 +    .sign_extend_x          (sign_extend_x),
   7.952 +    .size_x                 (size_x),
   7.953 +`ifdef CFG_DCACHE_ENABLED
   7.954 +    .dflush                 (dflush_m),
   7.955 +`endif
   7.956 +`ifdef CFG_IROM_ENABLED
   7.957 +    .irom_data_m            (irom_data_m),
   7.958 +`endif
   7.959 +    // From Wishbone
   7.960 +    .d_dat_i                (D_DAT_I),
   7.961 +    .d_ack_i                (D_ACK_I),
   7.962 +    .d_err_i                (D_ERR_I),
   7.963 +    .d_rty_i                (D_RTY_I),
   7.964 +    // ----- Outputs -------
   7.965 +    // To pipeline
   7.966 +`ifdef CFG_DCACHE_ENABLED
   7.967 +    .dcache_refill_request  (dcache_refill_request),
   7.968 +    .dcache_restart_request (dcache_restart_request),
   7.969 +    .dcache_stall_request   (dcache_stall_request),
   7.970 +    .dcache_refilling       (dcache_refilling),
   7.971 +`endif    
   7.972 +`ifdef CFG_IROM_ENABLED
   7.973 +    .irom_store_data_m      (irom_store_data_m),
   7.974 +    .irom_address_xm        (irom_address_xm),
   7.975 +    .irom_we_xm             (irom_we_xm),
   7.976 +    .irom_stall_request_x   (irom_stall_request_x),
   7.977 +`endif
   7.978 +    .load_data_w            (load_data_w),
   7.979 +    .stall_wb_load          (stall_wb_load),
   7.980 +    // To Wishbone
   7.981 +    .d_dat_o                (D_DAT_O),
   7.982 +    .d_adr_o                (D_ADR_O),
   7.983 +    .d_cyc_o                (D_CYC_O),
   7.984 +    .d_sel_o                (D_SEL_O),
   7.985 +    .d_stb_o                (D_STB_O),
   7.986 +    .d_we_o                 (D_WE_O),
   7.987 +    .d_cti_o                (D_CTI_O),
   7.988 +    .d_lock_o               (D_LOCK_O),
   7.989 +    .d_bte_o                (D_BTE_O)
   7.990 +    );      
   7.991 +       
   7.992 +// Adder       
   7.993 +lm32_adder adder (
   7.994 +    // ----- Inputs -------
   7.995 +    .adder_op_x             (adder_op_x),
   7.996 +    .adder_op_x_n           (adder_op_x_n),
   7.997 +    .operand_0_x            (operand_0_x),
   7.998 +    .operand_1_x            (operand_1_x),
   7.999 +    // ----- Outputs -------
  7.1000 +    .adder_result_x         (adder_result_x),
  7.1001 +    .adder_carry_n_x        (adder_carry_n_x),
  7.1002 +    .adder_overflow_x       (adder_overflow_x)
  7.1003 +    );
  7.1004 +
  7.1005 +// Logic operations
  7.1006 +lm32_logic_op logic_op (
  7.1007 +    // ----- Inputs -------
  7.1008 +    .logic_op_x             (logic_op_x),
  7.1009 +    .operand_0_x            (operand_0_x),
  7.1010 +
  7.1011 +    .operand_1_x            (operand_1_x),
  7.1012 +    // ----- Outputs -------
  7.1013 +    .logic_result_x         (logic_result_x)
  7.1014 +    );
  7.1015 +              
  7.1016 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.1017 +// Pipelined barrel-shifter
  7.1018 +lm32_shifter shifter (
  7.1019 +    // ----- Inputs -------
  7.1020 +    .clk_i                  (clk_i),
  7.1021 +    .rst_i                  (rst_i),
  7.1022 +    .stall_x                (stall_x),
  7.1023 +    .direction_x            (direction_x),
  7.1024 +    .sign_extend_x          (sign_extend_x),
  7.1025 +    .operand_0_x            (operand_0_x),
  7.1026 +    .operand_1_x            (operand_1_x),
  7.1027 +    // ----- Outputs -------
  7.1028 +    .shifter_result_m       (shifter_result_m)
  7.1029 +    );
  7.1030 +`endif
  7.1031 +
  7.1032 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.1033 +// Pipeline fixed-point multiplier
  7.1034 +lm32_multiplier multiplier (
  7.1035 +    // ----- Inputs -------
  7.1036 +    .clk_i                  (clk_i),
  7.1037 +    .rst_i                  (rst_i),
  7.1038 +    .stall_x                (stall_x),
  7.1039 +    .stall_m                (stall_m),
  7.1040 +    .operand_0              (d_result_0),
  7.1041 +    .operand_1              (d_result_1),
  7.1042 +    // ----- Outputs -------
  7.1043 +    .result                 (multiplier_result_w)    
  7.1044 +    );
  7.1045 +`endif
  7.1046 +
  7.1047 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1048 +// Multi-cycle arithmetic
  7.1049 +lm32_mc_arithmetic mc_arithmetic (
  7.1050 +    // ----- Inputs -------
  7.1051 +    .clk_i                  (clk_i),
  7.1052 +    .rst_i                  (rst_i),
  7.1053 +    .stall_d                (stall_d),
  7.1054 +    .kill_x                 (kill_x),
  7.1055 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  7.1056 +    .divide_d               (divide_q_d),
  7.1057 +    .modulus_d              (modulus_q_d),
  7.1058 +`endif
  7.1059 +`ifdef CFG_MC_MULTIPLY_ENABLED        
  7.1060 +    .multiply_d             (multiply_q_d),
  7.1061 +`endif
  7.1062 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  7.1063 +    .shift_left_d           (shift_left_q_d),
  7.1064 +    .shift_right_d          (shift_right_q_d),
  7.1065 +    .sign_extend_d          (sign_extend_d),
  7.1066 +`endif    
  7.1067 +    .operand_0_d            (d_result_0),
  7.1068 +    .operand_1_d            (d_result_1),
  7.1069 +    // ----- Outputs -------
  7.1070 +    .result_x               (mc_result_x),
  7.1071 +`ifdef CFG_MC_DIVIDE_ENABLED                  
  7.1072 +    .divide_by_zero_x       (divide_by_zero_x),
  7.1073 +`endif
  7.1074 +    .stall_request_x        (mc_stall_request_x)
  7.1075 +    );
  7.1076 +`endif
  7.1077 +              
  7.1078 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1079 +// Interrupt unit
  7.1080 +lm32_interrupt interrupt (
  7.1081 +    // ----- Inputs -------
  7.1082 +    .clk_i                  (clk_i), 
  7.1083 +    .rst_i                  (rst_i),
  7.1084 +    // From external devices
  7.1085 +    .interrupt_n            (interrupt_n),
  7.1086 +    // From pipeline
  7.1087 +    .stall_x                (stall_x),
  7.1088 +`ifdef CFG_DEBUG_ENABLED
  7.1089 +    .non_debug_exception    (non_debug_exception_q_w), 
  7.1090 +    .debug_exception        (debug_exception_q_w),
  7.1091 +`else
  7.1092 +    .exception              (exception_q_w), 
  7.1093 +`endif
  7.1094 +    .eret_q_x               (eret_q_x),
  7.1095 +`ifdef CFG_DEBUG_ENABLED
  7.1096 +    .bret_q_x               (bret_q_x),
  7.1097 +`endif
  7.1098 +    .csr                    (csr_x),
  7.1099 +    .csr_write_data         (operand_1_x),
  7.1100 +    .csr_write_enable       (csr_write_enable_q_x),
  7.1101 +    // ----- Outputs -------
  7.1102 +    .interrupt_exception    (interrupt_exception),
  7.1103 +    // To pipeline
  7.1104 +    .csr_read_data          (interrupt_csr_read_data_x)
  7.1105 +    );
  7.1106 +`endif
  7.1107 +
  7.1108 +`ifdef CFG_JTAG_ENABLED
  7.1109 +// JTAG interface
  7.1110 +lm32_jtag jtag (
  7.1111 +    // ----- Inputs -------
  7.1112 +    .clk_i                  (clk_i),
  7.1113 +    .rst_i                  (rst_i),
  7.1114 +    // From JTAG
  7.1115 +    .jtag_clk               (jtag_clk),
  7.1116 +    .jtag_update            (jtag_update),
  7.1117 +    .jtag_reg_q             (jtag_reg_q),
  7.1118 +    .jtag_reg_addr_q        (jtag_reg_addr_q),
  7.1119 +    // From pipeline
  7.1120 +`ifdef CFG_JTAG_UART_ENABLED
  7.1121 +    .csr                    (csr_x),
  7.1122 +    .csr_write_data         (operand_1_x),
  7.1123 +    .csr_write_enable       (csr_write_enable_q_x),
  7.1124 +    .stall_x                (stall_x),
  7.1125 +`endif
  7.1126 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1127 +    .jtag_read_data         (jtag_read_data),
  7.1128 +    .jtag_access_complete   (jtag_access_complete),
  7.1129 +`endif
  7.1130 +`ifdef CFG_DEBUG_ENABLED
  7.1131 +    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
  7.1132 +`endif    
  7.1133 +    // ----- Outputs -------
  7.1134 +    // To pipeline
  7.1135 +`ifdef CFG_JTAG_UART_ENABLED
  7.1136 +    .jtx_csr_read_data      (jtx_csr_read_data),
  7.1137 +    .jrx_csr_read_data      (jrx_csr_read_data),
  7.1138 +`endif
  7.1139 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1140 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  7.1141 +    .jtag_csr_write_data    (jtag_csr_write_data),
  7.1142 +    .jtag_csr               (jtag_csr),
  7.1143 +    .jtag_read_enable       (jtag_read_enable),
  7.1144 +    .jtag_write_enable      (jtag_write_enable),
  7.1145 +    .jtag_write_data        (jtag_write_data),
  7.1146 +    .jtag_address           (jtag_address),
  7.1147 +`endif
  7.1148 +`ifdef CFG_DEBUG_ENABLED
  7.1149 +    .jtag_break             (jtag_break),
  7.1150 +    .jtag_reset             (reset_exception),
  7.1151 +`endif
  7.1152 +    // To JTAG 
  7.1153 +    .jtag_reg_d             (jtag_reg_d),
  7.1154 +    .jtag_reg_addr_d        (jtag_reg_addr_d)
  7.1155 +    );
  7.1156 +`endif
  7.1157 +
  7.1158 +`ifdef CFG_DEBUG_ENABLED
  7.1159 +// Debug unit
  7.1160 +lm32_debug #(
  7.1161 +    .breakpoints            (breakpoints),
  7.1162 +    .watchpoints            (watchpoints)
  7.1163 +  ) hw_debug (
  7.1164 +    // ----- Inputs -------
  7.1165 +    .clk_i                  (clk_i), 
  7.1166 +    .rst_i                  (rst_i),
  7.1167 +    .pc_x                   (pc_x),
  7.1168 +    .load_x                 (load_x),
  7.1169 +    .store_x                (store_x),
  7.1170 +    .load_store_address_x   (adder_result_x),
  7.1171 +    .csr_write_enable_x     (csr_write_enable_q_x),
  7.1172 +    .csr_write_data         (operand_1_x),
  7.1173 +    .csr_x                  (csr_x),
  7.1174 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1175 +    .jtag_csr_write_enable  (jtag_csr_write_enable),
  7.1176 +    .jtag_csr_write_data    (jtag_csr_write_data),
  7.1177 +    .jtag_csr               (jtag_csr),
  7.1178 +`endif
  7.1179 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1180 +    .eret_q_x               (eret_q_x),
  7.1181 +    .bret_q_x               (bret_q_x),
  7.1182 +    .stall_x                (stall_x),
  7.1183 +    .exception_x            (exception_x),
  7.1184 +    .q_x                    (q_x),
  7.1185 +`ifdef CFG_DCACHE_ENABLED
  7.1186 +    .dcache_refill_request  (dcache_refill_request),
  7.1187 +`endif
  7.1188 +`endif
  7.1189 +    // ----- Outputs -------
  7.1190 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1191 +    .dc_ss                  (dc_ss),
  7.1192 +`endif
  7.1193 +    .dc_re                  (dc_re),
  7.1194 +    .bp_match               (bp_match),
  7.1195 +    .wp_match               (wp_match)
  7.1196 +    );
  7.1197 +`endif
  7.1198 +
  7.1199 +// Register file
  7.1200 +
  7.1201 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.1202 +   /*----------------------------------------------------------------------
  7.1203 +    Register File is implemented using EBRs. There can be three accesses to
  7.1204 +    the register file in each cycle: two reads and one write. On-chip block
  7.1205 +    RAM has two read/write ports. To accomodate three accesses, two on-chip
  7.1206 +    block RAMs are used (each register file "write" is made to both block
  7.1207 +    RAMs).
  7.1208 +    
  7.1209 +    One limitation of the on-chip block RAMs is that one cannot perform a 
  7.1210 +    read and write to same location in a cycle (if this is done, then the
  7.1211 +    data read out is indeterminate).
  7.1212 +    ----------------------------------------------------------------------*/
  7.1213 +   wire [31:0] regfile_data_0, regfile_data_1;
  7.1214 +   reg [31:0]  w_result_d;
  7.1215 +   reg 	       regfile_raw_0, regfile_raw_0_nxt;
  7.1216 +   reg 	       regfile_raw_1, regfile_raw_1_nxt;
  7.1217 +   
  7.1218 +   /*----------------------------------------------------------------------
  7.1219 +    Check if read and write is being performed to same register in current 
  7.1220 +    cycle? This is done by comparing the read and write IDXs.
  7.1221 +    ----------------------------------------------------------------------*/
  7.1222 +   always @(reg_write_enable_q_w or write_idx_w or instruction_f)
  7.1223 +     begin
  7.1224 +	if (reg_write_enable_q_w
  7.1225 +	    && (write_idx_w == instruction_f[25:21]))
  7.1226 +	  regfile_raw_0_nxt = 1'b1;
  7.1227 +	else
  7.1228 +	  regfile_raw_0_nxt = 1'b0;
  7.1229 +	
  7.1230 +	if (reg_write_enable_q_w
  7.1231 +	    && (write_idx_w == instruction_f[20:16]))
  7.1232 +	  regfile_raw_1_nxt = 1'b1;
  7.1233 +	else
  7.1234 +	  regfile_raw_1_nxt = 1'b0;
  7.1235 +     end
  7.1236 +   
  7.1237 +   /*----------------------------------------------------------------------
  7.1238 +    Select latched (delayed) write value or data from register file. If 
  7.1239 +    read in previous cycle was performed to register written to in same
  7.1240 +    cycle, then latched (delayed) write value is selected.
  7.1241 +    ----------------------------------------------------------------------*/
  7.1242 +   always @(regfile_raw_0 or w_result_d or regfile_data_0)
  7.1243 +     if (regfile_raw_0)
  7.1244 +       reg_data_live_0 = w_result_d;
  7.1245 +     else
  7.1246 +       reg_data_live_0 = regfile_data_0;
  7.1247 +   
  7.1248 +   /*----------------------------------------------------------------------
  7.1249 +    Select latched (delayed) write value or data from register file. If 
  7.1250 +    read in previous cycle was performed to register written to in same
  7.1251 +    cycle, then latched (delayed) write value is selected.
  7.1252 +    ----------------------------------------------------------------------*/
  7.1253 +   always @(regfile_raw_1 or w_result_d or regfile_data_1)
  7.1254 +     if (regfile_raw_1)
  7.1255 +       reg_data_live_1 = w_result_d;
  7.1256 +     else
  7.1257 +       reg_data_live_1 = regfile_data_1;
  7.1258 +   
  7.1259 +   /*----------------------------------------------------------------------
  7.1260 +    Latch value written to register file
  7.1261 +    ----------------------------------------------------------------------*/
  7.1262 +   always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.1263 +     if (rst_i == `TRUE)
  7.1264 +       begin
  7.1265 +	  regfile_raw_0 <= 1'b0;
  7.1266 +	  regfile_raw_1 <= 1'b0;
  7.1267 +	  w_result_d <= 32'b0;
  7.1268 +       end
  7.1269 +     else
  7.1270 +       begin
  7.1271 +	  regfile_raw_0 <= regfile_raw_0_nxt;
  7.1272 +	  regfile_raw_1 <= regfile_raw_1_nxt;
  7.1273 +	  w_result_d <= w_result;
  7.1274 +       end
  7.1275 +   
  7.1276 +   /*----------------------------------------------------------------------
  7.1277 +    Register file instantiation as Pseudo-Dual Port EBRs.
  7.1278 +    ----------------------------------------------------------------------*/
  7.1279 +   pmi_ram_dp
  7.1280 +     #(
  7.1281 +       // ----- Parameters -----
  7.1282 +       .pmi_wr_addr_depth(1<<5),
  7.1283 +       .pmi_wr_addr_width(5),
  7.1284 +       .pmi_wr_data_width(32),
  7.1285 +       .pmi_rd_addr_depth(1<<5),
  7.1286 +       .pmi_rd_addr_width(5),
  7.1287 +       .pmi_rd_data_width(32),
  7.1288 +       .pmi_regmode("noreg"),
  7.1289 +       .pmi_gsr("enable"),
  7.1290 +       .pmi_resetmode("sync"),
  7.1291 +       .pmi_init_file("none"),
  7.1292 +       .pmi_init_file_format("binary"),
  7.1293 +       .pmi_family(`LATTICE_FAMILY),
  7.1294 +       .module_type("pmi_ram_dp")
  7.1295 +       )
  7.1296 +   reg_0
  7.1297 +     (
  7.1298 +      // ----- Inputs -----
  7.1299 +      .Data(w_result),
  7.1300 +      .WrAddress(write_idx_w),
  7.1301 +      .RdAddress(instruction_f[25:21]),
  7.1302 +      .WrClock(clk_i),
  7.1303 +      .RdClock(clk_i),
  7.1304 +      .WrClockEn(`TRUE),
  7.1305 +      .RdClockEn(`TRUE),
  7.1306 +      .WE(reg_write_enable_q_w),
  7.1307 +      .Reset(rst_i), 
  7.1308 +      // ----- Outputs -----
  7.1309 +      .Q(regfile_data_0)
  7.1310 +      );
  7.1311 +
  7.1312 +   pmi_ram_dp
  7.1313 +     #(
  7.1314 +       // ----- Parameters -----
  7.1315 +       .pmi_wr_addr_depth(1<<5),
  7.1316 +       .pmi_wr_addr_width(5),
  7.1317 +       .pmi_wr_data_width(32),
  7.1318 +       .pmi_rd_addr_depth(1<<5),
  7.1319 +       .pmi_rd_addr_width(5),
  7.1320 +       .pmi_rd_data_width(32),
  7.1321 +       .pmi_regmode("noreg"),
  7.1322 +       .pmi_gsr("enable"),
  7.1323 +       .pmi_resetmode("sync"),
  7.1324 +       .pmi_init_file("none"),
  7.1325 +       .pmi_init_file_format("binary"),
  7.1326 +       .pmi_family(`LATTICE_FAMILY),
  7.1327 +       .module_type("pmi_ram_dp")
  7.1328 +       )
  7.1329 +   reg_1
  7.1330 +     (
  7.1331 +      // ----- Inputs -----
  7.1332 +      .Data(w_result),
  7.1333 +      .WrAddress(write_idx_w),
  7.1334 +      .RdAddress(instruction_f[20:16]),
  7.1335 +      .WrClock(clk_i),
  7.1336 +      .RdClock(clk_i),
  7.1337 +      .WrClockEn(`TRUE),
  7.1338 +      .RdClockEn(`TRUE),
  7.1339 +      .WE(reg_write_enable_q_w),
  7.1340 +      .Reset(rst_i), 
  7.1341 +      // ----- Outputs -----
  7.1342 +      .Q(regfile_data_1)
  7.1343 +      );
  7.1344 +`endif
  7.1345 +
  7.1346 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  7.1347 +   pmi_ram_dp
  7.1348 +     #(
  7.1349 +       // ----- Parameters -----
  7.1350 +       .pmi_wr_addr_depth(1<<5),
  7.1351 +       .pmi_wr_addr_width(5),
  7.1352 +       .pmi_wr_data_width(32),
  7.1353 +       .pmi_rd_addr_depth(1<<5),
  7.1354 +       .pmi_rd_addr_width(5),
  7.1355 +       .pmi_rd_data_width(32),
  7.1356 +       .pmi_regmode("noreg"),
  7.1357 +       .pmi_gsr("enable"),
  7.1358 +       .pmi_resetmode("sync"),
  7.1359 +       .pmi_init_file("none"),
  7.1360 +       .pmi_init_file_format("binary"),
  7.1361 +       .pmi_family(`LATTICE_FAMILY),
  7.1362 +       .module_type("pmi_ram_dp")
  7.1363 +       )
  7.1364 +   reg_0
  7.1365 +     (
  7.1366 +      // ----- Inputs -----
  7.1367 +      .Data(w_result),
  7.1368 +      .WrAddress(write_idx_w),
  7.1369 +      .RdAddress(read_idx_0_d),
  7.1370 +      .WrClock(clk_i),
  7.1371 +      .RdClock(clk_n_i),
  7.1372 +      .WrClockEn(`TRUE),
  7.1373 +      .RdClockEn(stall_f == `FALSE),
  7.1374 +      .WE(reg_write_enable_q_w),
  7.1375 +      .Reset(rst_i), 
  7.1376 +      // ----- Outputs -----
  7.1377 +      .Q(reg_data_0)
  7.1378 +      );
  7.1379 +   
  7.1380 +   pmi_ram_dp
  7.1381 +     #(
  7.1382 +       // ----- Parameters -----
  7.1383 +       .pmi_wr_addr_depth(1<<5),
  7.1384 +       .pmi_wr_addr_width(5),
  7.1385 +       .pmi_wr_data_width(32),
  7.1386 +       .pmi_rd_addr_depth(1<<5),
  7.1387 +       .pmi_rd_addr_width(5),
  7.1388 +       .pmi_rd_data_width(32),
  7.1389 +       .pmi_regmode("noreg"),
  7.1390 +       .pmi_gsr("enable"),
  7.1391 +       .pmi_resetmode("sync"),
  7.1392 +       .pmi_init_file("none"),
  7.1393 +       .pmi_init_file_format("binary"),
  7.1394 +       .pmi_family(`LATTICE_FAMILY),
  7.1395 +       .module_type("pmi_ram_dp")
  7.1396 +       )
  7.1397 +   reg_1
  7.1398 +     (
  7.1399 +      // ----- Inputs -----
  7.1400 +      .Data(w_result),
  7.1401 +      .WrAddress(write_idx_w),
  7.1402 +      .RdAddress(read_idx_1_d),
  7.1403 +      .WrClock(clk_i),
  7.1404 +      .RdClock(clk_n_i),
  7.1405 +      .WrClockEn(`TRUE),
  7.1406 +      .RdClockEn(stall_f == `FALSE),
  7.1407 +      .WE(reg_write_enable_q_w),
  7.1408 +      .Reset(rst_i), 
  7.1409 +      // ----- Outputs -----
  7.1410 +      .Q(reg_data_1)
  7.1411 +      );
  7.1412 +`endif
  7.1413 +
  7.1414 +
  7.1415 +/////////////////////////////////////////////////////
  7.1416 +// Combinational Logic
  7.1417 +/////////////////////////////////////////////////////
  7.1418 +
  7.1419 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.1420 +// Select between buffered and live data from register file
  7.1421 +assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
  7.1422 +assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
  7.1423 +`endif
  7.1424 +`ifdef LM32_EBR_REGISTER_FILE
  7.1425 +`else
  7.1426 +// Register file read ports
  7.1427 +assign reg_data_0 = registers[read_idx_0_d];
  7.1428 +assign reg_data_1 = registers[read_idx_1_d];
  7.1429 +`endif
  7.1430 +
  7.1431 +// Detect read-after-write hazzards
  7.1432 +assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
  7.1433 +assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
  7.1434 +assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
  7.1435 +assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
  7.1436 +assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
  7.1437 +assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
  7.1438 +
  7.1439 +// Interlock detection - Raise an interlock for RAW hazzards 
  7.1440 +always @(*)
  7.1441 +begin
  7.1442 +    if (   (   (x_bypass_enable_x == `FALSE)
  7.1443 +            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
  7.1444 +                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
  7.1445 +               )
  7.1446 +           )
  7.1447 +        || (   (m_bypass_enable_m == `FALSE)
  7.1448 +            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
  7.1449 +                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
  7.1450 +               )
  7.1451 +           )
  7.1452 +       )
  7.1453 +        interlock = `TRUE;
  7.1454 +    else
  7.1455 +        interlock = `FALSE;
  7.1456 +end
  7.1457 +
  7.1458 +// Bypass for reg port 0
  7.1459 +always @(*)
  7.1460 +begin
  7.1461 +    if (raw_x_0 == `TRUE)        
  7.1462 +        bypass_data_0 = x_result;
  7.1463 +    else if (raw_m_0 == `TRUE)
  7.1464 +        bypass_data_0 = m_result;
  7.1465 +    else if (raw_w_0 == `TRUE)
  7.1466 +        bypass_data_0 = w_result;
  7.1467 +    else
  7.1468 +        bypass_data_0 = reg_data_0;
  7.1469 +end
  7.1470 +
  7.1471 +// Bypass for reg port 1
  7.1472 +always @(*)
  7.1473 +begin
  7.1474 +    if (raw_x_1 == `TRUE)
  7.1475 +        bypass_data_1 = x_result;
  7.1476 +    else if (raw_m_1 == `TRUE)
  7.1477 +        bypass_data_1 = m_result;
  7.1478 +    else if (raw_w_1 == `TRUE)
  7.1479 +        bypass_data_1 = w_result;
  7.1480 +    else
  7.1481 +        bypass_data_1 = reg_data_1;
  7.1482 +end
  7.1483 +
  7.1484 +   /*----------------------------------------------------------------------
  7.1485 +    Branch prediction is performed in D stage of pipeline. Only PC-relative
  7.1486 +    branches are predicted: forward-pointing conditional branches are not-
  7.1487 +    taken, while backward-pointing conditional branches are taken. 
  7.1488 +    Unconditional branches are always predicted taken!
  7.1489 +    ----------------------------------------------------------------------*/
  7.1490 +   assign branch_predict_d = bi_unconditional | bi_conditional;
  7.1491 +   assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
  7.1492 +   
  7.1493 +   // Compute branch target address: Branch PC PLUS Offset
  7.1494 +   assign branch_target_d = pc_d + branch_offset_d;
  7.1495 +
  7.1496 +   // Compute fetch address. Address of instruction sequentially after the
  7.1497 +   // branch if branch is not taken. Target address of branch is branch is
  7.1498 +   // taken
  7.1499 +   assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
  7.1500 +
  7.1501 +// D stage result selection
  7.1502 +always @(*)
  7.1503 +begin
  7.1504 +    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
  7.1505 +    case (d_result_sel_1_d)
  7.1506 +    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
  7.1507 +    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
  7.1508 +    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
  7.1509 +    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
  7.1510 +    endcase
  7.1511 +end
  7.1512 +
  7.1513 +`ifdef CFG_USER_ENABLED    
  7.1514 +// Operands for user-defined instructions
  7.1515 +assign user_operand_0 = operand_0_x;
  7.1516 +assign user_operand_1 = operand_1_x;
  7.1517 +`endif
  7.1518 +
  7.1519 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.1520 +// Sign-extension
  7.1521 +assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
  7.1522 +assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
  7.1523 +assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
  7.1524 +`endif
  7.1525 +
  7.1526 +`ifdef LM32_NO_BARREL_SHIFT
  7.1527 +// Only single bit shift operations are supported when barrel-shifter isn't implemented
  7.1528 +assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
  7.1529 +`endif
  7.1530 +
  7.1531 +// Condition evaluation
  7.1532 +assign cmp_zero = operand_0_x == operand_1_x;
  7.1533 +assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
  7.1534 +assign cmp_overflow = adder_overflow_x;
  7.1535 +assign cmp_carry_n = adder_carry_n_x;
  7.1536 +always @(*)
  7.1537 +begin
  7.1538 +    case (condition_x)
  7.1539 +    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
  7.1540 +    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
  7.1541 +    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
  7.1542 +    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
  7.1543 +    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
  7.1544 +    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
  7.1545 +    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
  7.1546 +    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
  7.1547 +    default:              condition_met_x = 1'bx;
  7.1548 +    endcase 
  7.1549 +end
  7.1550 +
  7.1551 +// X stage result selection
  7.1552 +always @(*)
  7.1553 +begin
  7.1554 +    x_result =   x_result_sel_add_x ? adder_result_x 
  7.1555 +               : x_result_sel_csr_x ? csr_read_data_x
  7.1556 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.1557 +               : x_result_sel_sext_x ? sext_result_x
  7.1558 +`endif
  7.1559 +`ifdef CFG_USER_ENABLED
  7.1560 +               : x_result_sel_user_x ? user_result
  7.1561 +`endif
  7.1562 +`ifdef LM32_NO_BARREL_SHIFT
  7.1563 +               : x_result_sel_shift_x ? shifter_result_x
  7.1564 +`endif
  7.1565 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1566 +               : x_result_sel_mc_arith_x ? mc_result_x
  7.1567 +`endif
  7.1568 +               : logic_result_x;
  7.1569 +end
  7.1570 +
  7.1571 +// M stage result selection
  7.1572 +always @(*)
  7.1573 +begin
  7.1574 +    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
  7.1575 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.1576 +               : m_result_sel_shift_m ? shifter_result_m
  7.1577 +`endif
  7.1578 +               : operand_m; 
  7.1579 +end
  7.1580 +
  7.1581 +// W stage result selection
  7.1582 +always @(*)
  7.1583 +begin
  7.1584 +    w_result =    w_result_sel_load_w ? load_data_w
  7.1585 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.1586 +                : w_result_sel_mul_w ? multiplier_result_w
  7.1587 +`endif
  7.1588 +                : operand_w;
  7.1589 +end
  7.1590 +
  7.1591 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1592 +// Indicate when a branch should be taken in X stage
  7.1593 +assign branch_taken_x =      (stall_x == `FALSE)
  7.1594 +                          && (   (branch_x == `TRUE)
  7.1595 +                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
  7.1596 +                              && (valid_x == `TRUE)
  7.1597 +                              && (branch_predict_x == `FALSE)
  7.1598 +                             ); 
  7.1599 +`endif
  7.1600 +
  7.1601 +// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
  7.1602 +assign branch_taken_m =      (stall_m == `FALSE) 
  7.1603 +                          && (   (   (branch_m == `TRUE) 
  7.1604 +                                  && (valid_m == `TRUE)
  7.1605 +                                  && (   (   (condition_met_m == `TRUE)
  7.1606 +					  && (branch_predict_taken_m == `FALSE)
  7.1607 +					 )
  7.1608 +				      || (   (condition_met_m == `FALSE)
  7.1609 +					  && (branch_predict_m == `TRUE)
  7.1610 +					  && (branch_predict_taken_m == `TRUE)
  7.1611 +					 )
  7.1612 +				     )
  7.1613 +                                 ) 
  7.1614 +                              || (exception_m == `TRUE)
  7.1615 +                             );
  7.1616 +
  7.1617 +// Indicate when a branch in M stage is mispredicted as being taken
  7.1618 +assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
  7.1619 +                                   && (branch_predict_m == `TRUE)
  7.1620 +	   			   && (branch_predict_taken_m == `TRUE);
  7.1621 +   
  7.1622 +// Indicate when a branch in M stage will cause flush in X stage
  7.1623 +assign branch_flushX_m =    (stall_m == `FALSE)
  7.1624 +                         && (   (   (branch_m == `TRUE) 
  7.1625 +                                 && (valid_m == `TRUE)
  7.1626 +			         && (   (condition_met_m == `TRUE)
  7.1627 +				     || (   (condition_met_m == `FALSE)
  7.1628 +					 && (branch_predict_m == `TRUE)
  7.1629 +					 && (branch_predict_taken_m == `TRUE)
  7.1630 +					)
  7.1631 +				    )
  7.1632 +			        )
  7.1633 +			     || (exception_m == `TRUE)
  7.1634 +			    );
  7.1635 +
  7.1636 +// Generate signal that will kill instructions in each pipeline stage when necessary
  7.1637 +assign kill_f =    (   (valid_d == `TRUE)
  7.1638 +                    && (branch_predict_taken_d == `TRUE)
  7.1639 +		   )
  7.1640 +                || (branch_taken_m == `TRUE) 
  7.1641 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1642 +                || (branch_taken_x == `TRUE)
  7.1643 +`endif
  7.1644 +`ifdef CFG_ICACHE_ENABLED
  7.1645 +                || (icache_refill_request == `TRUE) 
  7.1646 +`endif
  7.1647 +`ifdef CFG_DCACHE_ENABLED                
  7.1648 +                || (dcache_refill_request == `TRUE)
  7.1649 +`endif
  7.1650 +                ;
  7.1651 +assign kill_d =    (branch_taken_m == `TRUE) 
  7.1652 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.1653 +                || (branch_taken_x == `TRUE)
  7.1654 +`endif
  7.1655 +`ifdef CFG_ICACHE_ENABLED
  7.1656 +                || (icache_refill_request == `TRUE)     
  7.1657 +`endif                
  7.1658 +`ifdef CFG_DCACHE_ENABLED                
  7.1659 +                || (dcache_refill_request == `TRUE)
  7.1660 +`endif
  7.1661 +                ;
  7.1662 +assign kill_x =    (branch_flushX_m == `TRUE) 
  7.1663 +`ifdef CFG_DCACHE_ENABLED                
  7.1664 +                || (dcache_refill_request == `TRUE)
  7.1665 +`endif
  7.1666 +                ;
  7.1667 +assign kill_m =    `FALSE
  7.1668 +`ifdef CFG_DCACHE_ENABLED                
  7.1669 +                || (dcache_refill_request == `TRUE)
  7.1670 +`endif
  7.1671 +                ;                
  7.1672 +assign kill_w =    `FALSE
  7.1673 +`ifdef CFG_DCACHE_ENABLED                
  7.1674 +                || (dcache_refill_request == `TRUE)
  7.1675 +`endif                
  7.1676 +                ;
  7.1677 +
  7.1678 +// Exceptions
  7.1679 +
  7.1680 +`ifdef CFG_DEBUG_ENABLED
  7.1681 +assign breakpoint_exception =    (   (   (break_x == `TRUE)
  7.1682 +				      || (bp_match == `TRUE)
  7.1683 +				     )
  7.1684 +				  && (valid_x == `TRUE)
  7.1685 +				 )
  7.1686 +`ifdef CFG_JTAG_ENABLED
  7.1687 +                              || (jtag_break == `TRUE)
  7.1688 +`endif
  7.1689 +                              ;
  7.1690 +`endif
  7.1691 +
  7.1692 +`ifdef CFG_DEBUG_ENABLED
  7.1693 +assign watchpoint_exception = wp_match == `TRUE;
  7.1694 +`endif
  7.1695 +
  7.1696 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1697 +assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
  7.1698 +                                          && (valid_x == `TRUE)
  7.1699 +                                         );
  7.1700 +assign data_bus_error_exception = data_bus_error_seen == `TRUE;
  7.1701 +`endif
  7.1702 +
  7.1703 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1704 +assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
  7.1705 +`endif
  7.1706 +
  7.1707 +assign system_call_exception = (   (scall_x == `TRUE)
  7.1708 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1709 +                                && (valid_x == `TRUE)
  7.1710 +`endif
  7.1711 +			       );
  7.1712 +
  7.1713 +`ifdef CFG_DEBUG_ENABLED
  7.1714 +assign debug_exception_x =  (breakpoint_exception == `TRUE)
  7.1715 +                         || (watchpoint_exception == `TRUE)
  7.1716 +                         ;
  7.1717 +
  7.1718 +assign non_debug_exception_x = (system_call_exception == `TRUE)
  7.1719 +`ifdef CFG_JTAG_ENABLED
  7.1720 +                            || (reset_exception == `TRUE)
  7.1721 +`endif
  7.1722 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1723 +                            || (instruction_bus_error_exception == `TRUE)
  7.1724 +                            || (data_bus_error_exception == `TRUE)
  7.1725 +`endif
  7.1726 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1727 +                            || (divide_by_zero_exception == `TRUE)
  7.1728 +`endif
  7.1729 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1730 +                            || (   (interrupt_exception == `TRUE)
  7.1731 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1732 +                                && (dc_ss == `FALSE)
  7.1733 +`endif                            
  7.1734 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1735 + 				&& (store_q_m == `FALSE)
  7.1736 +				&& (D_CYC_O == `FALSE)
  7.1737 +`endif
  7.1738 +                               )
  7.1739 +`endif
  7.1740 +                            ;
  7.1741 +
  7.1742 +assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
  7.1743 +`else
  7.1744 +assign exception_x =           (system_call_exception == `TRUE)
  7.1745 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1746 +                            || (instruction_bus_error_exception == `TRUE)
  7.1747 +                            || (data_bus_error_exception == `TRUE)
  7.1748 +`endif
  7.1749 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1750 +                            || (divide_by_zero_exception == `TRUE)
  7.1751 +`endif
  7.1752 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1753 +                            || (   (interrupt_exception == `TRUE)
  7.1754 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1755 +                                && (dc_ss == `FALSE)
  7.1756 +`endif                            
  7.1757 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1758 + 				&& (store_q_m == `FALSE)
  7.1759 +				&& (D_CYC_O == `FALSE)
  7.1760 +`endif
  7.1761 +                               )
  7.1762 +`endif
  7.1763 +                            ;
  7.1764 +`endif
  7.1765 +
  7.1766 +// Exception ID
  7.1767 +always @(*)
  7.1768 +begin
  7.1769 +`ifdef CFG_DEBUG_ENABLED
  7.1770 +`ifdef CFG_JTAG_ENABLED
  7.1771 +    if (reset_exception == `TRUE)
  7.1772 +        eid_x = `LM32_EID_RESET;
  7.1773 +    else
  7.1774 +`endif     
  7.1775 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1776 +         if (data_bus_error_exception == `TRUE)
  7.1777 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  7.1778 +    else
  7.1779 +`endif
  7.1780 +         if (breakpoint_exception == `TRUE)
  7.1781 +        eid_x = `LM32_EID_BREAKPOINT;
  7.1782 +    else
  7.1783 +`endif
  7.1784 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.1785 +         if (data_bus_error_exception == `TRUE)
  7.1786 +        eid_x = `LM32_EID_DATA_BUS_ERROR;
  7.1787 +    else
  7.1788 +         if (instruction_bus_error_exception == `TRUE)
  7.1789 +        eid_x = `LM32_EID_INST_BUS_ERROR;
  7.1790 +    else
  7.1791 +`endif
  7.1792 +`ifdef CFG_DEBUG_ENABLED
  7.1793 +         if (watchpoint_exception == `TRUE)
  7.1794 +        eid_x = `LM32_EID_WATCHPOINT;
  7.1795 +    else 
  7.1796 +`endif
  7.1797 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1798 +         if (divide_by_zero_exception == `TRUE)
  7.1799 +        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
  7.1800 +    else
  7.1801 +`endif
  7.1802 +`ifdef CFG_INTERRUPTS_ENABLED
  7.1803 +         if (   (interrupt_exception == `TRUE)
  7.1804 +`ifdef LM32_SINGLE_STEP_ENABLED
  7.1805 +             && (dc_ss == `FALSE)
  7.1806 +`endif                            
  7.1807 +            )
  7.1808 +        eid_x = `LM32_EID_INTERRUPT;
  7.1809 +    else
  7.1810 +`endif
  7.1811 +        eid_x = `LM32_EID_SCALL;
  7.1812 +end
  7.1813 +
  7.1814 +// Stall generation
  7.1815 +
  7.1816 +assign stall_a = (stall_f == `TRUE);
  7.1817 +                
  7.1818 +assign stall_f = (stall_d == `TRUE);
  7.1819 +                
  7.1820 +assign stall_d =   (stall_x == `TRUE) 
  7.1821 +                || (   (interlock == `TRUE)
  7.1822 +                    && (kill_d == `FALSE)
  7.1823 +                   ) 
  7.1824 +		|| (   (   (eret_d == `TRUE)
  7.1825 +			|| (scall_d == `TRUE)
  7.1826 +			|| (bus_error_d == `TRUE)
  7.1827 +		       )
  7.1828 +		    && (   (load_q_x == `TRUE)
  7.1829 +			|| (load_q_m == `TRUE)
  7.1830 +			|| (store_q_x == `TRUE)
  7.1831 +			|| (store_q_m == `TRUE)
  7.1832 +			|| (D_CYC_O == `TRUE)
  7.1833 +		       )
  7.1834 +                    && (kill_d == `FALSE)
  7.1835 +		   )
  7.1836 +`ifdef CFG_DEBUG_ENABLED
  7.1837 +		|| (   (   (break_d == `TRUE)
  7.1838 +			|| (bret_d == `TRUE)
  7.1839 +		       )
  7.1840 +		    && (   (load_q_x == `TRUE)
  7.1841 +			|| (store_q_x == `TRUE)
  7.1842 +			|| (load_q_m == `TRUE)
  7.1843 +			|| (store_q_m == `TRUE)
  7.1844 +			|| (D_CYC_O == `TRUE)
  7.1845 +		       )
  7.1846 +                    && (kill_d == `FALSE)
  7.1847 +		   )
  7.1848 +`endif                   
  7.1849 +                || (   (csr_write_enable_d == `TRUE)
  7.1850 +                    && (load_q_x == `TRUE)
  7.1851 +                   )                      
  7.1852 +                ;
  7.1853 +                
  7.1854 +assign stall_x =    (stall_m == `TRUE)
  7.1855 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1856 +                 || (   (mc_stall_request_x == `TRUE)
  7.1857 +                     && (kill_x == `FALSE)
  7.1858 +                    ) 
  7.1859 +`endif
  7.1860 +`ifdef CFG_IROM_ENABLED
  7.1861 +                 // Stall load/store instruction in D stage if there is an ongoing store
  7.1862 +                 // operation to instruction ROM in M stage
  7.1863 +                 || (   (irom_stall_request_x == `TRUE)
  7.1864 +		     && (   (load_d == `TRUE)
  7.1865 +			 || (store_d == `TRUE)
  7.1866 +			)
  7.1867 +		    )
  7.1868 +`endif
  7.1869 +                 ;
  7.1870 +
  7.1871 +assign stall_m =    (stall_wb_load == `TRUE)
  7.1872 +`ifdef CFG_SIZE_OVER_SPEED
  7.1873 +                 || (D_CYC_O == `TRUE)
  7.1874 +`else
  7.1875 +                 || (   (D_CYC_O == `TRUE)
  7.1876 +                     && (   (store_m == `TRUE)
  7.1877 +		         /*
  7.1878 +			  Bug: Following loop does not allow interrupts to be services since
  7.1879 +			  either D_CYC_O or store_m is always high during entire duration of
  7.1880 +			  loop.
  7.1881 +		          L1:	addi	r1, r1, 1
  7.1882 +			  	sw	(r2,0), r1
  7.1883 +			  	bi	L1
  7.1884 +			  
  7.1885 +			  Introduce a single-cycle stall when a wishbone cycle is in progress
  7.1886 +			  and a new store instruction is in Execute stage and a interrupt
  7.1887 +			  exception has occured. This stall will ensure that D_CYC_O and 
  7.1888 +			  store_m will both be low for one cycle.
  7.1889 +			  */
  7.1890 +		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
  7.1891 +                         || (load_m == `TRUE)
  7.1892 +                         || (load_x == `TRUE)
  7.1893 +                        ) 
  7.1894 +                    ) 
  7.1895 +`endif                 
  7.1896 +`ifdef CFG_DCACHE_ENABLED
  7.1897 +                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
  7.1898 +`endif                                    
  7.1899 +`ifdef CFG_ICACHE_ENABLED
  7.1900 +                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
  7.1901 +                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
  7.1902 +`else
  7.1903 +`ifdef CFG_IWB_ENABLED
  7.1904 +                 || (I_CYC_O == `TRUE)            
  7.1905 +`endif
  7.1906 +`endif                               
  7.1907 +`ifdef CFG_USER_ENABLED
  7.1908 +                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
  7.1909 +                     && (user_complete == `FALSE)
  7.1910 +                    )
  7.1911 +`endif
  7.1912 +                 ;      
  7.1913 +
  7.1914 +// Qualify state changing control signals
  7.1915 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.1916 +assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
  7.1917 +`endif
  7.1918 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  7.1919 +assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
  7.1920 +assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
  7.1921 +`endif
  7.1922 +`ifdef CFG_MC_MULTIPLY_ENABLED
  7.1923 +assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
  7.1924 +`endif
  7.1925 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.1926 +assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
  7.1927 +assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
  7.1928 +`endif
  7.1929 +assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
  7.1930 +assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
  7.1931 +assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
  7.1932 +`ifdef CFG_DEBUG_ENABLED
  7.1933 +assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
  7.1934 +`endif
  7.1935 +assign load_q_x = (load_x == `TRUE) 
  7.1936 +               && (q_x == `TRUE)
  7.1937 +`ifdef CFG_DEBUG_ENABLED
  7.1938 +               && (bp_match == `FALSE)
  7.1939 +`endif
  7.1940 +                  ;
  7.1941 +assign store_q_x = (store_x == `TRUE) 
  7.1942 +               && (q_x == `TRUE)
  7.1943 +`ifdef CFG_DEBUG_ENABLED
  7.1944 +               && (bp_match == `FALSE)
  7.1945 +`endif
  7.1946 +                  ;
  7.1947 +`ifdef CFG_USER_ENABLED
  7.1948 +assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
  7.1949 +`endif                              
  7.1950 +assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
  7.1951 +assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
  7.1952 +assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
  7.1953 +`ifdef CFG_DEBUG_ENABLED
  7.1954 +assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
  7.1955 +assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
  7.1956 +`else
  7.1957 +assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
  7.1958 +`endif
  7.1959 +// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
  7.1960 +assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
  7.1961 +assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
  7.1962 +assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
  7.1963 +// The enable that actually does write the registers needs to be qualified with kill
  7.1964 +assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
  7.1965 +
  7.1966 +// Configuration (CFG) CSR
  7.1967 +assign cfg = {
  7.1968 +              `LM32_REVISION,
  7.1969 +              watchpoints[3:0],
  7.1970 +              breakpoints[3:0],
  7.1971 +              interrupts[5:0],
  7.1972 +`ifdef CFG_JTAG_UART_ENABLED
  7.1973 +              `TRUE,
  7.1974 +`else
  7.1975 +              `FALSE,
  7.1976 +`endif
  7.1977 +`ifdef CFG_ROM_DEBUG_ENABLED
  7.1978 +              `TRUE,
  7.1979 +`else
  7.1980 +              `FALSE,
  7.1981 +`endif
  7.1982 +`ifdef CFG_HW_DEBUG_ENABLED
  7.1983 +              `TRUE,
  7.1984 +`else
  7.1985 +              `FALSE,
  7.1986 +`endif
  7.1987 +`ifdef CFG_DEBUG_ENABLED
  7.1988 +              `TRUE,
  7.1989 +`else
  7.1990 +              `FALSE,
  7.1991 +`endif
  7.1992 +`ifdef CFG_ICACHE_ENABLED
  7.1993 +              `TRUE,
  7.1994 +`else
  7.1995 +              `FALSE,
  7.1996 +`endif
  7.1997 +`ifdef CFG_DCACHE_ENABLED
  7.1998 +              `TRUE,
  7.1999 +`else
  7.2000 +              `FALSE,
  7.2001 +`endif
  7.2002 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2003 +              `TRUE,
  7.2004 +`else
  7.2005 +              `FALSE,
  7.2006 +`endif
  7.2007 +`ifdef CFG_USER_ENABLED
  7.2008 +              `TRUE,
  7.2009 +`else
  7.2010 +              `FALSE,
  7.2011 +`endif
  7.2012 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2013 +              `TRUE,
  7.2014 +`else
  7.2015 +              `FALSE,
  7.2016 +`endif
  7.2017 +`ifdef LM32_BARREL_SHIFT_ENABLED
  7.2018 +              `TRUE,
  7.2019 +`else
  7.2020 +              `FALSE,
  7.2021 +`endif
  7.2022 +`ifdef CFG_MC_DIVIDE_ENABLED
  7.2023 +              `TRUE,
  7.2024 +`else
  7.2025 +              `FALSE,
  7.2026 +`endif
  7.2027 +`ifdef LM32_MULTIPLY_ENABLED 
  7.2028 +              `TRUE
  7.2029 +`else
  7.2030 +              `FALSE
  7.2031 +`endif
  7.2032 +              };
  7.2033 +
  7.2034 +assign cfg2 = {
  7.2035 +		     30'b0,
  7.2036 +`ifdef CFG_IROM_ENABLED
  7.2037 +		     `TRUE,
  7.2038 +`else
  7.2039 +		     `FALSE,
  7.2040 +`endif
  7.2041 +`ifdef CFG_DRAM_ENABLED
  7.2042 +		     `TRUE
  7.2043 +`else
  7.2044 +		     `FALSE
  7.2045 +`endif
  7.2046 +		     };
  7.2047 +   
  7.2048 +// Cache flush
  7.2049 +`ifdef CFG_ICACHE_ENABLED
  7.2050 +assign iflush =    (csr_write_enable_d == `TRUE) 
  7.2051 +                && (csr_d == `LM32_CSR_ICC)
  7.2052 +                && (stall_d == `FALSE)
  7.2053 +                && (kill_d == `FALSE)
  7.2054 +                && (valid_d == `TRUE);
  7.2055 +`endif 
  7.2056 +`ifdef CFG_DCACHE_ENABLED
  7.2057 +assign dflush_x =  (csr_write_enable_q_x == `TRUE) 
  7.2058 +                && (csr_x == `LM32_CSR_DCC);
  7.2059 +`endif 
  7.2060 +
  7.2061 +// Extract CSR index
  7.2062 +assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
  7.2063 +
  7.2064 +// CSR reads
  7.2065 +always @(*)
  7.2066 +begin
  7.2067 +    case (csr_x)
  7.2068 +`ifdef CFG_INTERRUPTS_ENABLED
  7.2069 +    `LM32_CSR_IE,
  7.2070 +    `LM32_CSR_IM,
  7.2071 +    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
  7.2072 +`endif
  7.2073 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2074 +    `LM32_CSR_CC:   csr_read_data_x = cc;
  7.2075 +`endif
  7.2076 +    `LM32_CSR_CFG:  csr_read_data_x = cfg;
  7.2077 +    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
  7.2078 +`ifdef CFG_DEBUG_ENABLED
  7.2079 +    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
  7.2080 +`endif
  7.2081 +`ifdef CFG_JTAG_UART_ENABLED
  7.2082 +    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
  7.2083 +    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
  7.2084 +`endif
  7.2085 +    `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  7.2086 +      
  7.2087 +    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
  7.2088 +    endcase
  7.2089 +end
  7.2090 +
  7.2091 +/////////////////////////////////////////////////////
  7.2092 +// Sequential Logic
  7.2093 +/////////////////////////////////////////////////////
  7.2094 +
  7.2095 +// Exception Base Address (EBA) CSR
  7.2096 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2097 +begin
  7.2098 +    if (rst_i == `TRUE)
  7.2099 +        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
  7.2100 +    else
  7.2101 +    begin
  7.2102 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
  7.2103 +            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  7.2104 +`ifdef CFG_HW_DEBUG_ENABLED
  7.2105 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
  7.2106 +            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  7.2107 +`endif
  7.2108 +    end
  7.2109 +end
  7.2110 +
  7.2111 +`ifdef CFG_DEBUG_ENABLED
  7.2112 +// Debug Exception Base Address (DEBA) CSR
  7.2113 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2114 +begin
  7.2115 +    if (rst_i == `TRUE)
  7.2116 +        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
  7.2117 +    else
  7.2118 +    begin
  7.2119 +        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
  7.2120 +            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  7.2121 +`ifdef CFG_HW_DEBUG_ENABLED
  7.2122 +        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
  7.2123 +            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  7.2124 +`endif
  7.2125 +    end
  7.2126 +end
  7.2127 +`endif
  7.2128 +
  7.2129 +// Cycle Counter (CC) CSR
  7.2130 +`ifdef CFG_CYCLE_COUNTER_ENABLED
  7.2131 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2132 +begin
  7.2133 +    if (rst_i == `TRUE)
  7.2134 +        cc <= {`LM32_WORD_WIDTH{1'b0}};
  7.2135 +    else
  7.2136 +        cc <= cc + 1'b1;
  7.2137 +end
  7.2138 +`endif
  7.2139 +
  7.2140 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2141 +// Watch for data bus errors
  7.2142 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2143 +begin
  7.2144 +    if (rst_i == `TRUE)
  7.2145 +        data_bus_error_seen <= `FALSE;
  7.2146 +    else
  7.2147 +    begin
  7.2148 +        // Set flag when bus error is detected
  7.2149 +        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
  7.2150 +            data_bus_error_seen <= `TRUE;
  7.2151 +        // Clear flag when exception is taken
  7.2152 +        if ((exception_m == `TRUE) && (kill_m == `FALSE))
  7.2153 +            data_bus_error_seen <= `FALSE;
  7.2154 +    end
  7.2155 +end
  7.2156 +`endif
  7.2157 + 
  7.2158 +// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  7.2159 +
  7.2160 +`ifdef CFG_ICACHE_ENABLED
  7.2161 +`ifdef CFG_DCACHE_ENABLED
  7.2162 +always @(*)
  7.2163 +begin
  7.2164 +    if (   (icache_refill_request == `TRUE) 
  7.2165 +        || (dcache_refill_request == `TRUE)
  7.2166 +       )
  7.2167 +        valid_a = `FALSE;
  7.2168 +    else if (   (icache_restart_request == `TRUE) 
  7.2169 +             || (dcache_restart_request == `TRUE) 
  7.2170 +            ) 
  7.2171 +        valid_a = `TRUE;
  7.2172 +    else 
  7.2173 +        valid_a = !icache_refilling && !dcache_refilling;
  7.2174 +end 
  7.2175 +`else
  7.2176 +always @(*)
  7.2177 +begin
  7.2178 +    if (icache_refill_request == `TRUE) 
  7.2179 +        valid_a = `FALSE;
  7.2180 +    else if (icache_restart_request == `TRUE) 
  7.2181 +        valid_a = `TRUE;
  7.2182 +    else 
  7.2183 +        valid_a = !icache_refilling;
  7.2184 +end 
  7.2185 +`endif
  7.2186 +`else
  7.2187 +`ifdef CFG_DCACHE_ENABLED
  7.2188 +always @(*)
  7.2189 +begin
  7.2190 +    if (dcache_refill_request == `TRUE) 
  7.2191 +        valid_a = `FALSE;
  7.2192 +    else if (dcache_restart_request == `TRUE) 
  7.2193 +        valid_a = `TRUE;
  7.2194 +    else 
  7.2195 +        valid_a = !dcache_refilling;
  7.2196 +end 
  7.2197 +`endif
  7.2198 +`endif
  7.2199 +
  7.2200 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2201 +begin
  7.2202 +    if (rst_i == `TRUE)
  7.2203 +    begin
  7.2204 +        valid_f <= `FALSE;
  7.2205 +        valid_d <= `FALSE;
  7.2206 +        valid_x <= `FALSE;
  7.2207 +        valid_m <= `FALSE;
  7.2208 +        valid_w <= `FALSE;
  7.2209 +    end
  7.2210 +    else
  7.2211 +    begin    
  7.2212 +        if ((kill_f == `TRUE) || (stall_a == `FALSE))
  7.2213 +`ifdef LM32_CACHE_ENABLED
  7.2214 +            valid_f <= valid_a;    
  7.2215 +`else
  7.2216 +            valid_f <= `TRUE;
  7.2217 +`endif            
  7.2218 +        else if (stall_f == `FALSE)
  7.2219 +            valid_f <= `FALSE;            
  7.2220 +
  7.2221 +        if (kill_d == `TRUE)
  7.2222 +            valid_d <= `FALSE;
  7.2223 +        else if (stall_f == `FALSE)
  7.2224 +            valid_d <= valid_f & !kill_f;
  7.2225 +        else if (stall_d == `FALSE)
  7.2226 +            valid_d <= `FALSE;
  7.2227 +       
  7.2228 +        if (stall_d == `FALSE)
  7.2229 +            valid_x <= valid_d & !kill_d;
  7.2230 +        else if (kill_x == `TRUE)
  7.2231 +            valid_x <= `FALSE;
  7.2232 +        else if (stall_x == `FALSE)
  7.2233 +            valid_x <= `FALSE;
  7.2234 +
  7.2235 +        if (kill_m == `TRUE)
  7.2236 +            valid_m <= `FALSE;
  7.2237 +        else if (stall_x == `FALSE)
  7.2238 +            valid_m <= valid_x & !kill_x;
  7.2239 +        else if (stall_m == `FALSE)
  7.2240 +            valid_m <= `FALSE;
  7.2241 +
  7.2242 +        if (stall_m == `FALSE)
  7.2243 +            valid_w <= valid_m & !kill_m;
  7.2244 +        else 
  7.2245 +            valid_w <= `FALSE;        
  7.2246 +    end
  7.2247 +end
  7.2248 +
  7.2249 +// Microcode pipeline registers
  7.2250 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2251 +begin
  7.2252 +    if (rst_i == `TRUE)
  7.2253 +    begin
  7.2254 +`ifdef CFG_USER_ENABLED
  7.2255 +        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
  7.2256 +`endif        
  7.2257 +        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2258 +        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2259 +        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
  7.2260 +        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
  7.2261 +        x_result_sel_csr_x <= `FALSE;
  7.2262 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.2263 +        x_result_sel_mc_arith_x <= `FALSE;
  7.2264 +`endif
  7.2265 +`ifdef LM32_NO_BARREL_SHIFT    
  7.2266 +        x_result_sel_shift_x <= `FALSE;
  7.2267 +`endif
  7.2268 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2269 +        x_result_sel_sext_x <= `FALSE;
  7.2270 +`endif    
  7.2271 +        x_result_sel_logic_x <= `FALSE;
  7.2272 +`ifdef CFG_USER_ENABLED
  7.2273 +        x_result_sel_user_x <= `FALSE;
  7.2274 +`endif
  7.2275 +        x_result_sel_add_x <= `FALSE;
  7.2276 +        m_result_sel_compare_x <= `FALSE;
  7.2277 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2278 +        m_result_sel_shift_x <= `FALSE;
  7.2279 +`endif    
  7.2280 +        w_result_sel_load_x <= `FALSE;
  7.2281 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2282 +        w_result_sel_mul_x <= `FALSE;
  7.2283 +`endif
  7.2284 +        x_bypass_enable_x <= `FALSE;
  7.2285 +        m_bypass_enable_x <= `FALSE;
  7.2286 +        write_enable_x <= `FALSE;
  7.2287 +        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
  7.2288 +        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
  7.2289 +        load_x <= `FALSE;
  7.2290 +        store_x <= `FALSE;
  7.2291 +        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
  7.2292 +        sign_extend_x <= `FALSE;
  7.2293 +        adder_op_x <= `FALSE;
  7.2294 +        adder_op_x_n <= `FALSE;
  7.2295 +        logic_op_x <= 4'h0;
  7.2296 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2297 +        direction_x <= `FALSE;
  7.2298 +`endif
  7.2299 +`ifdef CFG_ROTATE_ENABLED
  7.2300 +        rotate_x <= `FALSE;
  7.2301 +
  7.2302 +`endif
  7.2303 +        branch_x <= `FALSE;
  7.2304 +        branch_predict_x <= `FALSE;
  7.2305 +        branch_predict_taken_x <= `FALSE;
  7.2306 +        condition_x <= `LM32_CONDITION_U1;
  7.2307 +`ifdef CFG_DEBUG_ENABLED
  7.2308 +        break_x <= `FALSE;
  7.2309 +`endif
  7.2310 +        scall_x <= `FALSE;
  7.2311 +        eret_x <= `FALSE;
  7.2312 +`ifdef CFG_DEBUG_ENABLED
  7.2313 +        bret_x <= `FALSE;
  7.2314 +`endif
  7.2315 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2316 +        bus_error_x <= `FALSE;
  7.2317 +        data_bus_error_exception_m <= `FALSE;
  7.2318 +`endif
  7.2319 +        csr_write_enable_x <= `FALSE;
  7.2320 +        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
  7.2321 +        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
  7.2322 +        m_result_sel_compare_m <= `FALSE;
  7.2323 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2324 +        m_result_sel_shift_m <= `FALSE;
  7.2325 +`endif    
  7.2326 +        w_result_sel_load_m <= `FALSE;
  7.2327 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2328 +        w_result_sel_mul_m <= `FALSE;
  7.2329 +`endif
  7.2330 +        m_bypass_enable_m <= `FALSE;
  7.2331 +        branch_m <= `FALSE;
  7.2332 +        branch_predict_m <= `FALSE;
  7.2333 +	branch_predict_taken_m <= `FALSE;
  7.2334 +        exception_m <= `FALSE;
  7.2335 +        load_m <= `FALSE;
  7.2336 +        store_m <= `FALSE;
  7.2337 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2338 +        direction_m <= `FALSE;
  7.2339 +`endif
  7.2340 +        write_enable_m <= `FALSE;            
  7.2341 +        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
  7.2342 +        condition_met_m <= `FALSE;
  7.2343 +`ifdef CFG_DCACHE_ENABLED
  7.2344 +        dflush_m <= `FALSE;
  7.2345 +`endif
  7.2346 +`ifdef CFG_DEBUG_ENABLED
  7.2347 +        debug_exception_m <= `FALSE;
  7.2348 +        non_debug_exception_m <= `FALSE;        
  7.2349 +`endif
  7.2350 +        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
  7.2351 +        w_result_sel_load_w <= `FALSE;
  7.2352 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2353 +        w_result_sel_mul_w <= `FALSE;
  7.2354 +`endif
  7.2355 +        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
  7.2356 +        write_enable_w <= `FALSE;
  7.2357 +`ifdef CFG_DEBUG_ENABLED
  7.2358 +        debug_exception_w <= `FALSE;
  7.2359 +        non_debug_exception_w <= `FALSE;        
  7.2360 +`else
  7.2361 +        exception_w <= `FALSE;
  7.2362 +`endif
  7.2363 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2364 +        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
  7.2365 +`endif
  7.2366 +    end
  7.2367 +    else
  7.2368 +    begin
  7.2369 +        // D/X stage registers
  7.2370 +       
  7.2371 +        if (stall_x == `FALSE)
  7.2372 +        begin
  7.2373 +`ifdef CFG_USER_ENABLED
  7.2374 +            user_opcode <= user_opcode_d;       
  7.2375 +`endif        
  7.2376 +            operand_0_x <= d_result_0;
  7.2377 +            operand_1_x <= d_result_1;
  7.2378 +            store_operand_x <= bypass_data_1;
  7.2379 +            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
  7.2380 +            x_result_sel_csr_x <= x_result_sel_csr_d;
  7.2381 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  7.2382 +            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
  7.2383 +`endif
  7.2384 +`ifdef LM32_NO_BARREL_SHIFT    
  7.2385 +            x_result_sel_shift_x <= x_result_sel_shift_d;
  7.2386 +`endif
  7.2387 +`ifdef CFG_SIGN_EXTEND_ENABLED
  7.2388 +            x_result_sel_sext_x <= x_result_sel_sext_d;
  7.2389 +`endif    
  7.2390 +            x_result_sel_logic_x <= x_result_sel_logic_d;
  7.2391 +`ifdef CFG_USER_ENABLED
  7.2392 +            x_result_sel_user_x <= x_result_sel_user_d;
  7.2393 +`endif
  7.2394 +            x_result_sel_add_x <= x_result_sel_add_d;
  7.2395 +            m_result_sel_compare_x <= m_result_sel_compare_d;
  7.2396 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2397 +            m_result_sel_shift_x <= m_result_sel_shift_d;
  7.2398 +`endif    
  7.2399 +            w_result_sel_load_x <= w_result_sel_load_d;
  7.2400 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2401 +            w_result_sel_mul_x <= w_result_sel_mul_d;
  7.2402 +`endif
  7.2403 +            x_bypass_enable_x <= x_bypass_enable_d;
  7.2404 +            m_bypass_enable_x <= m_bypass_enable_d;
  7.2405 +            load_x <= load_d;
  7.2406 +            store_x <= store_d;
  7.2407 +            branch_x <= branch_d;
  7.2408 +	    branch_predict_x <= branch_predict_d;
  7.2409 +	    branch_predict_taken_x <= branch_predict_taken_d;
  7.2410 +	    write_idx_x <= write_idx_d;
  7.2411 +            csr_x <= csr_d;
  7.2412 +            size_x <= size_d;
  7.2413 +            sign_extend_x <= sign_extend_d;
  7.2414 +            adder_op_x <= adder_op_d;
  7.2415 +            adder_op_x_n <= ~adder_op_d;
  7.2416 +            logic_op_x <= logic_op_d;
  7.2417 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2418 +            direction_x <= direction_d;
  7.2419 +`endif
  7.2420 +`ifdef CFG_ROTATE_ENABLED
  7.2421 +            rotate_x <= rotate_d;
  7.2422 +`endif
  7.2423 +            condition_x <= condition_d;
  7.2424 +            csr_write_enable_x <= csr_write_enable_d;
  7.2425 +`ifdef CFG_DEBUG_ENABLED
  7.2426 +            break_x <= break_d;
  7.2427 +`endif
  7.2428 +            scall_x <= scall_d;
  7.2429 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2430 +            bus_error_x <= bus_error_d;
  7.2431 +`endif
  7.2432 +            eret_x <= eret_d;
  7.2433 +`ifdef CFG_DEBUG_ENABLED
  7.2434 +            bret_x <= bret_d; 
  7.2435 +`endif
  7.2436 +            write_enable_x <= write_enable_d;
  7.2437 +        end
  7.2438 +        
  7.2439 +        // X/M stage registers
  7.2440 +
  7.2441 +        if (stall_m == `FALSE)
  7.2442 +        begin
  7.2443 +            operand_m <= x_result;
  7.2444 +            m_result_sel_compare_m <= m_result_sel_compare_x;
  7.2445 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2446 +            m_result_sel_shift_m <= m_result_sel_shift_x;
  7.2447 +`endif    
  7.2448 +            if (exception_x == `TRUE)
  7.2449 +            begin
  7.2450 +                w_result_sel_load_m <= `FALSE;
  7.2451 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2452 +                w_result_sel_mul_m <= `FALSE;
  7.2453 +`endif
  7.2454 +            end
  7.2455 +            else
  7.2456 +            begin
  7.2457 +                w_result_sel_load_m <= w_result_sel_load_x;
  7.2458 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2459 +                w_result_sel_mul_m <= w_result_sel_mul_x;
  7.2460 +`endif
  7.2461 +            end
  7.2462 +            m_bypass_enable_m <= m_bypass_enable_x;
  7.2463 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  7.2464 +            direction_m <= direction_x;
  7.2465 +`endif
  7.2466 +            load_m <= load_x;
  7.2467 +            store_m <= store_x;
  7.2468 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  7.2469 +            branch_m <= branch_x && !branch_taken_x;
  7.2470 +`else
  7.2471 +            branch_m <= branch_x;
  7.2472 +	    branch_predict_m <= branch_predict_x;
  7.2473 +	    branch_predict_taken_m <= branch_predict_taken_x;
  7.2474 +`endif
  7.2475 +`ifdef CFG_DEBUG_ENABLED
  7.2476 +	   // Data bus errors are generated by the wishbone and are
  7.2477 +	   // made known to the processor only in next cycle (as a
  7.2478 +	   // non-debug exception). A break instruction can be seen
  7.2479 +	   // in same cycle (causing a debug exception). Handle non
  7.2480 +	   // -debug exception first!
  7.2481 +            if (non_debug_exception_x == `TRUE) 
  7.2482 +                write_idx_m <= `LM32_EA_REG;
  7.2483 +            else if (debug_exception_x == `TRUE)
  7.2484 +                write_idx_m <= `LM32_BA_REG;
  7.2485 +            else 
  7.2486 +                write_idx_m <= write_idx_x;
  7.2487 +`else
  7.2488 +            if (exception_x == `TRUE)
  7.2489 +                write_idx_m <= `LM32_EA_REG;
  7.2490 +            else 
  7.2491 +                write_idx_m <= write_idx_x;
  7.2492 +`endif
  7.2493 +            condition_met_m <= condition_met_x;
  7.2494 +`ifdef CFG_DEBUG_ENABLED
  7.2495 +	   if (exception_x == `TRUE)
  7.2496 +	     if ((dc_re == `TRUE)
  7.2497 +		 || ((debug_exception_x == `TRUE) 
  7.2498 +		     && (non_debug_exception_x == `FALSE)))
  7.2499 +	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
  7.2500 +	     else
  7.2501 +	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
  7.2502 +	   else
  7.2503 +	     branch_target_m <= branch_target_x;
  7.2504 +`else
  7.2505 +            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
  7.2506 +`endif
  7.2507 +`ifdef CFG_TRACE_ENABLED
  7.2508 +            eid_m <= eid_x;
  7.2509 +`endif
  7.2510 +`ifdef CFG_DCACHE_ENABLED
  7.2511 +            dflush_m <= dflush_x;
  7.2512 +`endif
  7.2513 +            eret_m <= eret_q_x;
  7.2514 +`ifdef CFG_DEBUG_ENABLED
  7.2515 +            bret_m <= bret_q_x; 
  7.2516 +`endif
  7.2517 +            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
  7.2518 +`ifdef CFG_DEBUG_ENABLED
  7.2519 +            debug_exception_m <= debug_exception_x;
  7.2520 +            non_debug_exception_m <= non_debug_exception_x;        
  7.2521 +`endif
  7.2522 +        end
  7.2523 +        
  7.2524 +        // State changing regs
  7.2525 +        if (stall_m == `FALSE)
  7.2526 +        begin
  7.2527 +            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  7.2528 +                exception_m <= `TRUE;
  7.2529 +            else 
  7.2530 +                exception_m <= `FALSE;
  7.2531 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2532 +	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
  7.2533 +`ifdef CFG_DEBUG_ENABLED
  7.2534 +					 && (reset_exception == `FALSE)
  7.2535 +`endif
  7.2536 +					 ;
  7.2537 +`endif
  7.2538 +	end
  7.2539 +                
  7.2540 +        // M/W stage registers
  7.2541 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2542 +        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
  7.2543 +`else
  7.2544 +        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
  7.2545 +`endif
  7.2546 +        w_result_sel_load_w <= w_result_sel_load_m;
  7.2547 +`ifdef CFG_PL_MULTIPLY_ENABLED
  7.2548 +        w_result_sel_mul_w <= w_result_sel_mul_m;
  7.2549 +`endif
  7.2550 +        write_idx_w <= write_idx_m;
  7.2551 +`ifdef CFG_TRACE_ENABLED
  7.2552 +        eid_w <= eid_m;
  7.2553 +        eret_w <= eret_m;
  7.2554 +`ifdef CFG_DEBUG_ENABLED
  7.2555 +        bret_w <= bret_m; 
  7.2556 +`endif
  7.2557 +`endif
  7.2558 +        write_enable_w <= write_enable_m;
  7.2559 +`ifdef CFG_DEBUG_ENABLED
  7.2560 +        debug_exception_w <= debug_exception_m;
  7.2561 +        non_debug_exception_w <= non_debug_exception_m;
  7.2562 +`else
  7.2563 +        exception_w <= exception_m;
  7.2564 +`endif
  7.2565 +`ifdef CFG_BUS_ERRORS_ENABLED
  7.2566 +        if (   (stall_m == `FALSE)
  7.2567 +            && (   (load_q_m == `TRUE) 
  7.2568 +                || (store_q_m == `TRUE)
  7.2569 +               )
  7.2570 +	   )
  7.2571 +          memop_pc_w <= pc_m;
  7.2572 +`endif
  7.2573 +    end
  7.2574 +end
  7.2575 +
  7.2576 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  7.2577 +// Buffer data read from register file, in case a stall occurs, and watch for
  7.2578 +// any writes to the modified registers
  7.2579 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2580 +begin
  7.2581 +    if (rst_i == `TRUE)
  7.2582 +    begin
  7.2583 +        use_buf <= `FALSE;
  7.2584 +        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
  7.2585 +        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
  7.2586 +    end
  7.2587 +    else
  7.2588 +    begin
  7.2589 +        if (stall_d == `FALSE)
  7.2590 +            use_buf <= `FALSE;
  7.2591 +        else if (use_buf == `FALSE)
  7.2592 +        begin        
  7.2593 +            reg_data_buf_0 <= reg_data_live_0;
  7.2594 +            reg_data_buf_1 <= reg_data_live_1;
  7.2595 +            use_buf <= `TRUE;
  7.2596 +        end        
  7.2597 +        if (reg_write_enable_q_w == `TRUE)
  7.2598 +        begin
  7.2599 +            if (write_idx_w == read_idx_0_d)
  7.2600 +                reg_data_buf_0 <= w_result;
  7.2601 +            if (write_idx_w == read_idx_1_d)
  7.2602 +                reg_data_buf_1 <= w_result;
  7.2603 +        end
  7.2604 +    end
  7.2605 +end
  7.2606 +`endif
  7.2607 +
  7.2608 +`ifdef LM32_EBR_REGISTER_FILE
  7.2609 +`else
  7.2610 +// Register file write port
  7.2611 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2612 +begin
  7.2613 +    if (rst_i == `TRUE) begin
  7.2614 +        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2615 +        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2616 +        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2617 +        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2618 +        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2619 +        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2620 +        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2621 +        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2622 +        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2623 +        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2624 +        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2625 +        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2626 +        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2627 +        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2628 +        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2629 +        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2630 +        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2631 +        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2632 +        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2633 +        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2634 +        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2635 +        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2636 +        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2637 +        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2638 +        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2639 +        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2640 +        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2641 +        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2642 +        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2643 +        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2644 +        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
  7.2645 +        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
  7.2646 +        end
  7.2647 +    else begin
  7.2648 +        if (reg_write_enable_q_w == `TRUE)
  7.2649 +          registers[write_idx_w] <= w_result;
  7.2650 +        end
  7.2651 +end
  7.2652 +`endif
  7.2653 +
  7.2654 +`ifdef CFG_TRACE_ENABLED
  7.2655 +// PC tracing logic
  7.2656 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  7.2657 +begin
  7.2658 +    if (rst_i == `TRUE)
  7.2659 +    begin
  7.2660 +        trace_pc_valid <= `FALSE;
  7.2661 +        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
  7.2662 +        trace_exception <= `FALSE;
  7.2663 +        trace_eid <= `LM32_EID_RESET;
  7.2664 +        trace_eret <= `FALSE;
  7.2665 +`ifdef CFG_DEBUG_ENABLED
  7.2666 +        trace_bret <= `FALSE;
  7.2667 +`endif
  7.2668 +        pc_c <= `CFG_EBA_RESET/4;
  7.2669 +    end
  7.2670 +    else
  7.2671 +    begin
  7.2672 +        trace_pc_valid <= `FALSE;
  7.2673 +        // Has an exception occured
  7.2674 +`ifdef CFG_DEBUG_ENABLED
  7.2675 +        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
  7.2676 +`else
  7.2677 +        if (exception_q_w == `TRUE)
  7.2678 +`endif
  7.2679 +        begin        
  7.2680 +            trace_exception <= `TRUE;
  7.2681 +            trace_pc_valid <= `TRUE;
  7.2682 +            trace_pc <= pc_w;
  7.2683 +            trace_eid <= eid_w;
  7.2684 +        end
  7.2685 +        else
  7.2686 +            trace_exception <= `FALSE;
  7.2687 +        
  7.2688 +        if ((valid_w == `TRUE) && (!kill_w))
  7.2689 +        begin
  7.2690 +            // An instruction is commiting. Determine if it is non-sequential
  7.2691 +            if (pc_c + 1'b1 != pc_w)
  7.2692 +            begin
  7.2693 +                // Non-sequential instruction
  7.2694 +                trace_pc_valid <= `TRUE;
  7.2695 +                trace_pc <= pc_w;
  7.2696 +            end
  7.2697 +            // Record PC so we can determine if next instruction is sequential or not
  7.2698 +            pc_c <= pc_w;
  7.2699 +            // Indicate if it was an eret/bret instruction
  7.2700 +            trace_eret <= eret_w;
  7.2701 +`ifdef CFG_DEBUG_ENABLED
  7.2702 +            trace_bret <= bret_w;
  7.2703 +`endif
  7.2704 +        end
  7.2705 +        else
  7.2706 +        begin
  7.2707 +            trace_eret <= `FALSE;
  7.2708 +`ifdef CFG_DEBUG_ENABLED
  7.2709 +            trace_bret <= `FALSE;
  7.2710 +`endif
  7.2711 +        end
  7.2712 +    end
  7.2713 +end
  7.2714 +`endif
  7.2715 +      
  7.2716 +/////////////////////////////////////////////////////
  7.2717 +// Behavioural Logic
  7.2718 +/////////////////////////////////////////////////////
  7.2719 +
  7.2720 +// synthesis translate_off            
  7.2721 +
  7.2722 +// Reset register 0. Only needed for simulation. 
  7.2723 +initial
  7.2724 +begin
  7.2725 +`ifdef LM32_EBR_REGISTER_FILE
  7.2726 +    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2727 +    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2728 +`else
  7.2729 +    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
  7.2730 +`endif
  7.2731 +end
  7.2732 +
  7.2733 +// synthesis translate_on
  7.2734 +        
  7.2735 +endmodule 
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/lm32_dcache.v	Sun Apr 04 20:40:03 2010 +0100
     8.3 @@ -0,0 +1,533 @@
     8.4 +// =============================================================================
     8.5 +//                           COPYRIGHT NOTICE
     8.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     8.7 +// ALL RIGHTS RESERVED
     8.8 +// This confidential and proprietary software may be used only as authorised by
     8.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    8.10 +// The entire notice above must be reproduced on all authorized copies and
    8.11 +// copies may only be made to the extent permitted by a licensing agreement from
    8.12 +// Lattice Semiconductor Corporation.
    8.13 +//
    8.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    8.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    8.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    8.17 +// U.S.A                                   email: techsupport@latticesemi.com
    8.18 +// =============================================================================/
    8.19 +//                         FILE DETAILS
    8.20 +// Project          : LatticeMico32
    8.21 +// File             : lm32_dcache.v
    8.22 +// Title            : Data cache
    8.23 +// Dependencies     : lm32_include.v
    8.24 +// Version          : 6.1.17
    8.25 +//                  : Initial Release
    8.26 +// Version          : 7.0SP2, 3.0
    8.27 +//                  : No Change
    8.28 +// Version	    : 3.1
    8.29 +//                  : Support for user-selected resource usage when implementing
    8.30 +//                  : cache memory. Additional parameters must be defined when
    8.31 +//                  : invoking lm32_ram.v
    8.32 +// =============================================================================
    8.33 +								 
    8.34 +`include "lm32_include.v"
    8.35 +
    8.36 +`ifdef CFG_DCACHE_ENABLED
    8.37 +
    8.38 +`define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
    8.39 +`define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
    8.40 +`define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
    8.41 +`define LM32_DC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
    8.42 +
    8.43 +`define LM32_DC_TMEM_ADDR_WIDTH          addr_set_width
    8.44 +`define LM32_DC_TMEM_ADDR_RNG            (`LM32_DC_TMEM_ADDR_WIDTH-1):0
    8.45 +`define LM32_DC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
    8.46 +`define LM32_DC_DMEM_ADDR_RNG            (`LM32_DC_DMEM_ADDR_WIDTH-1):0
    8.47 +
    8.48 +`define LM32_DC_TAGS_WIDTH               (addr_tag_width+1)
    8.49 +`define LM32_DC_TAGS_RNG                 (`LM32_DC_TAGS_WIDTH-1):0
    8.50 +`define LM32_DC_TAGS_TAG_RNG             (`LM32_DC_TAGS_WIDTH-1):1
    8.51 +`define LM32_DC_TAGS_VALID_RNG           0
    8.52 +
    8.53 +`define LM32_DC_STATE_RNG                2:0
    8.54 +`define LM32_DC_STATE_FLUSH              3'b001
    8.55 +`define LM32_DC_STATE_CHECK              3'b010
    8.56 +`define LM32_DC_STATE_REFILL             3'b100
    8.57 +
    8.58 +/////////////////////////////////////////////////////
    8.59 +// Module interface
    8.60 +/////////////////////////////////////////////////////
    8.61 +
    8.62 +module lm32_dcache ( 
    8.63 +    // ----- Inputs -----
    8.64 +    clk_i,
    8.65 +    rst_i,    
    8.66 +    stall_a,
    8.67 +    stall_x,
    8.68 +    stall_m,
    8.69 +    address_x,
    8.70 +    address_m,
    8.71 +    load_q_m,
    8.72 +    store_q_m,
    8.73 +    store_data,
    8.74 +    store_byte_select,
    8.75 +    refill_ready,
    8.76 +    refill_data,
    8.77 +    dflush,
    8.78 +    // ----- Outputs -----
    8.79 +    stall_request,
    8.80 +    restart_request,
    8.81 +    refill_request,
    8.82 +    refill_address,
    8.83 +    refilling,
    8.84 +    load_data
    8.85 +    );
    8.86 +
    8.87 +/////////////////////////////////////////////////////
    8.88 +// Parameters
    8.89 +/////////////////////////////////////////////////////
    8.90 +
    8.91 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
    8.92 +parameter sets = 512;                                   // Number of sets
    8.93 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
    8.94 +parameter base_address = 0;                             // Base address of cachable memory
    8.95 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
    8.96 +
    8.97 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
    8.98 +localparam addr_set_width = clogb2(sets)-1;
    8.99 +localparam addr_offset_lsb = 2;
   8.100 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
   8.101 +localparam addr_set_lsb = (addr_offset_msb+1);
   8.102 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
   8.103 +localparam addr_tag_lsb = (addr_set_msb+1);
   8.104 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
   8.105 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
   8.106 +
   8.107 +/////////////////////////////////////////////////////
   8.108 +// Inputs
   8.109 +/////////////////////////////////////////////////////
   8.110 +
   8.111 +input clk_i;                                            // Clock
   8.112 +input rst_i;                                            // Reset
   8.113 +
   8.114 +input stall_a;                                          // Stall A stage
   8.115 +input stall_x;                                          // Stall X stage
   8.116 +input stall_m;                                          // Stall M stage
   8.117 +
   8.118 +input [`LM32_WORD_RNG] address_x;                       // X stage load/store address
   8.119 +input [`LM32_WORD_RNG] address_m;                       // M stage load/store address
   8.120 +input load_q_m;                                         // Load instruction in M stage
   8.121 +input store_q_m;                                        // Store instruction in M stage
   8.122 +input [`LM32_WORD_RNG] store_data;                      // Data to store
   8.123 +input [`LM32_BYTE_SELECT_RNG] store_byte_select;        // Which bytes in store data should be modified
   8.124 +
   8.125 +input refill_ready;                                     // Indicates next word of refill data is ready
   8.126 +input [`LM32_WORD_RNG] refill_data;                     // Refill data
   8.127 +
   8.128 +input dflush;                                           // Indicates cache should be flushed
   8.129 +
   8.130 +/////////////////////////////////////////////////////
   8.131 +// Outputs
   8.132 +/////////////////////////////////////////////////////
   8.133 +
   8.134 +output stall_request;                                   // Request pipeline be stalled because cache is busy
   8.135 +wire   stall_request;
   8.136 +output restart_request;                                 // Request to restart instruction that caused the cache miss
   8.137 +reg    restart_request;
   8.138 +output refill_request;                                  // Request a refill 
   8.139 +reg    refill_request;
   8.140 +output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
   8.141 +reg    [`LM32_WORD_RNG] refill_address;
   8.142 +output refilling;                                       // Indicates if the cache is currently refilling
   8.143 +reg    refilling;
   8.144 +output [`LM32_WORD_RNG] load_data;                      // Data read from cache
   8.145 +wire   [`LM32_WORD_RNG] load_data;
   8.146 +
   8.147 +/////////////////////////////////////////////////////
   8.148 +// Internal nets and registers 
   8.149 +/////////////////////////////////////////////////////
   8.150 +
   8.151 +wire read_port_enable;                                  // Cache memory read port clock enable
   8.152 +wire write_port_enable;                                 // Cache memory write port clock enable
   8.153 +wire [0:associativity-1] way_tmem_we;                   // Tag memory write enable
   8.154 +wire [0:associativity-1] way_dmem_we;                   // Data memory write enable
   8.155 +wire [`LM32_WORD_RNG] way_data[0:associativity-1];      // Data read from data memory
   8.156 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
   8.157 +wire [0:associativity-1] way_valid;                     // Indicates which ways are valid
   8.158 +wire [0:associativity-1] way_match;                     // Indicates which ways matched
   8.159 +wire miss;                                              // Indicates no ways matched
   8.160 +
   8.161 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read address
   8.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
   8.163 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
   8.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
   8.165 +wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
   8.166 +reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
   8.167 +
   8.168 +reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
   8.169 +wire flushing;                                          // Indicates if cache is currently flushing
   8.170 +wire check;                                             // Indicates if cache is currently checking for hits/misses
   8.171 +wire refill;                                            // Indicates if cache is currently refilling
   8.172 +
   8.173 +wire valid_store;                                       // Indicates if there is a valid store instruction
   8.174 +reg [associativity-1:0] refill_way_select;              // Which way should be refilled
   8.175 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache line should be refilled
   8.176 +wire last_refill;                                       // Indicates when on last cycle of cache refill
   8.177 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
   8.178 +
   8.179 +genvar i, j;
   8.180 +
   8.181 +/////////////////////////////////////////////////////
   8.182 +// Functions
   8.183 +/////////////////////////////////////////////////////
   8.184 +
   8.185 +`include "lm32_functions.v"
   8.186 +
   8.187 +/////////////////////////////////////////////////////
   8.188 +// Instantiations
   8.189 +/////////////////////////////////////////////////////
   8.190 +
   8.191 +   generate
   8.192 +      for (i = 0; i < associativity; i = i + 1)    
   8.193 +	begin : memories
   8.194 +	   // Way data
   8.195 +           if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
   8.196 +             begin : data_memories
   8.197 +		lm32_ram 
   8.198 +		  #(
   8.199 +		    // ----- Parameters -------
   8.200 +		    .data_width (32),
   8.201 +		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
   8.202 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.203 +		    .RAM_IMPLEMENTATION ("EBR"),
   8.204 +		    .RAM_TYPE ("RAM_DP_TRUE")
   8.205 +`else
   8.206 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.207 +		    .RAM_IMPLEMENTATION ("SLICE")
   8.208 + `else
   8.209 +		    .RAM_IMPLEMENTATION ("AUTO")
   8.210 + `endif
   8.211 +`endif
   8.212 +		    ) way_0_data_ram 
   8.213 +		    (
   8.214 +		     // ----- Inputs -------
   8.215 +		     .read_clk (clk_i),
   8.216 +		     .write_clk (clk_i),
   8.217 +		     .reset (rst_i),
   8.218 +		     .read_address (dmem_read_address),
   8.219 +		     .enable_read (read_port_enable),
   8.220 +		     .write_address (dmem_write_address),
   8.221 +		     .enable_write (write_port_enable),
   8.222 +		     .write_enable (way_dmem_we[i]),
   8.223 +		     .write_data (dmem_write_data),    
   8.224 +		     // ----- Outputs -------
   8.225 +		     .read_data (way_data[i])
   8.226 +		     );    
   8.227 +             end
   8.228 +           else
   8.229 +             begin
   8.230 +		for (j = 0; j < 4; j = j + 1)    
   8.231 +		  begin : byte_memories
   8.232 +		     lm32_ram 
   8.233 +		       #(
   8.234 +			 // ----- Parameters -------
   8.235 +			 .data_width (8),
   8.236 +			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
   8.237 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.238 +			 .RAM_IMPLEMENTATION ("EBR"),
   8.239 +			 .RAM_TYPE ("RAM_DP_TRUE")
   8.240 +`else
   8.241 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.242 +			 .RAM_IMPLEMENTATION ("SLICE")
   8.243 + `else
   8.244 +			 .RAM_IMPLEMENTATION ("AUTO")
   8.245 + `endif
   8.246 +`endif
   8.247 +			 ) way_0_data_ram 
   8.248 +			 (
   8.249 +			  // ----- Inputs -------
   8.250 +			  .read_clk (clk_i),
   8.251 +			  .write_clk (clk_i),
   8.252 +			  .reset (rst_i),
   8.253 +			  .read_address (dmem_read_address),
   8.254 +			  .enable_read (read_port_enable),
   8.255 +			  .write_address (dmem_write_address),
   8.256 +			  .enable_write (write_port_enable),
   8.257 +			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
   8.258 +			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
   8.259 +			  // ----- Outputs -------
   8.260 +			  .read_data (way_data[i][(j+1)*8-1:j*8])
   8.261 +			  );
   8.262 +		  end
   8.263 +             end
   8.264 +	   
   8.265 +	   // Way tags
   8.266 +	   lm32_ram 
   8.267 +	     #(
   8.268 +	       // ----- Parameters -------
   8.269 +	       .data_width (`LM32_DC_TAGS_WIDTH),
   8.270 +	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
   8.271 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE
   8.272 +	       .RAM_IMPLEMENTATION ("EBR"),
   8.273 +	       .RAM_TYPE ("RAM_DP_TRUE")
   8.274 +`else
   8.275 + `ifdef CFG_DCACHE_DAT_USE_SLICE
   8.276 +	       .RAM_IMPLEMENTATION ("SLICE")
   8.277 + `else
   8.278 +	       .RAM_IMPLEMENTATION ("AUTO")
   8.279 + `endif
   8.280 +`endif
   8.281 +	       ) way_0_tag_ram 
   8.282 +	       (
   8.283 +		// ----- Inputs -------
   8.284 +		.read_clk (clk_i),
   8.285 +		.write_clk (clk_i),
   8.286 +		.reset (rst_i),
   8.287 +		.read_address (tmem_read_address),
   8.288 +		.enable_read (read_port_enable),
   8.289 +		.write_address (tmem_write_address),
   8.290 +		.enable_write (`TRUE),
   8.291 +		.write_enable (way_tmem_we[i]),
   8.292 +		.write_data (tmem_write_data),
   8.293 +		// ----- Outputs -------
   8.294 +		.read_data ({way_tag[i], way_valid[i]})
   8.295 +		);
   8.296 +	end
   8.297 +      
   8.298 +   endgenerate
   8.299 +
   8.300 +/////////////////////////////////////////////////////
   8.301 +// Combinational logic
   8.302 +/////////////////////////////////////////////////////
   8.303 +
   8.304 +// Compute which ways in the cache match the address being read
   8.305 +generate
   8.306 +    for (i = 0; i < associativity; i = i + 1)
   8.307 +    begin : match
   8.308 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
   8.309 +    end
   8.310 +endgenerate
   8.311 +
   8.312 +// Select data from way that matched the address being read     
   8.313 +generate
   8.314 +    if (associativity == 1)    
   8.315 +	 begin : data_1
   8.316 +assign load_data = way_data[0];
   8.317 +    end
   8.318 +    else if (associativity == 2)
   8.319 +	 begin : data_2
   8.320 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
   8.321 +    end
   8.322 +endgenerate
   8.323 +
   8.324 +generate
   8.325 +    if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
   8.326 +    begin
   8.327 +// Select data to write to data memories
   8.328 +always @(*)
   8.329 +begin
   8.330 +    if (refill == `TRUE)
   8.331 +        dmem_write_data = refill_data;
   8.332 +    else
   8.333 +    begin
   8.334 +        dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
   8.335 +        dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
   8.336 +        dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
   8.337 +        dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
   8.338 +    end
   8.339 +end
   8.340 +    end
   8.341 +    else
   8.342 +    begin
   8.343 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
   8.344 +always @(*)
   8.345 +begin
   8.346 +    if (refill == `TRUE)
   8.347 +        dmem_write_data = refill_data;
   8.348 +    else
   8.349 +        dmem_write_data = store_data;
   8.350 +end
   8.351 +    end
   8.352 +endgenerate
   8.353 +
   8.354 +// Compute address to use to index into the data memories
   8.355 +generate 
   8.356 +     if (bytes_per_line > 4)
   8.357 +assign dmem_write_address = (refill == `TRUE) 
   8.358 +                            ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
   8.359 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
   8.360 +    else
   8.361 +assign dmem_write_address = (refill == `TRUE) 
   8.362 +                            ? refill_address[`LM32_DC_ADDR_SET_RNG]
   8.363 +                            : address_m[`LM32_DC_ADDR_IDX_RNG];
   8.364 +endgenerate
   8.365 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
   8.366 +// Compute address to use to index into the tag memories   
   8.367 +assign tmem_write_address = (flushing == `TRUE)
   8.368 +                            ? flush_set
   8.369 +                            : refill_address[`LM32_DC_ADDR_SET_RNG];
   8.370 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
   8.371 +
   8.372 +// Compute signal to indicate when we are on the last refill accesses
   8.373 +generate 
   8.374 +    if (bytes_per_line > 4)                            
   8.375 +assign last_refill = refill_offset == {addr_offset_width{1'b1}};
   8.376 +    else
   8.377 +assign last_refill = `TRUE;
   8.378 +endgenerate
   8.379 +
   8.380 +// Compute data and tag memory access enable
   8.381 +assign read_port_enable = (stall_x == `FALSE);
   8.382 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
   8.383 +
   8.384 +// Determine when we have a valid store
   8.385 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
   8.386 +
   8.387 +// Compute data and tag memory write enables
   8.388 +generate
   8.389 +    if (associativity == 1) 
   8.390 +    begin : we_1     
   8.391 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
   8.392 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
   8.393 +    end 
   8.394 +    else 
   8.395 +    begin : we_2
   8.396 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
   8.397 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
   8.398 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
   8.399 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
   8.400 +    end
   8.401 +endgenerate
   8.402 +
   8.403 +// On the last refill cycle set the valid bit, for all other writes it should be cleared
   8.404 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
   8.405 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
   8.406 +
   8.407 +// Signals that indicate which state we are in
   8.408 +assign flushing = state[0];
   8.409 +assign check = state[1];
   8.410 +assign refill = state[2];
   8.411 +
   8.412 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
   8.413 +assign stall_request = (check == `FALSE);
   8.414 +                      
   8.415 +/////////////////////////////////////////////////////
   8.416 +// Sequential logic
   8.417 +/////////////////////////////////////////////////////
   8.418 +
   8.419 +// Record way selected for replacement on a cache miss
   8.420 +generate
   8.421 +    if (associativity >= 2) 
   8.422 +    begin : way_select      
   8.423 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.424 +begin
   8.425 +    if (rst_i == `TRUE)
   8.426 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
   8.427 +    else
   8.428 +    begin        
   8.429 +        if (refill_request == `TRUE)
   8.430 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
   8.431 +    end
   8.432 +end
   8.433 +    end 
   8.434 +endgenerate   
   8.435 +
   8.436 +// Record whether we are currently refilling
   8.437 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.438 +begin
   8.439 +    if (rst_i == `TRUE)
   8.440 +        refilling <= `FALSE;
   8.441 +    else 
   8.442 +        refilling <= refill;
   8.443 +end
   8.444 +
   8.445 +// Instruction cache control FSM
   8.446 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.447 +begin
   8.448 +    if (rst_i == `TRUE)
   8.449 +    begin
   8.450 +        state <= `LM32_DC_STATE_FLUSH;
   8.451 +        flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
   8.452 +        refill_request <= `FALSE;
   8.453 +        refill_address <= {`LM32_WORD_WIDTH{1'bx}};
   8.454 +        restart_request <= `FALSE;
   8.455 +    end
   8.456 +    else 
   8.457 +    begin
   8.458 +        case (state)
   8.459 +
   8.460 +        // Flush the cache 
   8.461 +        `LM32_DC_STATE_FLUSH:
   8.462 +        begin
   8.463 +            if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
   8.464 +                state <= `LM32_DC_STATE_CHECK;
   8.465 +            flush_set <= flush_set - 1'b1;
   8.466 +        end
   8.467 +        
   8.468 +        // Check for cache misses
   8.469 +        `LM32_DC_STATE_CHECK:
   8.470 +        begin
   8.471 +            if (stall_a == `FALSE)
   8.472 +                restart_request <= `FALSE;
   8.473 +            if (miss == `TRUE)
   8.474 +            begin
   8.475 +                refill_request <= `TRUE;
   8.476 +                refill_address <= address_m;
   8.477 +                state <= `LM32_DC_STATE_REFILL;
   8.478 +            end
   8.479 +            else if (dflush == `TRUE)
   8.480 +                state <= `LM32_DC_STATE_FLUSH;
   8.481 +        end
   8.482 +
   8.483 +        // Refill a cache line
   8.484 +        `LM32_DC_STATE_REFILL:
   8.485 +        begin
   8.486 +            refill_request <= `FALSE;
   8.487 +            if (refill_ready == `TRUE)
   8.488 +            begin
   8.489 +                if (last_refill == `TRUE)
   8.490 +                begin
   8.491 +                    restart_request <= `TRUE;
   8.492 +                    state <= `LM32_DC_STATE_CHECK;
   8.493 +                end
   8.494 +            end
   8.495 +        end
   8.496 +        
   8.497 +        endcase        
   8.498 +    end
   8.499 +end
   8.500 +
   8.501 +generate
   8.502 +    if (bytes_per_line > 4)
   8.503 +    begin
   8.504 +// Refill offset
   8.505 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   8.506 +begin
   8.507 +    if (rst_i == `TRUE)
   8.508 +        refill_offset <= {addr_offset_width{1'b0}};
   8.509 +    else 
   8.510 +    begin
   8.511 +        case (state)
   8.512 +        
   8.513 +        // Check for cache misses
   8.514 +        `LM32_DC_STATE_CHECK:
   8.515 +        begin
   8.516 +            if (miss == `TRUE)
   8.517 +                refill_offset <= {addr_offset_width{1'b0}};
   8.518 +        end
   8.519 +
   8.520 +        // Refill a cache line
   8.521 +        `LM32_DC_STATE_REFILL:
   8.522 +        begin
   8.523 +            if (refill_ready == `TRUE)
   8.524 +                refill_offset <= refill_offset + 1'b1;
   8.525 +        end
   8.526 +        
   8.527 +        endcase        
   8.528 +    end
   8.529 +end
   8.530 +    end
   8.531 +endgenerate
   8.532 +
   8.533 +endmodule
   8.534 +
   8.535 +`endif
   8.536 +
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/lm32_debug.v	Sun Apr 04 20:40:03 2010 +0100
     9.3 @@ -0,0 +1,348 @@
     9.4 +// =============================================================================
     9.5 +//                           COPYRIGHT NOTICE
     9.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     9.7 +// ALL RIGHTS RESERVED
     9.8 +// This confidential and proprietary software may be used only as authorised by
     9.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    9.10 +// The entire notice above must be reproduced on all authorized copies and
    9.11 +// copies may only be made to the extent permitted by a licensing agreement from
    9.12 +// Lattice Semiconductor Corporation.
    9.13 +//
    9.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    9.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    9.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    9.17 +// U.S.A                                   email: techsupport@latticesemi.com
    9.18 +// =============================================================================/
    9.19 +//                         FILE DETAILS
    9.20 +// Project          : LatticeMico32
    9.21 +// File             : lm32_debug.v
    9.22 +// Title            : Hardware debug registers and associated logic.
    9.23 +// Dependencies     : lm32_include.v
    9.24 +// Version          : 6.1.17
    9.25 +//                  : Initial Release
    9.26 +// Version          : 7.0SP2, 3.0
    9.27 +//                  : No Change
    9.28 +// Version          : 3.1
    9.29 +//                  : No Change
    9.30 +// Version          : 3.2
    9.31 +//                  : Fixed simulation bug which flares up when number of 
    9.32 +//                  : watchpoints is zero.
    9.33 +// =============================================================================
    9.34 +
    9.35 +`include "lm32_include.v"
    9.36 +
    9.37 +`ifdef CFG_DEBUG_ENABLED
    9.38 +
    9.39 +// States for single-step FSM
    9.40 +`define LM32_DEBUG_SS_STATE_RNG                 2:0
    9.41 +`define LM32_DEBUG_SS_STATE_IDLE                3'b000
    9.42 +`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
    9.43 +`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
    9.44 +`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
    9.45 +`define LM32_DEBUG_SS_STATE_RESTART             3'b100
    9.46 +
    9.47 +/////////////////////////////////////////////////////
    9.48 +// Module interface
    9.49 +/////////////////////////////////////////////////////
    9.50 +
    9.51 +module lm32_debug (
    9.52 +    // ----- Inputs -------
    9.53 +    clk_i, 
    9.54 +    rst_i,
    9.55 +    pc_x,
    9.56 +    load_x,
    9.57 +    store_x,
    9.58 +    load_store_address_x,
    9.59 +    csr_write_enable_x,
    9.60 +    csr_write_data,
    9.61 +    csr_x,
    9.62 +`ifdef CFG_HW_DEBUG_ENABLED
    9.63 +    jtag_csr_write_enable,
    9.64 +    jtag_csr_write_data,
    9.65 +    jtag_csr,
    9.66 +`endif
    9.67 +`ifdef LM32_SINGLE_STEP_ENABLED
    9.68 +    eret_q_x,
    9.69 +    bret_q_x,
    9.70 +    stall_x,
    9.71 +    exception_x,
    9.72 +    q_x,
    9.73 +`ifdef CFG_DCACHE_ENABLED
    9.74 +    dcache_refill_request,
    9.75 +`endif
    9.76 +`endif
    9.77 +    // ----- Outputs -------
    9.78 +`ifdef LM32_SINGLE_STEP_ENABLED
    9.79 +    dc_ss,
    9.80 +`endif
    9.81 +    dc_re,
    9.82 +    bp_match,
    9.83 +    wp_match
    9.84 +    );
    9.85 +    
    9.86 +/////////////////////////////////////////////////////
    9.87 +// Parameters
    9.88 +/////////////////////////////////////////////////////
    9.89 +
    9.90 +parameter breakpoints = 0;                      // Number of breakpoint CSRs
    9.91 +parameter watchpoints = 0;                      // Number of watchpoint CSRs
    9.92 +
    9.93 +/////////////////////////////////////////////////////
    9.94 +// Inputs
    9.95 +/////////////////////////////////////////////////////
    9.96 +
    9.97 +input clk_i;                                    // Clock
    9.98 +input rst_i;                                    // Reset
    9.99 +
   9.100 +input [`LM32_PC_RNG] pc_x;                      // X stage PC
   9.101 +input load_x;                                   // Load instruction in X stage
   9.102 +input store_x;                                  // Store instruction in X stage
   9.103 +input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
   9.104 +input csr_write_enable_x;                       // wcsr instruction in X stage
   9.105 +input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
   9.106 +input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
   9.107 +`ifdef CFG_HW_DEBUG_ENABLED
   9.108 +input jtag_csr_write_enable;                    // JTAG interface CSR write enable
   9.109 +input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
   9.110 +input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
   9.111 +`endif
   9.112 +`ifdef LM32_SINGLE_STEP_ENABLED
   9.113 +input eret_q_x;                                 // eret instruction in X stage
   9.114 +input bret_q_x;                                 // bret instruction in X stage
   9.115 +input stall_x;                                  // Instruction in X stage is stalled
   9.116 +input exception_x;                              // An exception has occured in X stage 
   9.117 +input q_x;                                      // Indicates the instruction in the X stage is qualified
   9.118 +`ifdef CFG_DCACHE_ENABLED
   9.119 +input dcache_refill_request;                    // Indicates data cache wants to be refilled 
   9.120 +`endif
   9.121 +`endif
   9.122 +
   9.123 +/////////////////////////////////////////////////////
   9.124 +// Outputs
   9.125 +/////////////////////////////////////////////////////
   9.126 +
   9.127 +`ifdef LM32_SINGLE_STEP_ENABLED
   9.128 +output dc_ss;                                   // Single-step enable
   9.129 +reg    dc_ss;
   9.130 +`endif
   9.131 +output dc_re;                                   // Remap exceptions
   9.132 +reg    dc_re;
   9.133 +output bp_match;                                // Indicates a breakpoint has matched
   9.134 +wire   bp_match;        
   9.135 +output wp_match;                                // Indicates a watchpoint has matched
   9.136 +wire   wp_match;
   9.137 +
   9.138 +/////////////////////////////////////////////////////
   9.139 +// Internal nets and registers 
   9.140 +/////////////////////////////////////////////////////
   9.141 +
   9.142 +genvar i;                                       // Loop index for generate statements
   9.143 +
   9.144 +// Debug CSRs
   9.145 +
   9.146 +reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
   9.147 +reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
   9.148 +wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
   9.149 +
   9.150 +reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
   9.151 +reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
   9.152 +wire [0:watchpoints]wp_match_n;               // Indicates if a h/w data watchpoint matched
   9.153 +
   9.154 +wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
   9.155 +wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
   9.156 +wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
   9.157 +
   9.158 +`ifdef LM32_SINGLE_STEP_ENABLED
   9.159 +// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
   9.160 +//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
   9.161 +integer state;                                  // State of single-step FSM
   9.162 +`endif
   9.163 +
   9.164 +/////////////////////////////////////////////////////
   9.165 +// Functions
   9.166 +/////////////////////////////////////////////////////
   9.167 +
   9.168 +`include "lm32_functions.v"
   9.169 +
   9.170 +/////////////////////////////////////////////////////
   9.171 +// Combinational Logic
   9.172 +/////////////////////////////////////////////////////
   9.173 +
   9.174 +// Check for breakpoints
   9.175 +generate
   9.176 +    for (i = 0; i < breakpoints; i = i + 1)
   9.177 +    begin : bp_comb
   9.178 +assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
   9.179 +    end
   9.180 +endgenerate
   9.181 +generate 
   9.182 +`ifdef LM32_SINGLE_STEP_ENABLED
   9.183 +    if (breakpoints > 0) 
   9.184 +assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
   9.185 +    else
   9.186 +assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
   9.187 +`else
   9.188 +    if (breakpoints > 0) 
   9.189 +assign bp_match = |bp_match_n;
   9.190 +    else
   9.191 +assign bp_match = `FALSE;
   9.192 +`endif
   9.193 +endgenerate    
   9.194 +               
   9.195 +// Check for watchpoints
   9.196 +generate 
   9.197 +    for (i = 0; i < watchpoints; i = i + 1)
   9.198 +    begin : wp_comb
   9.199 +assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
   9.200 +    end               
   9.201 +endgenerate
   9.202 +generate
   9.203 +    if (watchpoints > 0) 
   9.204 +assign wp_match = |wp_match_n;                
   9.205 +    else
   9.206 +assign wp_match = `FALSE;
   9.207 +endgenerate
   9.208 +                
   9.209 +`ifdef CFG_HW_DEBUG_ENABLED                
   9.210 +// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
   9.211 +assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
   9.212 +assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
   9.213 +assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
   9.214 +`else
   9.215 +assign debug_csr_write_enable = csr_write_enable_x;
   9.216 +assign debug_csr_write_data = csr_write_data;
   9.217 +assign debug_csr = csr_x;
   9.218 +`endif
   9.219 +
   9.220 +/////////////////////////////////////////////////////
   9.221 +// Sequential Logic
   9.222 +/////////////////////////////////////////////////////
   9.223 +
   9.224 +// Breakpoint address and enable CSRs
   9.225 +generate
   9.226 +    for (i = 0; i < breakpoints; i = i + 1)
   9.227 +    begin : bp_seq
   9.228 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   9.229 +begin
   9.230 +    if (rst_i == `TRUE)
   9.231 +    begin
   9.232 +        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
   9.233 +        bp_e[i] <= `FALSE;
   9.234 +    end
   9.235 +    else
   9.236 +    begin
   9.237 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
   9.238 +        begin
   9.239 +            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
   9.240 +            bp_e[i] <= debug_csr_write_data[0];
   9.241 +        end
   9.242 +    end
   9.243 +end    
   9.244 +    end
   9.245 +endgenerate
   9.246 +
   9.247 +// Watchpoint address and control flags CSRs
   9.248 +generate
   9.249 +    for (i = 0; i < watchpoints; i = i + 1)
   9.250 +    begin : wp_seq
   9.251 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   9.252 +begin
   9.253 +    if (rst_i == `TRUE)
   9.254 +    begin
   9.255 +        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
   9.256 +        wpc_c[i] <= `LM32_WPC_C_DISABLED;
   9.257 +    end
   9.258 +    else
   9.259 +    begin
   9.260 +        if (debug_csr_write_enable == `TRUE)
   9.261 +        begin
   9.262 +            if (debug_csr == `LM32_CSR_DC)
   9.263 +                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
   9.264 +            if (debug_csr == `LM32_CSR_WP0 + i)
   9.265 +                wp[i] <= debug_csr_write_data;
   9.266 +        end
   9.267 +    end  
   9.268 +end
   9.269 +    end
   9.270 +endgenerate
   9.271 +
   9.272 +// Remap exceptions control bit
   9.273 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   9.274 +begin
   9.275 +    if (rst_i == `TRUE)
   9.276 +        dc_re <= `FALSE;
   9.277 +    else
   9.278 +    begin
   9.279 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
   9.280 +            dc_re <= debug_csr_write_data[1];
   9.281 +    end
   9.282 +end    
   9.283 +
   9.284 +`ifdef LM32_SINGLE_STEP_ENABLED
   9.285 +// Single-step control flag
   9.286 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   9.287 +begin
   9.288 +    if (rst_i == `TRUE)
   9.289 +    begin
   9.290 +        state <= `LM32_DEBUG_SS_STATE_IDLE;
   9.291 +        dc_ss <= `FALSE;
   9.292 +    end
   9.293 +    else
   9.294 +    begin
   9.295 +        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
   9.296 +        begin
   9.297 +            dc_ss <= debug_csr_write_data[0];
   9.298 +            if (debug_csr_write_data[0] == `FALSE) 
   9.299 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
   9.300 +            else 
   9.301 +                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
   9.302 +        end
   9.303 +        case (state)
   9.304 +        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
   9.305 +        begin
   9.306 +            // Wait for eret or bret instruction to be executed
   9.307 +            if (   (   (eret_q_x == `TRUE)
   9.308 +                    || (bret_q_x == `TRUE)
   9.309 +                    )
   9.310 +                && (stall_x == `FALSE)
   9.311 +               )
   9.312 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
   9.313 +        end
   9.314 +        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
   9.315 +        begin
   9.316 +            // Wait for an instruction to be executed
   9.317 +            if ((q_x == `TRUE) && (stall_x == `FALSE))
   9.318 +                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
   9.319 +        end
   9.320 +        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
   9.321 +        begin
   9.322 +            // Wait for exception to be raised
   9.323 +`ifdef CFG_DCACHE_ENABLED
   9.324 +            if (dcache_refill_request == `TRUE)
   9.325 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   9.326 +            else 
   9.327 +`endif
   9.328 +                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
   9.329 +            begin
   9.330 +                dc_ss <= `FALSE;
   9.331 +                state <= `LM32_DEBUG_SS_STATE_RESTART;
   9.332 +            end
   9.333 +        end
   9.334 +        `LM32_DEBUG_SS_STATE_RESTART:
   9.335 +        begin
   9.336 +            // Watch to see if stepped instruction is restarted due to a cache miss
   9.337 +`ifdef CFG_DCACHE_ENABLED
   9.338 +            if (dcache_refill_request == `TRUE)
   9.339 +                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   9.340 +            else 
   9.341 +`endif
   9.342 +                state <= `LM32_DEBUG_SS_STATE_IDLE;
   9.343 +        end
   9.344 +        endcase
   9.345 +    end
   9.346 +end
   9.347 +`endif
   9.348 +
   9.349 +endmodule
   9.350 +
   9.351 +`endif
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/lm32_decoder.v	Sun Apr 04 20:40:03 2010 +0100
    10.3 @@ -0,0 +1,583 @@
    10.4 +// =============================================================================
    10.5 +//                           COPYRIGHT NOTICE
    10.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    10.7 +// ALL RIGHTS RESERVED
    10.8 +// This confidential and proprietary software may be used only as authorised by
    10.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   10.10 +// The entire notice above must be reproduced on all authorized copies and
   10.11 +// copies may only be made to the extent permitted by a licensing agreement from
   10.12 +// Lattice Semiconductor Corporation.
   10.13 +//
   10.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   10.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   10.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   10.17 +// U.S.A                                   email: techsupport@latticesemi.com
   10.18 +// =============================================================================/
   10.19 +//                         FILE DETAILS
   10.20 +// Project          : LatticeMico32
   10.21 +// File             : lm32_decoder.v
   10.22 +// Title            : Instruction decoder
   10.23 +// Dependencies     : lm32_include.v
   10.24 +// Version          : 6.1.17
   10.25 +//                  : Initial Release
   10.26 +// Version          : 7.0SP2, 3.0
   10.27 +//                  : No Change
   10.28 +// Version          : 3.1
   10.29 +//                  : Support for static branch prediction. Information about
   10.30 +//                  : branch type is generated and passed on to the predictor.
   10.31 +// Version          : 3.2
   10.32 +//                  : No change
   10.33 +// Version          : 3.3
   10.34 +//                  : Renamed port names that conflict with keywords reserved
   10.35 +//                  : in System-Verilog.
   10.36 +// =============================================================================
   10.37 +
   10.38 +`include "lm32_include.v"
   10.39 +
   10.40 +// Index of opcode field in an instruction
   10.41 +`define LM32_OPCODE_RNG         31:26
   10.42 +`define LM32_OP_RNG             30:26
   10.43 +
   10.44 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
   10.45 +`define LM32_OPCODE_ADD         5'b01101
   10.46 +`define LM32_OPCODE_AND         5'b01000
   10.47 +`define LM32_OPCODE_ANDHI       6'b011000
   10.48 +`define LM32_OPCODE_B           6'b110000
   10.49 +`define LM32_OPCODE_BI          6'b111000
   10.50 +`define LM32_OPCODE_BE          6'b010001
   10.51 +`define LM32_OPCODE_BG          6'b010010
   10.52 +`define LM32_OPCODE_BGE         6'b010011
   10.53 +`define LM32_OPCODE_BGEU        6'b010100
   10.54 +`define LM32_OPCODE_BGU         6'b010101
   10.55 +`define LM32_OPCODE_BNE         6'b010111
   10.56 +`define LM32_OPCODE_CALL        6'b110110
   10.57 +`define LM32_OPCODE_CALLI       6'b111110
   10.58 +`define LM32_OPCODE_CMPE        5'b11001
   10.59 +`define LM32_OPCODE_CMPG        5'b11010
   10.60 +`define LM32_OPCODE_CMPGE       5'b11011
   10.61 +`define LM32_OPCODE_CMPGEU      5'b11100
   10.62 +`define LM32_OPCODE_CMPGU       5'b11101
   10.63 +`define LM32_OPCODE_CMPNE       5'b11111
   10.64 +`define LM32_OPCODE_DIVU        6'b100011
   10.65 +`define LM32_OPCODE_LB          6'b000100
   10.66 +`define LM32_OPCODE_LBU         6'b010000
   10.67 +`define LM32_OPCODE_LH          6'b000111
   10.68 +`define LM32_OPCODE_LHU         6'b001011
   10.69 +`define LM32_OPCODE_LW          6'b001010
   10.70 +`define LM32_OPCODE_MODU        6'b110001
   10.71 +`define LM32_OPCODE_MUL         5'b00010
   10.72 +`define LM32_OPCODE_NOR         5'b00001
   10.73 +`define LM32_OPCODE_OR          5'b01110
   10.74 +`define LM32_OPCODE_ORHI        6'b011110
   10.75 +`define LM32_OPCODE_RAISE       6'b101011
   10.76 +`define LM32_OPCODE_RCSR        6'b100100
   10.77 +`define LM32_OPCODE_SB          6'b001100
   10.78 +`define LM32_OPCODE_SEXTB       6'b101100
   10.79 +`define LM32_OPCODE_SEXTH       6'b110111
   10.80 +`define LM32_OPCODE_SH          6'b000011
   10.81 +`define LM32_OPCODE_SL          5'b01111
   10.82 +`define LM32_OPCODE_SR          5'b00101
   10.83 +`define LM32_OPCODE_SRU         5'b00000
   10.84 +`define LM32_OPCODE_SUB         6'b110010
   10.85 +`define LM32_OPCODE_SW          6'b010110
   10.86 +`define LM32_OPCODE_USER        6'b110011
   10.87 +`define LM32_OPCODE_WCSR        6'b110100
   10.88 +`define LM32_OPCODE_XNOR        5'b01001
   10.89 +`define LM32_OPCODE_XOR         5'b00110
   10.90 +
   10.91 +/////////////////////////////////////////////////////
   10.92 +// Module interface
   10.93 +/////////////////////////////////////////////////////
   10.94 +
   10.95 +module lm32_decoder (
   10.96 +    // ----- Inputs -------
   10.97 +    instruction,
   10.98 +    // ----- Outputs -------
   10.99 +    d_result_sel_0,
  10.100 +    d_result_sel_1,        
  10.101 +    x_result_sel_csr,
  10.102 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  10.103 +    x_result_sel_mc_arith,
  10.104 +`endif    
  10.105 +`ifdef LM32_NO_BARREL_SHIFT    
  10.106 +    x_result_sel_shift,
  10.107 +`endif
  10.108 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.109 +    x_result_sel_sext,
  10.110 +`endif    
  10.111 +    x_result_sel_logic,
  10.112 +`ifdef CFG_USER_ENABLED
  10.113 +    x_result_sel_user,
  10.114 +`endif
  10.115 +    x_result_sel_add,
  10.116 +    m_result_sel_compare,
  10.117 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.118 +    m_result_sel_shift,  
  10.119 +`endif    
  10.120 +    w_result_sel_load,
  10.121 +`ifdef CFG_PL_MULTIPLY_ENABLED
  10.122 +    w_result_sel_mul,
  10.123 +`endif
  10.124 +    x_bypass_enable,
  10.125 +    m_bypass_enable,
  10.126 +    read_enable_0,
  10.127 +    read_idx_0,
  10.128 +    read_enable_1,
  10.129 +    read_idx_1,
  10.130 +    write_enable,
  10.131 +    write_idx,
  10.132 +    immediate,
  10.133 +    branch_offset,
  10.134 +    load,
  10.135 +    store,
  10.136 +    size,
  10.137 +    sign_extend,
  10.138 +    adder_op,
  10.139 +    logic_op,
  10.140 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.141 +    direction,
  10.142 +`endif
  10.143 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  10.144 +    shift_left,
  10.145 +    shift_right,
  10.146 +`endif
  10.147 +`ifdef CFG_MC_MULTIPLY_ENABLED
  10.148 +    multiply,
  10.149 +`endif
  10.150 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.151 +    divide,
  10.152 +    modulus,
  10.153 +`endif
  10.154 +    branch,
  10.155 +    branch_reg,
  10.156 +    condition,
  10.157 +    bi_conditional,
  10.158 +    bi_unconditional,
  10.159 +`ifdef CFG_DEBUG_ENABLED
  10.160 +    break_opcode,
  10.161 +`endif
  10.162 +    scall,
  10.163 +    eret,
  10.164 +`ifdef CFG_DEBUG_ENABLED
  10.165 +    bret,
  10.166 +`endif
  10.167 +`ifdef CFG_USER_ENABLED
  10.168 +    user_opcode,
  10.169 +`endif
  10.170 +    csr_write_enable
  10.171 +    );
  10.172 +
  10.173 +/////////////////////////////////////////////////////
  10.174 +// Inputs
  10.175 +/////////////////////////////////////////////////////
  10.176 +
  10.177 +input [`LM32_INSTRUCTION_RNG] instruction;       // Instruction to decode
  10.178 +
  10.179 +/////////////////////////////////////////////////////
  10.180 +// Outputs
  10.181 +/////////////////////////////////////////////////////
  10.182 +
  10.183 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  10.184 +reg    [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
  10.185 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  10.186 +reg    [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
  10.187 +output x_result_sel_csr;
  10.188 +reg    x_result_sel_csr;
  10.189 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  10.190 +output x_result_sel_mc_arith;
  10.191 +reg    x_result_sel_mc_arith;
  10.192 +`endif
  10.193 +`ifdef LM32_NO_BARREL_SHIFT    
  10.194 +output x_result_sel_shift;
  10.195 +reg    x_result_sel_shift;
  10.196 +`endif
  10.197 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.198 +output x_result_sel_sext;
  10.199 +reg    x_result_sel_sext;
  10.200 +`endif
  10.201 +output x_result_sel_logic;
  10.202 +reg    x_result_sel_logic;
  10.203 +`ifdef CFG_USER_ENABLED
  10.204 +output x_result_sel_user;
  10.205 +reg    x_result_sel_user;
  10.206 +`endif
  10.207 +output x_result_sel_add;
  10.208 +reg    x_result_sel_add;
  10.209 +output m_result_sel_compare;
  10.210 +reg    m_result_sel_compare;
  10.211 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.212 +output m_result_sel_shift;
  10.213 +reg    m_result_sel_shift;
  10.214 +`endif
  10.215 +output w_result_sel_load;
  10.216 +reg    w_result_sel_load;
  10.217 +`ifdef CFG_PL_MULTIPLY_ENABLED
  10.218 +output w_result_sel_mul;
  10.219 +reg    w_result_sel_mul;
  10.220 +`endif
  10.221 +output x_bypass_enable;
  10.222 +wire   x_bypass_enable;
  10.223 +output m_bypass_enable;
  10.224 +wire   m_bypass_enable;
  10.225 +output read_enable_0;
  10.226 +wire   read_enable_0;
  10.227 +output [`LM32_REG_IDX_RNG] read_idx_0;
  10.228 +wire   [`LM32_REG_IDX_RNG] read_idx_0;
  10.229 +output read_enable_1;
  10.230 +wire   read_enable_1;
  10.231 +output [`LM32_REG_IDX_RNG] read_idx_1;
  10.232 +wire   [`LM32_REG_IDX_RNG] read_idx_1;
  10.233 +output write_enable;
  10.234 +wire   write_enable;
  10.235 +output [`LM32_REG_IDX_RNG] write_idx;
  10.236 +wire   [`LM32_REG_IDX_RNG] write_idx;
  10.237 +output [`LM32_WORD_RNG] immediate;
  10.238 +wire   [`LM32_WORD_RNG] immediate;
  10.239 +output [`LM32_PC_RNG] branch_offset;
  10.240 +wire   [`LM32_PC_RNG] branch_offset;
  10.241 +output load;
  10.242 +wire   load;
  10.243 +output store;
  10.244 +wire   store;
  10.245 +output [`LM32_SIZE_RNG] size;
  10.246 +wire   [`LM32_SIZE_RNG] size;
  10.247 +output sign_extend;
  10.248 +wire   sign_extend;
  10.249 +output adder_op;
  10.250 +wire   adder_op;
  10.251 +output [`LM32_LOGIC_OP_RNG] logic_op;
  10.252 +wire   [`LM32_LOGIC_OP_RNG] logic_op;
  10.253 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.254 +output direction;
  10.255 +wire   direction;
  10.256 +`endif
  10.257 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  10.258 +output shift_left;
  10.259 +wire   shift_left;
  10.260 +output shift_right;
  10.261 +wire   shift_right;
  10.262 +`endif
  10.263 +`ifdef CFG_MC_MULTIPLY_ENABLED
  10.264 +output multiply;
  10.265 +wire   multiply;
  10.266 +`endif
  10.267 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.268 +output divide;
  10.269 +wire   divide;
  10.270 +output modulus;
  10.271 +wire   modulus;
  10.272 +`endif
  10.273 +output branch;
  10.274 +wire   branch;
  10.275 +output branch_reg;
  10.276 +wire   branch_reg;
  10.277 +output [`LM32_CONDITION_RNG] condition;
  10.278 +wire   [`LM32_CONDITION_RNG] condition;
  10.279 +output bi_conditional;
  10.280 +wire bi_conditional;
  10.281 +output bi_unconditional;
  10.282 +wire bi_unconditional;
  10.283 +`ifdef CFG_DEBUG_ENABLED
  10.284 +output break_opcode;
  10.285 +wire   break_opcode;
  10.286 +`endif
  10.287 +output scall;
  10.288 +wire   scall;
  10.289 +output eret;
  10.290 +wire   eret;
  10.291 +`ifdef CFG_DEBUG_ENABLED
  10.292 +output bret;
  10.293 +wire   bret;
  10.294 +`endif
  10.295 +`ifdef CFG_USER_ENABLED
  10.296 +output [`LM32_USER_OPCODE_RNG] user_opcode;
  10.297 +wire   [`LM32_USER_OPCODE_RNG] user_opcode;
  10.298 +`endif
  10.299 +output csr_write_enable;
  10.300 +wire   csr_write_enable;
  10.301 +
  10.302 +/////////////////////////////////////////////////////
  10.303 +// Internal nets and registers 
  10.304 +/////////////////////////////////////////////////////
  10.305 +
  10.306 +wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
  10.307 +wire [`LM32_WORD_RNG] high_immediate;           // Immediate as high 16 bits
  10.308 +wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
  10.309 +wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
  10.310 +wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
  10.311 +wire select_high_immediate;                     // Whether to select the high immediate  
  10.312 +wire select_call_immediate;                     // Whether to select the call immediate 
  10.313 +
  10.314 +/////////////////////////////////////////////////////
  10.315 +// Functions
  10.316 +/////////////////////////////////////////////////////
  10.317 +
  10.318 +`include "lm32_functions.v"
  10.319 +
  10.320 +/////////////////////////////////////////////////////
  10.321 +// Combinational logic
  10.322 +/////////////////////////////////////////////////////
  10.323 +
  10.324 +// Determine opcode
  10.325 +assign op_add    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
  10.326 +assign op_and    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
  10.327 +assign op_andhi  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
  10.328 +assign op_b      = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
  10.329 +assign op_bi     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
  10.330 +assign op_be     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
  10.331 +assign op_bg     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
  10.332 +assign op_bge    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
  10.333 +assign op_bgeu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
  10.334 +assign op_bgu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
  10.335 +assign op_bne    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
  10.336 +assign op_call   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
  10.337 +assign op_calli  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
  10.338 +assign op_cmpe   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
  10.339 +assign op_cmpg   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
  10.340 +assign op_cmpge  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
  10.341 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
  10.342 +assign op_cmpgu  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
  10.343 +assign op_cmpne  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
  10.344 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.345 +assign op_divu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
  10.346 +`endif
  10.347 +assign op_lb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
  10.348 +assign op_lbu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
  10.349 +assign op_lh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
  10.350 +assign op_lhu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
  10.351 +assign op_lw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
  10.352 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.353 +assign op_modu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
  10.354 +`endif
  10.355 +`ifdef LM32_MULTIPLY_ENABLED
  10.356 +assign op_mul    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
  10.357 +`endif
  10.358 +assign op_nor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
  10.359 +assign op_or     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
  10.360 +assign op_orhi   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
  10.361 +assign op_raise  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
  10.362 +assign op_rcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
  10.363 +assign op_sb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
  10.364 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.365 +assign op_sextb  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
  10.366 +assign op_sexth  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
  10.367 +`endif
  10.368 +assign op_sh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
  10.369 +`ifdef LM32_BARREL_SHIFT_ENABLED
  10.370 +assign op_sl     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;      
  10.371 +`endif
  10.372 +assign op_sr     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
  10.373 +assign op_sru    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
  10.374 +assign op_sub    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
  10.375 +assign op_sw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
  10.376 +assign op_user   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
  10.377 +assign op_wcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
  10.378 +assign op_xnor   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
  10.379 +assign op_xor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
  10.380 +
  10.381 +// Group opcodes by function
  10.382 +assign arith = op_add | op_sub;
  10.383 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
  10.384 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
  10.385 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
  10.386 +assign bi_unconditional = op_bi;
  10.387 +assign bra = op_b | bi_unconditional | bi_conditional;
  10.388 +assign call = op_call | op_calli;
  10.389 +`ifdef LM32_BARREL_SHIFT_ENABLED
  10.390 +assign shift = op_sl | op_sr | op_sru;
  10.391 +`endif
  10.392 +`ifdef LM32_NO_BARREL_SHIFT
  10.393 +assign shift = op_sr | op_sru;
  10.394 +`endif
  10.395 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  10.396 +assign shift_left = op_sl;
  10.397 +assign shift_right = op_sr | op_sru;
  10.398 +`endif
  10.399 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.400 +assign sext = op_sextb | op_sexth;
  10.401 +`endif
  10.402 +`ifdef LM32_MULTIPLY_ENABLED
  10.403 +assign multiply = op_mul;
  10.404 +`endif
  10.405 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.406 +assign divide = op_divu; 
  10.407 +assign modulus = op_modu;
  10.408 +`endif
  10.409 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
  10.410 +assign store = op_sb | op_sh | op_sw;
  10.411 +
  10.412 +// Select pipeline multiplexor controls
  10.413 +always @(*)
  10.414 +begin
  10.415 +    // D stage
  10.416 +    if (call) 
  10.417 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
  10.418 +    else 
  10.419 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
  10.420 +    if (call) 
  10.421 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;         
  10.422 +    else if ((instruction[31] == 1'b0) && !bra) 
  10.423 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
  10.424 +    else
  10.425 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 
  10.426 +    // X stage
  10.427 +    x_result_sel_csr = `FALSE;
  10.428 +`ifdef LM32_MC_ARITHMETIC_ENABLED
  10.429 +    x_result_sel_mc_arith = `FALSE;
  10.430 +`endif
  10.431 +`ifdef LM32_NO_BARREL_SHIFT
  10.432 +    x_result_sel_shift = `FALSE;
  10.433 +`endif
  10.434 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.435 +    x_result_sel_sext = `FALSE;
  10.436 +`endif
  10.437 +    x_result_sel_logic = `FALSE;
  10.438 +`ifdef CFG_USER_ENABLED        
  10.439 +    x_result_sel_user = `FALSE;
  10.440 +`endif
  10.441 +    x_result_sel_add = `FALSE;
  10.442 +    if (op_rcsr)
  10.443 +        x_result_sel_csr = `TRUE;
  10.444 +`ifdef LM32_MC_ARITHMETIC_ENABLED    
  10.445 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  10.446 +    else if (shift_left | shift_right) 
  10.447 +        x_result_sel_mc_arith = `TRUE;
  10.448 +`endif
  10.449 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.450 +    else if (divide | modulus)
  10.451 +        x_result_sel_mc_arith = `TRUE;        
  10.452 +`endif
  10.453 +`ifdef CFG_MC_MULTIPLY_ENABLED
  10.454 +    else if (multiply)
  10.455 +        x_result_sel_mc_arith = `TRUE;            
  10.456 +`endif
  10.457 +`endif
  10.458 +`ifdef LM32_NO_BARREL_SHIFT
  10.459 +    else if (shift)
  10.460 +        x_result_sel_shift = `TRUE;        
  10.461 +`endif
  10.462 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.463 +    else if (sext)
  10.464 +        x_result_sel_sext = `TRUE;
  10.465 +`endif        
  10.466 +    else if (logical) 
  10.467 +        x_result_sel_logic = `TRUE;
  10.468 +`ifdef CFG_USER_ENABLED        
  10.469 +    else if (op_user)
  10.470 +        x_result_sel_user = `TRUE;
  10.471 +`endif
  10.472 +    else 
  10.473 +        x_result_sel_add = `TRUE;        
  10.474 +    
  10.475 +    // M stage
  10.476 +
  10.477 +    m_result_sel_compare = cmp;
  10.478 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.479 +    m_result_sel_shift = shift;
  10.480 +`endif
  10.481 +
  10.482 +    // W stage
  10.483 +    w_result_sel_load = load;
  10.484 +`ifdef CFG_PL_MULTIPLY_ENABLED
  10.485 +    w_result_sel_mul = op_mul; 
  10.486 +`endif
  10.487 +end
  10.488 +
  10.489 +// Set if result is valid at end of X stage
  10.490 +assign x_bypass_enable =  arith 
  10.491 +                        | logical
  10.492 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  10.493 +                        | shift_left
  10.494 +                        | shift_right
  10.495 +`endif                        
  10.496 +`ifdef CFG_MC_MULTIPLY_ENABLED
  10.497 +                        | multiply
  10.498 +`endif
  10.499 +`ifdef CFG_MC_DIVIDE_ENABLED
  10.500 +                        | divide
  10.501 +                        | modulus
  10.502 +`endif
  10.503 +`ifdef LM32_NO_BARREL_SHIFT
  10.504 +                        | shift
  10.505 +`endif                  
  10.506 +`ifdef CFG_SIGN_EXTEND_ENABLED
  10.507 +                        | sext 
  10.508 +`endif                        
  10.509 +`ifdef CFG_USER_ENABLED
  10.510 +                        | op_user
  10.511 +`endif
  10.512 +                        | op_rcsr
  10.513 +                        ;
  10.514 +// Set if result is valid at end of M stage                        
  10.515 +assign m_bypass_enable = x_bypass_enable 
  10.516 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.517 +                        | shift
  10.518 +`endif
  10.519 +                        | cmp
  10.520 +                        ;
  10.521 +// Register file read port 0                        
  10.522 +assign read_enable_0 = ~(op_bi | op_calli);
  10.523 +assign read_idx_0 = instruction[25:21];
  10.524 +// Register file read port 1 
  10.525 +assign read_enable_1 = ~(op_bi | op_calli | load);
  10.526 +assign read_idx_1 = instruction[20:16];
  10.527 +// Register file write port
  10.528 +assign write_enable = ~(bra | op_raise | store | op_wcsr);
  10.529 +assign write_idx = call
  10.530 +                    ? 5'd29
  10.531 +                    : instruction[31] == 1'b0 
  10.532 +                        ? instruction[20:16] 
  10.533 +                        : instruction[15:11];
  10.534 +                        
  10.535 +// Size of load/stores                        
  10.536 +assign size = instruction[27:26];
  10.537 +// Whether to sign or zero extend
  10.538 +assign sign_extend = instruction[28];                      
  10.539 +// Set adder_op to 1 to perform a subtraction
  10.540 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
  10.541 +// Logic operation (and, or, etc)
  10.542 +assign logic_op = instruction[29:26];
  10.543 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  10.544 +// Shift direction
  10.545 +assign direction = instruction[29];
  10.546 +`endif
  10.547 +// Control flow microcodes
  10.548 +assign branch = bra | call;
  10.549 +assign branch_reg = op_call | op_b;
  10.550 +assign condition = instruction[28:26];      
  10.551 +`ifdef CFG_DEBUG_ENABLED
  10.552 +assign break_opcode = op_raise & ~instruction[2];
  10.553 +`endif
  10.554 +assign scall = op_raise & instruction[2];
  10.555 +assign eret = op_b & (instruction[25:21] == 5'd30);
  10.556 +`ifdef CFG_DEBUG_ENABLED
  10.557 +assign bret = op_b & (instruction[25:21] == 5'd31);
  10.558 +`endif
  10.559 +`ifdef CFG_USER_ENABLED
  10.560 +// Extract user opcode
  10.561 +assign user_opcode = instruction[10:0];
  10.562 +`endif
  10.563 +// CSR read/write
  10.564 +assign csr_write_enable = op_wcsr;
  10.565 +
  10.566 +// Extract immediate from instruction
  10.567 +
  10.568 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
  10.569 +assign select_high_immediate = op_andhi | op_orhi;
  10.570 +assign select_call_immediate = instruction[31];
  10.571 +
  10.572 +assign high_immediate = {instruction[15:0], 16'h0000};
  10.573 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
  10.574 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
  10.575 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
  10.576 +
  10.577 +assign immediate = select_high_immediate == `TRUE 
  10.578 +                        ? high_immediate 
  10.579 +                        : extended_immediate;
  10.580 +   
  10.581 +assign branch_offset = select_call_immediate == `TRUE   
  10.582 +                        ? call_immediate
  10.583 +                        : branch_immediate;
  10.584 +    
  10.585 +endmodule 
  10.586 +
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/lm32_functions.v	Sun Apr 04 20:40:03 2010 +0100
    11.3 @@ -0,0 +1,49 @@
    11.4 +// =============================================================================
    11.5 +//                           COPYRIGHT NOTICE
    11.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    11.7 +// ALL RIGHTS RESERVED
    11.8 +// This confidential and proprietary software may be used only as authorised by
    11.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   11.10 +// The entire notice above must be reproduced on all authorized copies and
   11.11 +// copies may only be made to the extent permitted by a licensing agreement from
   11.12 +// Lattice Semiconductor Corporation.
   11.13 +//
   11.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   11.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   11.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   11.17 +// U.S.A                                   email: techsupport@latticesemi.com
   11.18 +// =============================================================================/
   11.19 +//                         FILE DETAILS
   11.20 +// Project      : LatticeMico32
   11.21 +// File         : lm32_functions.v
   11.22 +// Title        : Common functions
   11.23 +// Version      : 6.1.17
   11.24 +//              : Initial Release
   11.25 +// Version      : 7.0SP2, 3.0
   11.26 +//              : No Change
   11.27 +// Version      : 3.5
   11.28 +//              : Added function to generate log-of-two that rounds-up to
   11.29 +//              : power-of-two
   11.30 +// =============================================================================
   11.31 +					  
   11.32 +function integer clogb2;
   11.33 +input [31:0] value;
   11.34 +begin
   11.35 +   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
   11.36 +        value = value >> 1;
   11.37 +end
   11.38 +endfunction 
   11.39 +
   11.40 +function integer clogb2_v1;
   11.41 +input [31:0] value;
   11.42 +reg   [31:0] i;
   11.43 +reg   [31:0] temp;
   11.44 +begin
   11.45 +   temp = 0;
   11.46 +   i    = 0;
   11.47 +   for (i = 0; temp < value; i = i + 1)  
   11.48 +	temp = 1<<i;
   11.49 +   clogb2_v1 = i-1;
   11.50 +end
   11.51 +endfunction
   11.52 +
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/lm32_icache.v	Sun Apr 04 20:40:03 2010 +0100
    12.3 @@ -0,0 +1,488 @@
    12.4 +// =============================================================================
    12.5 +//                           COPYRIGHT NOTICE
    12.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    12.7 +// ALL RIGHTS RESERVED
    12.8 +// This confidential and proprietary software may be used only as authorised by
    12.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   12.10 +// The entire notice above must be reproduced on all authorized copies and
   12.11 +// copies may only be made to the extent permitted by a licensing agreement from
   12.12 +// Lattice Semiconductor Corporation.
   12.13 +//
   12.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   12.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   12.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   12.17 +// U.S.A                                   email: techsupport@latticesemi.com
   12.18 +// =============================================================================/
   12.19 +//                         FILE DETAILS
   12.20 +// Project          : LatticeMico32
   12.21 +// File             : lm32_icache.v
   12.22 +// Title            : Instruction cache
   12.23 +// Dependencies     : lm32_include.v
   12.24 +// 
   12.25 +// Version 3.5
   12.26 +// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
   12.27 +//    cause segmentation fault due to incorrect fetches.
   12.28 +//
   12.29 +// Version 3.1
   12.30 +// 1. Feature: Support for user-selected resource usage when implementing
   12.31 +//    cache memory. Additional parameters must be defined when invoking module
   12.32 +//    lm32_ram. Instruction cache miss mechanism is dependent on branch
   12.33 +//    prediction being performed in D stage of pipeline.
   12.34 +//
   12.35 +// Version 7.0SP2, 3.0
   12.36 +// No change
   12.37 +// =============================================================================
   12.38 +					  
   12.39 +`include "lm32_include.v"
   12.40 +
   12.41 +`ifdef CFG_ICACHE_ENABLED
   12.42 +
   12.43 +`define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
   12.44 +`define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
   12.45 +`define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
   12.46 +`define LM32_IC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
   12.47 +
   12.48 +`define LM32_IC_TMEM_ADDR_WIDTH          addr_set_width
   12.49 +`define LM32_IC_TMEM_ADDR_RNG            (`LM32_IC_TMEM_ADDR_WIDTH-1):0
   12.50 +`define LM32_IC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
   12.51 +`define LM32_IC_DMEM_ADDR_RNG            (`LM32_IC_DMEM_ADDR_WIDTH-1):0
   12.52 +
   12.53 +`define LM32_IC_TAGS_WIDTH               (addr_tag_width+1)
   12.54 +`define LM32_IC_TAGS_RNG                 (`LM32_IC_TAGS_WIDTH-1):0
   12.55 +`define LM32_IC_TAGS_TAG_RNG             (`LM32_IC_TAGS_WIDTH-1):1
   12.56 +`define LM32_IC_TAGS_VALID_RNG           0
   12.57 +
   12.58 +`define LM32_IC_STATE_RNG                3:0
   12.59 +`define LM32_IC_STATE_FLUSH_INIT         4'b0001
   12.60 +`define LM32_IC_STATE_FLUSH              4'b0010
   12.61 +`define LM32_IC_STATE_CHECK              4'b0100
   12.62 +`define LM32_IC_STATE_REFILL             4'b1000
   12.63 +
   12.64 +/////////////////////////////////////////////////////
   12.65 +// Module interface
   12.66 +/////////////////////////////////////////////////////
   12.67 +
   12.68 +module lm32_icache ( 
   12.69 +    // ----- Inputs -----
   12.70 +    clk_i,
   12.71 +    rst_i,    
   12.72 +    stall_a,
   12.73 +    stall_f,
   12.74 +    address_a,
   12.75 +    address_f,
   12.76 +    read_enable_f,
   12.77 +    refill_ready,
   12.78 +    refill_data,
   12.79 +    iflush,
   12.80 +`ifdef CFG_IROM_ENABLED
   12.81 +    select_f,
   12.82 +`endif
   12.83 +    valid_d,
   12.84 +    branch_predict_taken_d,
   12.85 +    // ----- Outputs -----
   12.86 +    stall_request,
   12.87 +    restart_request,
   12.88 +    refill_request,
   12.89 +    refill_address,
   12.90 +    refilling,
   12.91 +    inst
   12.92 +    );
   12.93 +
   12.94 +/////////////////////////////////////////////////////
   12.95 +// Parameters
   12.96 +/////////////////////////////////////////////////////
   12.97 +
   12.98 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   12.99 +parameter sets = 512;                                   // Number of sets
  12.100 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  12.101 +parameter base_address = 0;                             // Base address of cachable memory
  12.102 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  12.103 +
  12.104 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
  12.105 +localparam addr_set_width = clogb2(sets)-1;
  12.106 +localparam addr_offset_lsb = 2;
  12.107 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  12.108 +localparam addr_set_lsb = (addr_offset_msb+1);
  12.109 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
  12.110 +localparam addr_tag_lsb = (addr_set_msb+1);
  12.111 +localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
  12.112 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
  12.113 +
  12.114 +/////////////////////////////////////////////////////
  12.115 +// Inputs
  12.116 +/////////////////////////////////////////////////////
  12.117 +
  12.118 +input clk_i;                                        // Clock 
  12.119 +input rst_i;                                        // Reset
  12.120 +
  12.121 +input stall_a;                                      // Stall instruction in A stage
  12.122 +input stall_f;                                      // Stall instruction in F stage
  12.123 +
  12.124 +input valid_d;                                      // Valid instruction in D stage
  12.125 +input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
  12.126 +   
  12.127 +input [`LM32_PC_RNG] address_a;                     // Address of instruction in A stage
  12.128 +input [`LM32_PC_RNG] address_f;                     // Address of instruction in F stage
  12.129 +input read_enable_f;                                // Indicates if cache access is valid
  12.130 +
  12.131 +input refill_ready;                                 // Next word of refill data is ready
  12.132 +input [`LM32_INSTRUCTION_RNG] refill_data;          // Data to refill the cache with
  12.133 +
  12.134 +input iflush;                                       // Flush the cache
  12.135 +`ifdef CFG_IROM_ENABLED
  12.136 +input select_f;                                     // Instruction in F stage is mapped through instruction cache
  12.137 +`endif
  12.138 +   
  12.139 +/////////////////////////////////////////////////////
  12.140 +// Outputs
  12.141 +/////////////////////////////////////////////////////
  12.142 +
  12.143 +output stall_request;                               // Request to stall the pipeline
  12.144 +wire   stall_request;
  12.145 +output restart_request;                             // Request to restart instruction that caused the cache miss
  12.146 +reg    restart_request;
  12.147 +output refill_request;                              // Request to refill a cache line
  12.148 +wire   refill_request;
  12.149 +output [`LM32_PC_RNG] refill_address;               // Base address of cache refill
  12.150 +reg    [`LM32_PC_RNG] refill_address;               
  12.151 +output refilling;                                   // Indicates the instruction cache is currently refilling
  12.152 +reg    refilling;
  12.153 +output [`LM32_INSTRUCTION_RNG] inst;                // Instruction read from cache
  12.154 +wire   [`LM32_INSTRUCTION_RNG] inst;
  12.155 +
  12.156 +/////////////////////////////////////////////////////
  12.157 +// Internal nets and registers 
  12.158 +/////////////////////////////////////////////////////
  12.159 +
  12.160 +wire enable;
  12.161 +wire [0:associativity-1] way_mem_we;
  12.162 +wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
  12.163 +wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
  12.164 +wire [0:associativity-1] way_valid;
  12.165 +wire [0:associativity-1] way_match;
  12.166 +wire miss;
  12.167 +
  12.168 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
  12.169 +wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
  12.170 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
  12.171 +wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
  12.172 +wire [`LM32_IC_TAGS_RNG] tmem_write_data;
  12.173 +
  12.174 +reg [`LM32_IC_STATE_RNG] state;
  12.175 +wire flushing;
  12.176 +wire check;
  12.177 +wire refill;
  12.178 +
  12.179 +reg [associativity-1:0] refill_way_select;
  12.180 +reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
  12.181 +wire last_refill;
  12.182 +reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
  12.183 +
  12.184 +genvar i;
  12.185 +
  12.186 +/////////////////////////////////////////////////////
  12.187 +// Functions
  12.188 +/////////////////////////////////////////////////////
  12.189 +
  12.190 +`include "lm32_functions.v"
  12.191 +
  12.192 +/////////////////////////////////////////////////////
  12.193 +// Instantiations
  12.194 +/////////////////////////////////////////////////////
  12.195 +
  12.196 +   generate
  12.197 +      for (i = 0; i < associativity; i = i + 1)
  12.198 +	begin : memories
  12.199 +	   
  12.200 +	   lm32_ram 
  12.201 +	     #(
  12.202 +	       // ----- Parameters -------
  12.203 +	       .data_width                 (32),
  12.204 +	       .address_width              (`LM32_IC_DMEM_ADDR_WIDTH),
  12.205 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  12.206 +	       .RAM_IMPLEMENTATION         ("EBR"),
  12.207 +	       .RAM_TYPE                   ("RAM_DP_TRUE")
  12.208 +`else
  12.209 + `ifdef CFG_ICACHE_DAT_USE_DP
  12.210 +	       .RAM_IMPLEMENTATION         ("EBR"),
  12.211 +	       .RAM_TYPE                   ("RAM_DP")
  12.212 + `else
  12.213 +  `ifdef CFG_ICACHE_DAT_USE_SLICE
  12.214 +	       .RAM_IMPLEMENTATION         ("SLICE")
  12.215 +  `else
  12.216 +	       .RAM_IMPLEMENTATION         ("AUTO")
  12.217 +  `endif
  12.218 + `endif
  12.219 +`endif
  12.220 +	       ) 
  12.221 +	   way_0_data_ram 
  12.222 +	     (
  12.223 +	      // ----- Inputs -------
  12.224 +	      .read_clk                   (clk_i),
  12.225 +	      .write_clk                  (clk_i),
  12.226 +	      .reset                      (rst_i),
  12.227 +	      .read_address               (dmem_read_address),
  12.228 +	      .enable_read                (enable),
  12.229 +	      .write_address              (dmem_write_address),
  12.230 +	      .enable_write               (`TRUE),
  12.231 +	      .write_enable               (way_mem_we[i]),
  12.232 +	      .write_data                 (refill_data),    
  12.233 +	      // ----- Outputs -------
  12.234 +	      .read_data                  (way_data[i])
  12.235 +	      );
  12.236 +	   
  12.237 +	   lm32_ram 
  12.238 +	     #(
  12.239 +	       // ----- Parameters -------
  12.240 +	       .data_width                 (`LM32_IC_TAGS_WIDTH),
  12.241 +	       .address_width              (`LM32_IC_TMEM_ADDR_WIDTH),
  12.242 +`ifdef CFG_ICACHE_DAT_USE_DP_TRUE
  12.243 +	       .RAM_IMPLEMENTATION         ("EBR"),
  12.244 +	       .RAM_TYPE                   ("RAM_DP_TRUE")
  12.245 +`else
  12.246 + `ifdef CFG_ICACHE_DAT_USE_DP
  12.247 +	       .RAM_IMPLEMENTATION         ("EBR"),
  12.248 +	       .RAM_TYPE                   ("RAM_DP")
  12.249 + `else
  12.250 +  `ifdef CFG_ICACHE_DAT_USE_SLICE
  12.251 +	       .RAM_IMPLEMENTATION         ("SLICE")
  12.252 +  `else
  12.253 +	       .RAM_IMPLEMENTATION         ("AUTO")
  12.254 +  `endif
  12.255 + `endif
  12.256 +`endif
  12.257 +	       ) 
  12.258 +	   way_0_tag_ram 
  12.259 +	     (
  12.260 +	      // ----- Inputs -------
  12.261 +	      .read_clk                   (clk_i),
  12.262 +	      .write_clk                  (clk_i),
  12.263 +	      .reset                      (rst_i),
  12.264 +	      .read_address               (tmem_read_address),
  12.265 +	      .enable_read                (enable),
  12.266 +	      .write_address              (tmem_write_address),
  12.267 +	      .enable_write               (`TRUE),
  12.268 +	      .write_enable               (way_mem_we[i] | flushing),
  12.269 +	      .write_data                 (tmem_write_data),
  12.270 +	      // ----- Outputs -------
  12.271 +	      .read_data                  ({way_tag[i], way_valid[i]})
  12.272 +	      );
  12.273 +	   
  12.274 +	end
  12.275 +endgenerate
  12.276 +
  12.277 +/////////////////////////////////////////////////////
  12.278 +// Combinational logic
  12.279 +/////////////////////////////////////////////////////
  12.280 +
  12.281 +// Compute which ways in the cache match the address address being read
  12.282 +generate
  12.283 +    for (i = 0; i < associativity; i = i + 1)
  12.284 +    begin : match
  12.285 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
  12.286 +    end
  12.287 +endgenerate
  12.288 +
  12.289 +// Select data from way that matched the address being read     
  12.290 +generate
  12.291 +    if (associativity == 1)
  12.292 +    begin : inst_1
  12.293 +assign inst = way_match[0] ? way_data[0] : 32'b0;
  12.294 +    end
  12.295 +    else if (associativity == 2)
  12.296 +	 begin : inst_2
  12.297 +assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
  12.298 +    end
  12.299 +endgenerate
  12.300 +
  12.301 +// Compute address to use to index into the data memories
  12.302 +generate 
  12.303 +    if (bytes_per_line > 4)
  12.304 +assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
  12.305 +    else
  12.306 +assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
  12.307 +endgenerate
  12.308 +    
  12.309 +assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
  12.310 +
  12.311 +// Compute address to use to index into the tag memories                        
  12.312 +assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
  12.313 +assign tmem_write_address = flushing 
  12.314 +                                ? flush_set
  12.315 +                                : refill_address[`LM32_IC_ADDR_SET_RNG];
  12.316 +
  12.317 +// Compute signal to indicate when we are on the last refill accesses
  12.318 +generate 
  12.319 +    if (bytes_per_line > 4)                            
  12.320 +assign last_refill = refill_offset == {addr_offset_width{1'b1}};
  12.321 +    else
  12.322 +assign last_refill = `TRUE;
  12.323 +endgenerate
  12.324 +
  12.325 +// Compute data and tag memory access enable
  12.326 +assign enable = (stall_a == `FALSE);
  12.327 +
  12.328 +// Compute data and tag memory write enables
  12.329 +generate
  12.330 +    if (associativity == 1) 
  12.331 +    begin : we_1     
  12.332 +assign way_mem_we[0] = (refill_ready == `TRUE);
  12.333 +    end
  12.334 +    else
  12.335 +    begin : we_2
  12.336 +assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
  12.337 +assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
  12.338 +    end
  12.339 +endgenerate                     
  12.340 +
  12.341 +// On the last refill cycle set the valid bit, for all other writes it should be cleared
  12.342 +assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
  12.343 +assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
  12.344 +
  12.345 +// Signals that indicate which state we are in
  12.346 +assign flushing = |state[1:0];
  12.347 +assign check = state[2];
  12.348 +assign refill = state[3];
  12.349 +
  12.350 +assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
  12.351 +assign stall_request = (check == `FALSE);
  12.352 +assign refill_request = (refill == `TRUE);
  12.353 +                      
  12.354 +/////////////////////////////////////////////////////
  12.355 +// Sequential logic
  12.356 +/////////////////////////////////////////////////////
  12.357 +
  12.358 +// Record way selected for replacement on a cache miss
  12.359 +generate
  12.360 +    if (associativity >= 2) 
  12.361 +    begin : way_select      
  12.362 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  12.363 +begin
  12.364 +    if (rst_i == `TRUE)
  12.365 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
  12.366 +    else
  12.367 +    begin        
  12.368 +        if (miss == `TRUE)
  12.369 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
  12.370 +    end
  12.371 +end
  12.372 +    end
  12.373 +endgenerate
  12.374 +
  12.375 +// Record whether we are refilling
  12.376 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  12.377 +begin
  12.378 +    if (rst_i == `TRUE)
  12.379 +        refilling <= `FALSE;
  12.380 +    else
  12.381 +        refilling <= refill;
  12.382 +end
  12.383 +
  12.384 +// Instruction cache control FSM
  12.385 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  12.386 +begin
  12.387 +    if (rst_i == `TRUE)
  12.388 +    begin
  12.389 +        state <= `LM32_IC_STATE_FLUSH_INIT;
  12.390 +        flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
  12.391 +        refill_address <= {`LM32_PC_WIDTH{1'bx}};
  12.392 +        restart_request <= `FALSE;
  12.393 +    end
  12.394 +    else 
  12.395 +    begin
  12.396 +        case (state)
  12.397 +
  12.398 +        // Flush the cache for the first time after reset
  12.399 +        `LM32_IC_STATE_FLUSH_INIT:
  12.400 +        begin            
  12.401 +            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  12.402 +                state <= `LM32_IC_STATE_CHECK;
  12.403 +            flush_set <= flush_set - 1'b1;
  12.404 +        end
  12.405 +
  12.406 +        // Flush the cache in response to an write to the ICC CSR
  12.407 +        `LM32_IC_STATE_FLUSH:
  12.408 +        begin            
  12.409 +            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
  12.410 +`ifdef CFG_IROM_ENABLED
  12.411 +	      if (select_f)
  12.412 +                state <= `LM32_IC_STATE_REFILL;
  12.413 +	      else
  12.414 +`endif
  12.415 +		state <= `LM32_IC_STATE_CHECK;
  12.416 +	   
  12.417 +            flush_set <= flush_set - 1'b1;
  12.418 +        end
  12.419 +        
  12.420 +        // Check for cache misses
  12.421 +        `LM32_IC_STATE_CHECK:
  12.422 +        begin            
  12.423 +            if (stall_a == `FALSE)
  12.424 +                restart_request <= `FALSE;
  12.425 +            if (iflush == `TRUE)
  12.426 +            begin
  12.427 +                refill_address <= address_f;
  12.428 +                state <= `LM32_IC_STATE_FLUSH;
  12.429 +            end
  12.430 +            else if (miss == `TRUE)
  12.431 +            begin
  12.432 +                refill_address <= address_f;
  12.433 +                state <= `LM32_IC_STATE_REFILL;
  12.434 +            end
  12.435 +        end
  12.436 +
  12.437 +        // Refill a cache line
  12.438 +        `LM32_IC_STATE_REFILL:
  12.439 +        begin            
  12.440 +            if (refill_ready == `TRUE)
  12.441 +            begin
  12.442 +                if (last_refill == `TRUE)
  12.443 +                begin
  12.444 +                    restart_request <= `TRUE;
  12.445 +                    state <= `LM32_IC_STATE_CHECK;
  12.446 +                end
  12.447 +            end
  12.448 +        end
  12.449 +
  12.450 +        endcase        
  12.451 +    end
  12.452 +end
  12.453 +
  12.454 +generate 
  12.455 +    if (bytes_per_line > 4)
  12.456 +    begin
  12.457 +// Refill offset
  12.458 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  12.459 +begin
  12.460 +    if (rst_i == `TRUE)
  12.461 +        refill_offset <= {addr_offset_width{1'b0}};
  12.462 +    else 
  12.463 +    begin
  12.464 +        case (state)
  12.465 +        
  12.466 +        // Check for cache misses
  12.467 +        `LM32_IC_STATE_CHECK:
  12.468 +        begin            
  12.469 +            if (iflush == `TRUE)
  12.470 +                refill_offset <= {addr_offset_width{1'b0}};
  12.471 +            else if (miss == `TRUE)
  12.472 +                refill_offset <= {addr_offset_width{1'b0}};
  12.473 +        end
  12.474 +
  12.475 +        // Refill a cache line
  12.476 +        `LM32_IC_STATE_REFILL:
  12.477 +        begin            
  12.478 +            if (refill_ready == `TRUE)
  12.479 +                refill_offset <= refill_offset + 1'b1;
  12.480 +        end
  12.481 +
  12.482 +        endcase        
  12.483 +    end
  12.484 +end
  12.485 +    end
  12.486 +endgenerate
  12.487 +   
  12.488 +endmodule
  12.489 +
  12.490 +`endif
  12.491 +
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/lm32_include.v	Sun Apr 04 20:40:03 2010 +0100
    13.3 @@ -0,0 +1,329 @@
    13.4 +// =============================================================================
    13.5 +//                           COPYRIGHT NOTICE
    13.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    13.7 +// ALL RIGHTS RESERVED
    13.8 +// This confidential and proprietary software may be used only as authorised by
    13.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   13.10 +// The entire notice above must be reproduced on all authorized copies and
   13.11 +// copies may only be made to the extent permitted by a licensing agreement from
   13.12 +// Lattice Semiconductor Corporation.
   13.13 +//
   13.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   13.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   13.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   13.17 +// U.S.A                                   email: techsupport@latticesemi.com
   13.18 +// =============================================================================/
   13.19 +//                         FILE DETAILS
   13.20 +// Project          : LatticeMico32
   13.21 +// File             : lm32_include.v
   13.22 +// Title            : CPU global macros
   13.23 +// Version          : 6.1.17
   13.24 +//                  : Initial Release
   13.25 +// Version          : 7.0SP2, 3.0
   13.26 +//                  : No Change
   13.27 +// Version          : 3.1
   13.28 +//                  : No Change
   13.29 +// Version          : 3.2
   13.30 +//                  : No Change
   13.31 +// Version          : 3.3
   13.32 +//                  : Support for extended configuration register
   13.33 +// =============================================================================
   13.34 +
   13.35 +`ifdef LM32_INCLUDE_V
   13.36 +`else
   13.37 +`define LM32_INCLUDE_V
   13.38 +
   13.39 +// Configuration options
   13.40 +`include "system_conf.v"
   13.41 +
   13.42 +`ifdef TRUE
   13.43 +`else
   13.44 +`define TRUE    1'b1
   13.45 +`define FALSE   1'b0
   13.46 +`define TRUE_N  1'b0
   13.47 +`define FALSE_N 1'b1
   13.48 +`endif
   13.49 +
   13.50 +// Wishbone configuration
   13.51 +`define CFG_IWB_ENABLED
   13.52 +`define CFG_DWB_ENABLED
   13.53 +
   13.54 +// Data-path width
   13.55 +`define LM32_WORD_WIDTH                 32
   13.56 +`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
   13.57 +`define LM32_SHIFT_WIDTH                5
   13.58 +`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
   13.59 +`define LM32_BYTE_SELECT_WIDTH          4
   13.60 +`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
   13.61 +
   13.62 +// Register file size
   13.63 +`define LM32_REGISTERS                  32
   13.64 +`define LM32_REG_IDX_WIDTH              5
   13.65 +`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
   13.66 +
   13.67 +// Standard register numbers
   13.68 +`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
   13.69 +`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
   13.70 +`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
   13.71 +
   13.72 +// Range of Program Counter. Two LSBs are always 0. 
   13.73 +// `ifdef CFG_ICACHE_ENABLED
   13.74 +// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
   13.75 +// `else
   13.76 +// `ifdef CFG_IWB_ENABLED
   13.77 +`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
   13.78 +// `else
   13.79 +// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
   13.80 +// `endif
   13.81 +// `endif
   13.82 +`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
   13.83 +
   13.84 +// Range of an instruction
   13.85 +`define LM32_INSTRUCTION_WIDTH          32
   13.86 +`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
   13.87 +
   13.88 +// Adder operation
   13.89 +`define LM32_ADDER_OP_ADD               1'b0
   13.90 +`define LM32_ADDER_OP_SUBTRACT          1'b1
   13.91 +
   13.92 +// Shift direction
   13.93 +`define LM32_SHIFT_OP_RIGHT             1'b0
   13.94 +`define LM32_SHIFT_OP_LEFT              1'b1
   13.95 +
   13.96 +// Currently always enabled
   13.97 +`define CFG_BUS_ERRORS_ENABLED
   13.98 +
   13.99 +// Derive macro that indicates whether we have single-stepping or not
  13.100 +`ifdef CFG_ROM_DEBUG_ENABLED
  13.101 +`define LM32_SINGLE_STEP_ENABLED
  13.102 +`else
  13.103 +`ifdef CFG_HW_DEBUG_ENABLED
  13.104 +`define LM32_SINGLE_STEP_ENABLED
  13.105 +`endif
  13.106 +`endif
  13.107 +
  13.108 +// Derive macro that indicates whether JTAG interface is required
  13.109 +`ifdef CFG_JTAG_UART_ENABLED
  13.110 +`define LM32_JTAG_ENABLED
  13.111 +`else
  13.112 +`ifdef CFG_DEBUG_ENABLED
  13.113 +`define LM32_JTAG_ENABLED
  13.114 +`else
  13.115 +`endif
  13.116 +`endif
  13.117 +
  13.118 +// Derive macro that indicates whether we have a barrel-shifter or not
  13.119 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
  13.120 +`define LM32_BARREL_SHIFT_ENABLED
  13.121 +`else // CFG_PL_BARREL_SHIFT_ENABLED
  13.122 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  13.123 +`define LM32_BARREL_SHIFT_ENABLED
  13.124 +`else
  13.125 +`define LM32_NO_BARREL_SHIFT
  13.126 +`endif
  13.127 +`endif // CFG_PL_BARREL_SHIFT_ENABLED
  13.128 +
  13.129 +// Derive macro that indicates whether we have a multiplier or not
  13.130 +`ifdef CFG_PL_MULTIPLY_ENABLED
  13.131 +`define LM32_MULTIPLY_ENABLED
  13.132 +`else
  13.133 +`ifdef CFG_MC_MULTIPLY_ENABLED
  13.134 +`define LM32_MULTIPLY_ENABLED
  13.135 +`endif
  13.136 +`endif
  13.137 +
  13.138 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
  13.139 +`ifdef CFG_MC_DIVIDE_ENABLED
  13.140 +`define LM32_MC_ARITHMETIC_ENABLED
  13.141 +`endif
  13.142 +`ifdef CFG_MC_MULTIPLY_ENABLED
  13.143 +`define LM32_MC_ARITHMETIC_ENABLED
  13.144 +`endif
  13.145 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
  13.146 +`define LM32_MC_ARITHMETIC_ENABLED
  13.147 +`endif
  13.148 +
  13.149 +// Derive macro that indicates if we are using an EBR register file
  13.150 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  13.151 +`define LM32_EBR_REGISTER_FILE
  13.152 +`endif
  13.153 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  13.154 +`define LM32_EBR_REGISTER_FILE
  13.155 +`endif
  13.156 +
  13.157 +// Revision number
  13.158 +`define LM32_REVISION                   6'h02
  13.159 +
  13.160 +// Logical operations - Function encoded directly in instruction
  13.161 +`define LM32_LOGIC_OP_RNG               3:0
  13.162 +
  13.163 +// Conditions for conditional branches
  13.164 +`define LM32_CONDITION_WIDTH            3
  13.165 +`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
  13.166 +`define LM32_CONDITION_E                3'b001
  13.167 +`define LM32_CONDITION_G                3'b010
  13.168 +`define LM32_CONDITION_GE               3'b011
  13.169 +`define LM32_CONDITION_GEU              3'b100
  13.170 +`define LM32_CONDITION_GU               3'b101
  13.171 +`define LM32_CONDITION_NE               3'b111
  13.172 +`define LM32_CONDITION_U1               3'b000
  13.173 +`define LM32_CONDITION_U2               3'b110
  13.174 +
  13.175 +// Size of load or store instruction - Encoding corresponds to opcode
  13.176 +`define LM32_SIZE_WIDTH                 2
  13.177 +`define LM32_SIZE_RNG                   1:0
  13.178 +`define LM32_SIZE_BYTE                  2'b00
  13.179 +`define LM32_SIZE_HWORD                 2'b11
  13.180 +`define LM32_SIZE_WORD                  2'b10
  13.181 +`define LM32_ADDRESS_LSBS_WIDTH         2
  13.182 +
  13.183 +// Width and range of a CSR index
  13.184 +`ifdef CFG_DEBUG_ENABLED
  13.185 +`define LM32_CSR_WIDTH                  5
  13.186 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  13.187 +`else
  13.188 +`ifdef CFG_JTAG_ENABLED
  13.189 +`define LM32_CSR_WIDTH                  4
  13.190 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  13.191 +`else
  13.192 +`define LM32_CSR_WIDTH                  3
  13.193 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
  13.194 +`endif
  13.195 +`endif
  13.196 +
  13.197 +// CSR indices
  13.198 +`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
  13.199 +`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
  13.200 +`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
  13.201 +`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
  13.202 +`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
  13.203 +`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
  13.204 +`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
  13.205 +`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
  13.206 +`ifdef CFG_DEBUG_ENABLED
  13.207 +`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
  13.208 +`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
  13.209 +`endif
  13.210 +`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
  13.211 +`ifdef CFG_JTAG_ENABLED
  13.212 +`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
  13.213 +`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
  13.214 +`endif
  13.215 +`ifdef CFG_DEBUG_ENABLED
  13.216 +`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
  13.217 +`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
  13.218 +`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
  13.219 +`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
  13.220 +`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
  13.221 +`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
  13.222 +`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
  13.223 +`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
  13.224 +`endif 
  13.225 +
  13.226 +// Values for WPC CSR
  13.227 +`define LM32_WPC_C_RNG                  1:0
  13.228 +`define LM32_WPC_C_DISABLED             2'b00
  13.229 +`define LM32_WPC_C_READ                 2'b01
  13.230 +`define LM32_WPC_C_WRITE                2'b10
  13.231 +`define LM32_WPC_C_READ_WRITE           2'b11
  13.232 +
  13.233 +// Exception IDs
  13.234 +`define LM32_EID_WIDTH                  3
  13.235 +`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
  13.236 +`define LM32_EID_RESET                  3'h0
  13.237 +`define LM32_EID_BREAKPOINT             3'd1
  13.238 +`define LM32_EID_INST_BUS_ERROR         3'h2
  13.239 +`define LM32_EID_WATCHPOINT             3'd3
  13.240 +`define LM32_EID_DATA_BUS_ERROR         3'h4
  13.241 +`define LM32_EID_DIVIDE_BY_ZERO         3'h5
  13.242 +`define LM32_EID_INTERRUPT              3'h6
  13.243 +`define LM32_EID_SCALL                  3'h7
  13.244 +
  13.245 +// Pipeline result selection mux controls
  13.246 +
  13.247 +`define LM32_D_RESULT_SEL_0_RNG          0:0
  13.248 +`define LM32_D_RESULT_SEL_0_REG_0        1'b0
  13.249 +`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
  13.250 +
  13.251 +`define LM32_D_RESULT_SEL_1_RNG          1:0
  13.252 +`define LM32_D_RESULT_SEL_1_ZERO         2'b00
  13.253 +`define LM32_D_RESULT_SEL_1_REG_1        2'b01
  13.254 +`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
  13.255 +
  13.256 +`define LM32_USER_OPCODE_WIDTH           11
  13.257 +`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
  13.258 +
  13.259 +// Derive a macro to indicate if either of the caches are implemented
  13.260 +`ifdef CFG_ICACHE_ENABLED
  13.261 +`define LM32_CACHE_ENABLED      
  13.262 +`else
  13.263 +`ifdef CFG_DCACHE_ENABLED
  13.264 +`define LM32_CACHE_ENABLED
  13.265 +`endif
  13.266 +`endif
  13.267 +
  13.268 +/////////////////////////////////////////////////////
  13.269 +// Interrupts
  13.270 +/////////////////////////////////////////////////////
  13.271 +
  13.272 +// Always enable interrupts
  13.273 +`define CFG_INTERRUPTS_ENABLED
  13.274 +
  13.275 +// Currently this is fixed to 32 and should not be changed
  13.276 +`define CFG_INTERRUPTS                  32
  13.277 +`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
  13.278 +`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
  13.279 +
  13.280 +/////////////////////////////////////////////////////
  13.281 +// General
  13.282 +/////////////////////////////////////////////////////
  13.283 +
  13.284 +// Sub-word range types
  13.285 +`define LM32_BYTE_WIDTH                 8
  13.286 +`define LM32_BYTE_RNG                   7:0
  13.287 +`define LM32_HWORD_WIDTH                16
  13.288 +`define LM32_HWORD_RNG                  15:0
  13.289 +
  13.290 +// Word sub-byte indicies
  13.291 +`define LM32_BYTE_0_RNG                  7:0
  13.292 +`define LM32_BYTE_1_RNG                  15:8
  13.293 +`define LM32_BYTE_2_RNG                  23:16
  13.294 +`define LM32_BYTE_3_RNG                  31:24
  13.295 +
  13.296 +// Word sub-halfword indices
  13.297 +`define LM32_HWORD_0_RNG                 15:0
  13.298 +`define LM32_HWORD_1_RNG                 31:16
  13.299 +
  13.300 +// Use an asynchronous reset
  13.301 +// To use a synchronous reset, define this macro as nothing
  13.302 +`define CFG_RESET_SENSITIVITY 
  13.303 +
  13.304 +// V.T. Srce
  13.305 +`define SRCE
  13.306 +
  13.307 +// Whether to include context registers for debug exceptions
  13.308 +// in addition to standard exception handling registers
  13.309 +// Bizarre - Removing this increases LUT count!
  13.310 +`define CFG_DEBUG_EXCEPTIONS_ENABLED
  13.311 +
  13.312 +// Wishbone defines 
  13.313 +// Refer to Wishbone System-on-Chip Interconnection Architecture
  13.314 +// These should probably be moved to a Wishbone common file
  13.315 +
  13.316 +// Wishbone cycle types
  13.317 +`define LM32_CTYPE_WIDTH                3
  13.318 +`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
  13.319 +`define LM32_CTYPE_CLASSIC              3'b000
  13.320 +`define LM32_CTYPE_CONSTANT             3'b001
  13.321 +`define LM32_CTYPE_INCREMENTING         3'b010
  13.322 +`define LM32_CTYPE_END                  3'b111
  13.323 +
  13.324 +// Wishbone burst types
  13.325 +`define LM32_BTYPE_WIDTH                2
  13.326 +`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
  13.327 +`define LM32_BTYPE_LINEAR               2'b00
  13.328 +`define LM32_BTYPE_4_BEAT               2'b01
  13.329 +`define LM32_BTYPE_8_BEAT               2'b10
  13.330 +`define LM32_BTYPE_16_BEAT              2'b11
  13.331 +
  13.332 +`endif
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/lm32_instruction_unit.v	Sun Apr 04 20:40:03 2010 +0100
    14.3 @@ -0,0 +1,841 @@
    14.4 +// =============================================================================
    14.5 +//                           COPYRIGHT NOTICE
    14.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    14.7 +// ALL RIGHTS RESERVED
    14.8 +// This confidential and proprietary software may be used only as authorised by
    14.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   14.10 +// The entire notice above must be reproduced on all authorized copies and
   14.11 +// copies may only be made to the extent permitted by a licensing agreement from
   14.12 +// Lattice Semiconductor Corporation.
   14.13 +//
   14.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   14.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   14.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   14.17 +// U.S.A                                   email: techsupport@latticesemi.com
   14.18 +// =============================================================================/
   14.19 +//                         FILE DETAILS
   14.20 +// Project      : LatticeMico32
   14.21 +// File         : lm32_instruction_unit.v
   14.22 +// Title        : Instruction unit
   14.23 +// Dependencies : lm32_include.v
   14.24 +// Version      : 6.1.17
   14.25 +//              : Initial Release
   14.26 +// Version      : 7.0SP2, 3.0
   14.27 +//              : No Change
   14.28 +// Version      : 3.1
   14.29 +//              : Support for static branch prediction is added. Fetching of
   14.30 +//              : instructions can also be altered by branches predicted in D
   14.31 +//              : stage of pipeline, and mispredicted branches in the X and M 
   14.32 +//              : stages of the pipeline.
   14.33 +// Version      : 3.2
   14.34 +//              : EBRs use SYNC resets instead of ASYNC resets.
   14.35 +// Version      : 3.3
   14.36 +//              : Support for a non-cacheable Instruction Memory that has a 
   14.37 +//              : single-cycle access latency. This memory can be accessed by
   14.38 +//              : data port of LM32 (so that debugger has access to it).
   14.39 +// Version      : 3.4
   14.40 +//              : No change
   14.41 +// Version      : 3.5
   14.42 +//              : Bug fix: Inline memory is correctly generated if it is not a
   14.43 +//              : power-of-two.
   14.44 +//              : Bug fix: Fixed a bug that caused LM32 (configured without
   14.45 +//              : instruction cache) to lock up in to an infinite loop due to a 
   14.46 +//              : instruction bus error when EBA was set to instruction inline
   14.47 +//              : memory.
   14.48 +// =============================================================================
   14.49 +
   14.50 +`include "lm32_include.v"
   14.51 +
   14.52 +/////////////////////////////////////////////////////
   14.53 +// Module interface
   14.54 +/////////////////////////////////////////////////////
   14.55 +
   14.56 +module lm32_instruction_unit (
   14.57 +    // ----- Inputs -------
   14.58 +    clk_i,
   14.59 +    rst_i,
   14.60 +    // From pipeline
   14.61 +    stall_a,
   14.62 +    stall_f,
   14.63 +    stall_d,
   14.64 +    stall_x,
   14.65 +    stall_m,
   14.66 +    valid_f,
   14.67 +    valid_d,
   14.68 +    kill_f,
   14.69 +    branch_predict_taken_d,
   14.70 +    branch_predict_address_d,
   14.71 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   14.72 +    branch_taken_x,
   14.73 +    branch_target_x,
   14.74 +`endif
   14.75 +    exception_m,
   14.76 +    branch_taken_m,
   14.77 +    branch_mispredict_taken_m,
   14.78 +    branch_target_m,
   14.79 +`ifdef CFG_ICACHE_ENABLED
   14.80 +    iflush,
   14.81 +`endif
   14.82 +`ifdef CFG_DCACHE_ENABLED
   14.83 +    dcache_restart_request,
   14.84 +    dcache_refill_request,
   14.85 +    dcache_refilling,
   14.86 +`endif        
   14.87 +`ifdef CFG_IROM_ENABLED
   14.88 +    irom_store_data_m,
   14.89 +    irom_address_xm,
   14.90 +    irom_we_xm,
   14.91 +`endif
   14.92 +`ifdef CFG_IWB_ENABLED
   14.93 +    // From Wishbone
   14.94 +    i_dat_i,
   14.95 +    i_ack_i,
   14.96 +    i_err_i,
   14.97 +    i_rty_i,
   14.98 +`endif
   14.99 +`ifdef CFG_HW_DEBUG_ENABLED
  14.100 +    jtag_read_enable,
  14.101 +    jtag_write_enable,
  14.102 +    jtag_write_data,
  14.103 +    jtag_address,
  14.104 +`endif
  14.105 +    // ----- Outputs -------
  14.106 +    // To pipeline
  14.107 +    pc_f,
  14.108 +    pc_d,
  14.109 +    pc_x,
  14.110 +    pc_m,
  14.111 +    pc_w,
  14.112 +`ifdef CFG_ICACHE_ENABLED
  14.113 +    icache_stall_request,
  14.114 +    icache_restart_request,
  14.115 +    icache_refill_request,
  14.116 +    icache_refilling,
  14.117 +`endif
  14.118 +`ifdef CFG_IROM_ENABLED
  14.119 +    irom_data_m,
  14.120 +`endif
  14.121 +`ifdef CFG_IWB_ENABLED
  14.122 +    // To Wishbone
  14.123 +    i_dat_o,
  14.124 +    i_adr_o,
  14.125 +    i_cyc_o,
  14.126 +    i_sel_o,
  14.127 +    i_stb_o,
  14.128 +    i_we_o,
  14.129 +    i_cti_o,
  14.130 +    i_lock_o,
  14.131 +    i_bte_o,
  14.132 +`endif
  14.133 +`ifdef CFG_HW_DEBUG_ENABLED
  14.134 +    jtag_read_data,
  14.135 +    jtag_access_complete,
  14.136 +`endif
  14.137 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.138 +    bus_error_d,
  14.139 +`endif
  14.140 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  14.141 +    instruction_f,
  14.142 +`endif    
  14.143 +    instruction_d
  14.144 +    );
  14.145 +
  14.146 +/////////////////////////////////////////////////////
  14.147 +// Parameters
  14.148 +/////////////////////////////////////////////////////
  14.149 +
  14.150 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  14.151 +parameter sets = 512;                                   // Number of sets
  14.152 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  14.153 +parameter base_address = 0;                             // Base address of cachable memory
  14.154 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  14.155 +
  14.156 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  14.157 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  14.158 +localparam addr_offset_lsb = 2;
  14.159 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  14.160 +
  14.161 +/////////////////////////////////////////////////////
  14.162 +// Inputs
  14.163 +/////////////////////////////////////////////////////
  14.164 +
  14.165 +input clk_i;                                            // Clock
  14.166 +input rst_i;                                            // Reset
  14.167 +
  14.168 +input stall_a;                                          // Stall A stage instruction
  14.169 +input stall_f;                                          // Stall F stage instruction
  14.170 +input stall_d;                                          // Stall D stage instruction
  14.171 +input stall_x;                                          // Stall X stage instruction
  14.172 +input stall_m;                                          // Stall M stage instruction
  14.173 +input valid_f;                                          // Instruction in F stage is valid
  14.174 +input valid_d;                                          // Instruction in D stage is valid
  14.175 +input kill_f;                                           // Kill instruction in F stage
  14.176 +
  14.177 +input branch_predict_taken_d;                           // Branch is predicted taken in D stage
  14.178 +input [`LM32_PC_RNG] branch_predict_address_d;          // Branch target address
  14.179 +   
  14.180 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  14.181 +input branch_taken_x;                                   // Branch instruction in X stage is taken
  14.182 +input [`LM32_PC_RNG] branch_target_x;                   // Target PC of X stage branch instruction
  14.183 +`endif
  14.184 +input exception_m;
  14.185 +input branch_taken_m;                                   // Branch instruction in M stage is taken
  14.186 +input branch_mispredict_taken_m;                        // Branch instruction in M stage is mispredicted as taken
  14.187 +input [`LM32_PC_RNG] branch_target_m;                   // Target PC of M stage branch instruction
  14.188 +
  14.189 +`ifdef CFG_ICACHE_ENABLED
  14.190 +input iflush;                                           // Flush instruction cache
  14.191 +`endif
  14.192 +`ifdef CFG_DCACHE_ENABLED
  14.193 +input dcache_restart_request;                           // Restart instruction that caused a data cache miss
  14.194 +input dcache_refill_request;                            // Request to refill data cache
  14.195 +input dcache_refilling;
  14.196 +`endif        
  14.197 +
  14.198 +`ifdef CFG_IROM_ENABLED
  14.199 +input [`LM32_WORD_RNG] irom_store_data_m;               // Data from load-store unit
  14.200 +input [`LM32_WORD_RNG] irom_address_xm;                 // Address from load-store unit
  14.201 +input irom_we_xm;                                       // Indicates if memory operation is load or store
  14.202 +`endif
  14.203 +
  14.204 +`ifdef CFG_IWB_ENABLED
  14.205 +input [`LM32_WORD_RNG] i_dat_i;                         // Instruction Wishbone interface read data
  14.206 +input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
  14.207 +input i_err_i;                                          // Instruction Wishbone interface error
  14.208 +input i_rty_i;                                          // Instruction Wishbone interface retry
  14.209 +`endif
  14.210 +
  14.211 +`ifdef CFG_HW_DEBUG_ENABLED
  14.212 +input jtag_read_enable;                                 // JTAG read memory request
  14.213 +input jtag_write_enable;                                // JTAG write memory request
  14.214 +input [`LM32_BYTE_RNG] jtag_write_data;                 // JTAG wrirte data
  14.215 +input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write address
  14.216 +`endif
  14.217 +
  14.218 +/////////////////////////////////////////////////////
  14.219 +// Outputs
  14.220 +/////////////////////////////////////////////////////
  14.221 +        
  14.222 +output [`LM32_PC_RNG] pc_f;                             // F stage PC
  14.223 +reg    [`LM32_PC_RNG] pc_f;
  14.224 +output [`LM32_PC_RNG] pc_d;                             // D stage PC
  14.225 +reg    [`LM32_PC_RNG] pc_d;
  14.226 +output [`LM32_PC_RNG] pc_x;                             // X stage PC
  14.227 +reg    [`LM32_PC_RNG] pc_x;
  14.228 +output [`LM32_PC_RNG] pc_m;                             // M stage PC
  14.229 +reg    [`LM32_PC_RNG] pc_m;
  14.230 +output [`LM32_PC_RNG] pc_w;                             // W stage PC
  14.231 +reg    [`LM32_PC_RNG] pc_w;
  14.232 +
  14.233 +`ifdef CFG_ICACHE_ENABLED
  14.234 +output icache_stall_request;                            // Instruction cache stall request
  14.235 +wire   icache_stall_request;
  14.236 +output icache_restart_request;                          // Request to restart instruction that cached instruction cache miss
  14.237 +wire   icache_restart_request;
  14.238 +output icache_refill_request;                           // Instruction cache refill request
  14.239 +wire   icache_refill_request;
  14.240 +output icache_refilling;                                // Indicates the icache is refilling
  14.241 +wire   icache_refilling;
  14.242 +`endif
  14.243 +
  14.244 +`ifdef CFG_IROM_ENABLED
  14.245 +output [`LM32_WORD_RNG] irom_data_m;                    // Data to load-store unit on load
  14.246 +wire   [`LM32_WORD_RNG] irom_data_m;                      
  14.247 +`endif   
  14.248 +
  14.249 +`ifdef CFG_IWB_ENABLED
  14.250 +output [`LM32_WORD_RNG] i_dat_o;                        // Instruction Wishbone interface write data
  14.251 +`ifdef CFG_HW_DEBUG_ENABLED
  14.252 +reg    [`LM32_WORD_RNG] i_dat_o;
  14.253 +`else
  14.254 +wire   [`LM32_WORD_RNG] i_dat_o;
  14.255 +`endif
  14.256 +output [`LM32_WORD_RNG] i_adr_o;                        // Instruction Wishbone interface address
  14.257 +reg    [`LM32_WORD_RNG] i_adr_o;
  14.258 +output i_cyc_o;                                         // Instruction Wishbone interface cycle
  14.259 +reg    i_cyc_o; 
  14.260 +output [`LM32_BYTE_SELECT_RNG] i_sel_o;                 // Instruction Wishbone interface byte select
  14.261 +`ifdef CFG_HW_DEBUG_ENABLED
  14.262 +reg    [`LM32_BYTE_SELECT_RNG] i_sel_o;
  14.263 +`else
  14.264 +wire   [`LM32_BYTE_SELECT_RNG] i_sel_o;
  14.265 +`endif
  14.266 +output i_stb_o;                                         // Instruction Wishbone interface strobe
  14.267 +reg    i_stb_o;
  14.268 +output i_we_o;                                          // Instruction Wishbone interface write enable
  14.269 +`ifdef CFG_HW_DEBUG_ENABLED
  14.270 +reg    i_we_o;
  14.271 +`else
  14.272 +wire   i_we_o;
  14.273 +`endif
  14.274 +output [`LM32_CTYPE_RNG] i_cti_o;                       // Instruction Wishbone interface cycle type 
  14.275 +reg    [`LM32_CTYPE_RNG] i_cti_o;
  14.276 +output i_lock_o;                                        // Instruction Wishbone interface lock bus
  14.277 +reg    i_lock_o;
  14.278 +output [`LM32_BTYPE_RNG] i_bte_o;                       // Instruction Wishbone interface burst type 
  14.279 +wire   [`LM32_BTYPE_RNG] i_bte_o;
  14.280 +`endif
  14.281 +
  14.282 +`ifdef CFG_HW_DEBUG_ENABLED
  14.283 +output [`LM32_BYTE_RNG] jtag_read_data;                 // Data read for JTAG interface
  14.284 +reg    [`LM32_BYTE_RNG] jtag_read_data;
  14.285 +output jtag_access_complete;                            // Requested memory access by JTAG interface is complete
  14.286 +wire   jtag_access_complete;
  14.287 +`endif
  14.288 +
  14.289 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.290 +output bus_error_d;                                     // Indicates a bus error occured while fetching the instruction
  14.291 +reg    bus_error_d;
  14.292 +`endif
  14.293 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  14.294 +output [`LM32_INSTRUCTION_RNG] instruction_f;           // F stage instruction (only to have register indices extracted from)
  14.295 +wire   [`LM32_INSTRUCTION_RNG] instruction_f;
  14.296 +`endif
  14.297 +output [`LM32_INSTRUCTION_RNG] instruction_d;           // D stage instruction to be decoded
  14.298 +reg    [`LM32_INSTRUCTION_RNG] instruction_d;
  14.299 +
  14.300 +/////////////////////////////////////////////////////
  14.301 +// Internal nets and registers 
  14.302 +/////////////////////////////////////////////////////
  14.303 +
  14.304 +reg [`LM32_PC_RNG] pc_a;                                // A stage PC
  14.305 +
  14.306 +`ifdef LM32_CACHE_ENABLED
  14.307 +reg [`LM32_PC_RNG] restart_address;                     // Address to restart from after a cache miss  
  14.308 +`endif
  14.309 +
  14.310 +`ifdef CFG_ICACHE_ENABLED
  14.311 +wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
  14.312 +wire [`LM32_PC_RNG] icache_refill_address;              // Address that caused cache miss
  14.313 +reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
  14.314 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data;         // Next word of refill data, fetched from Wishbone
  14.315 +wire [`LM32_INSTRUCTION_RNG] icache_data_f;             // Instruction fetched from instruction cache
  14.316 +wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  14.317 +wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  14.318 +wire last_word;                                         // Indicates if this is the last word in the cache line
  14.319 +wire [`LM32_PC_RNG] first_address;                      // First cache refill address
  14.320 +`else
  14.321 +`ifdef CFG_IWB_ENABLED
  14.322 +reg [`LM32_INSTRUCTION_RNG] wb_data_f;                  // Instruction fetched from Wishbone
  14.323 +`endif
  14.324 +`endif
  14.325 +`ifdef CFG_IROM_ENABLED
  14.326 +wire irom_select_a;                                     // Indicates if A stage PC maps to a ROM address
  14.327 +reg irom_select_f;                                      // Indicates if F stage PC maps to a ROM address
  14.328 +wire [`LM32_INSTRUCTION_RNG] irom_data_f;               // Instruction fetched from ROM
  14.329 +`endif
  14.330 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  14.331 +`else
  14.332 +wire [`LM32_INSTRUCTION_RNG] instruction_f;             // F stage instruction
  14.333 +`endif
  14.334 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.335 +reg bus_error_f;                                        // Indicates if a bus error occured while fetching the instruction in the F stage
  14.336 +`endif
  14.337 +
  14.338 +`ifdef CFG_HW_DEBUG_ENABLED
  14.339 +reg jtag_access;                                        // Indicates if a JTAG WB access is in progress
  14.340 +`endif
  14.341 +
  14.342 +/////////////////////////////////////////////////////
  14.343 +// Functions
  14.344 +/////////////////////////////////////////////////////
  14.345 +
  14.346 +`include "lm32_functions.v"
  14.347 +
  14.348 +/////////////////////////////////////////////////////
  14.349 +// Instantiations
  14.350 +/////////////////////////////////////////////////////
  14.351 +
  14.352 +// Instruction ROM
  14.353 +`ifdef CFG_IROM_ENABLED  
  14.354 +   pmi_ram_dp_true 
  14.355 +     #(
  14.356 +       // ----- Parameters -------
  14.357 +       .pmi_family             (`LATTICE_FAMILY),
  14.358 +	 
  14.359 +       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  14.360 +       //.pmi_addr_width_a       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  14.361 +       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  14.362 +       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  14.363 +       //.pmi_addr_width_b       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
  14.364 +       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  14.365 +	 
  14.366 +       .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  14.367 +       .pmi_addr_width_a       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  14.368 +       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  14.369 +       .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
  14.370 +       .pmi_addr_width_b       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  14.371 +       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  14.372 +	 
  14.373 +       .pmi_regmode_a          ("noreg"),
  14.374 +       .pmi_regmode_b          ("noreg"),
  14.375 +       .pmi_gsr                ("enable"),
  14.376 +       .pmi_resetmode          ("sync"),
  14.377 +       .pmi_init_file          (`CFG_IROM_INIT_FILE),
  14.378 +       .pmi_init_file_format   (`CFG_IROM_INIT_FILE_FORMAT),
  14.379 +       .module_type            ("pmi_ram_dp_true")
  14.380 +       ) 
  14.381 +       ram (
  14.382 +	    // ----- Inputs -------
  14.383 +	    .ClockA                 (clk_i),
  14.384 +	    .ClockB                 (clk_i),
  14.385 +	    .ResetA                 (rst_i),
  14.386 +	    .ResetB                 (rst_i),
  14.387 +	    .DataInA                ({32{1'b0}}),
  14.388 +	    .DataInB                (irom_store_data_m),
  14.389 +	    .AddressA               (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  14.390 +	    .AddressB               (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  14.391 +	    .ClockEnA               (!stall_a),
  14.392 +	    .ClockEnB               (!stall_x || !stall_m),
  14.393 +	    .WrA                    (`FALSE),
  14.394 +	    .WrB                    (irom_we_xm), 
  14.395 +	    // ----- Outputs -------
  14.396 +	    .QA                     (irom_data_f),
  14.397 +	    .QB                     (irom_data_m)
  14.398 +	    );
  14.399 +`endif    
  14.400 + 
  14.401 +`ifdef CFG_ICACHE_ENABLED
  14.402 +// Instruction cache
  14.403 +lm32_icache #(
  14.404 +    .associativity          (associativity),
  14.405 +    .sets                   (sets),
  14.406 +    .bytes_per_line         (bytes_per_line),
  14.407 +    .base_address           (base_address),
  14.408 +    .limit                  (limit)
  14.409 +    ) icache ( 
  14.410 +    // ----- Inputs -----
  14.411 +    .clk_i                  (clk_i),
  14.412 +    .rst_i                  (rst_i),      
  14.413 +    .stall_a                (stall_a),
  14.414 +    .stall_f                (stall_f),
  14.415 +    .branch_predict_taken_d (branch_predict_taken_d),
  14.416 +    .valid_d                (valid_d),
  14.417 +    .address_a              (pc_a),
  14.418 +    .address_f              (pc_f),
  14.419 +    .read_enable_f          (icache_read_enable_f),
  14.420 +    .refill_ready           (icache_refill_ready),
  14.421 +    .refill_data            (icache_refill_data),
  14.422 +    .iflush                 (iflush),
  14.423 +    // ----- Outputs -----
  14.424 +    .stall_request          (icache_stall_request),
  14.425 +    .restart_request        (icache_restart_request),
  14.426 +    .refill_request         (icache_refill_request),
  14.427 +    .refill_address         (icache_refill_address),
  14.428 +    .refilling              (icache_refilling),
  14.429 +    .inst                   (icache_data_f)
  14.430 +    );
  14.431 +`endif
  14.432 +
  14.433 +/////////////////////////////////////////////////////
  14.434 +// Combinational Logic
  14.435 +/////////////////////////////////////////////////////
  14.436 +
  14.437 +`ifdef CFG_ICACHE_ENABLED
  14.438 +// Generate signal that indicates when instruction cache misses are valid
  14.439 +assign icache_read_enable_f =    (valid_f == `TRUE)
  14.440 +                              && (kill_f == `FALSE)
  14.441 +`ifdef CFG_DCACHE_ENABLED
  14.442 +                              && (dcache_restart_request == `FALSE)
  14.443 +`endif                         
  14.444 +`ifdef CFG_IROM_ENABLED 
  14.445 +                              && (irom_select_f == `FALSE)
  14.446 +`endif       
  14.447 +                              ;
  14.448 +`endif
  14.449 +
  14.450 +// Compute address of next instruction to fetch
  14.451 +always @(*)
  14.452 +begin
  14.453 +    // The request from the latest pipeline stage must take priority
  14.454 +`ifdef CFG_DCACHE_ENABLED
  14.455 +    if (dcache_restart_request == `TRUE)
  14.456 +        pc_a = restart_address;
  14.457 +    else 
  14.458 +`endif    
  14.459 +      if (branch_taken_m == `TRUE)
  14.460 +	if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
  14.461 +	  pc_a = pc_x;
  14.462 +	else
  14.463 +          pc_a = branch_target_m;
  14.464 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  14.465 +      else if (branch_taken_x == `TRUE)
  14.466 +        pc_a = branch_target_x;
  14.467 +`endif
  14.468 +      else
  14.469 +	if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
  14.470 +	  pc_a = branch_predict_address_d;
  14.471 +	else
  14.472 +`ifdef CFG_ICACHE_ENABLED
  14.473 +          if (icache_restart_request == `TRUE)
  14.474 +            pc_a = restart_address;
  14.475 +	  else 
  14.476 +`endif        
  14.477 +            pc_a = pc_f + 1'b1;
  14.478 +end
  14.479 +
  14.480 +// Select where instruction should be fetched from
  14.481 +`ifdef CFG_IROM_ENABLED
  14.482 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
  14.483 +`endif
  14.484 +                     
  14.485 +// Select instruction from selected source
  14.486 +`ifdef CFG_ICACHE_ENABLED
  14.487 +`ifdef CFG_IROM_ENABLED
  14.488 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
  14.489 +`else
  14.490 +assign instruction_f = icache_data_f;
  14.491 +`endif
  14.492 +`else
  14.493 +`ifdef CFG_IROM_ENABLED
  14.494 +`ifdef CFG_IWB_ENABLED
  14.495 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
  14.496 +`else
  14.497 +assign instruction_f = irom_data_f;
  14.498 +`endif
  14.499 +`else
  14.500 +assign instruction_f = wb_data_f;
  14.501 +`endif
  14.502 +`endif
  14.503 +
  14.504 +// Unused/constant Wishbone signals
  14.505 +`ifdef CFG_IWB_ENABLED
  14.506 +`ifdef CFG_HW_DEBUG_ENABLED
  14.507 +`else
  14.508 +assign i_dat_o = 32'd0;
  14.509 +assign i_we_o = `FALSE;
  14.510 +assign i_sel_o = 4'b1111;
  14.511 +`endif
  14.512 +assign i_bte_o = `LM32_BTYPE_LINEAR;
  14.513 +`endif
  14.514 +
  14.515 +`ifdef CFG_ICACHE_ENABLED
  14.516 +// Determine parameters for next cache refill Wishbone access                
  14.517 +generate
  14.518 +    case (bytes_per_line)
  14.519 +    4:
  14.520 +    begin
  14.521 +assign first_cycle_type = `LM32_CTYPE_END;
  14.522 +assign next_cycle_type = `LM32_CTYPE_END;
  14.523 +assign last_word = `TRUE;
  14.524 +assign first_address = icache_refill_address;
  14.525 +    end
  14.526 +    8:
  14.527 +    begin
  14.528 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  14.529 +assign next_cycle_type = `LM32_CTYPE_END;
  14.530 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
  14.531 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  14.532 +    end
  14.533 +    16:
  14.534 +    begin
  14.535 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
  14.536 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
  14.537 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
  14.538 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  14.539 +    end
  14.540 +    endcase
  14.541 +endgenerate
  14.542 +`endif
  14.543 +                     
  14.544 +/////////////////////////////////////////////////////
  14.545 +// Sequential Logic
  14.546 +/////////////////////////////////////////////////////
  14.547 +
  14.548 +// PC 
  14.549 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.550 +begin
  14.551 +    if (rst_i == `TRUE)
  14.552 +    begin
  14.553 +        pc_f <= (`CFG_EBA_RESET-4)/4;
  14.554 +        pc_d <= {`LM32_PC_WIDTH{1'b0}};
  14.555 +        pc_x <= {`LM32_PC_WIDTH{1'b0}};
  14.556 +        pc_m <= {`LM32_PC_WIDTH{1'b0}};
  14.557 +        pc_w <= {`LM32_PC_WIDTH{1'b0}};
  14.558 +    end
  14.559 +    else
  14.560 +    begin
  14.561 +        if (stall_f == `FALSE)
  14.562 +            pc_f <= pc_a;
  14.563 +        if (stall_d == `FALSE)
  14.564 +            pc_d <= pc_f;
  14.565 +        if (stall_x == `FALSE)
  14.566 +            pc_x <= pc_d;
  14.567 +        if (stall_m == `FALSE)
  14.568 +            pc_m <= pc_x;
  14.569 +        pc_w <= pc_m;
  14.570 +    end
  14.571 +end
  14.572 +
  14.573 +`ifdef LM32_CACHE_ENABLED
  14.574 +// Address to restart from after a cache miss has been handled
  14.575 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.576 +begin
  14.577 +    if (rst_i == `TRUE)
  14.578 +        restart_address <= {`LM32_PC_WIDTH{1'b0}};
  14.579 +    else
  14.580 +    begin
  14.581 +`ifdef CFG_DCACHE_ENABLED
  14.582 +`ifdef CFG_ICACHE_ENABLED        
  14.583 +            // D-cache restart address must take priority, otherwise instructions will be lost
  14.584 +            if (dcache_refill_request == `TRUE)
  14.585 +                restart_address <= pc_w;
  14.586 +            else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
  14.587 +                restart_address <= icache_refill_address;
  14.588 +`else
  14.589 +            if (dcache_refill_request == `TRUE)
  14.590 +                restart_address <= pc_w;
  14.591 +`endif
  14.592 +`else
  14.593 +`ifdef CFG_ICACHE_ENABLED        
  14.594 +            if (icache_refill_request == `TRUE)
  14.595 +                restart_address <= icache_refill_address;
  14.596 +`endif
  14.597 +`endif
  14.598 +    end
  14.599 +end
  14.600 +`endif
  14.601 +
  14.602 +// Record where instruction was fetched from
  14.603 +`ifdef CFG_IROM_ENABLED
  14.604 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.605 +begin
  14.606 +    if (rst_i == `TRUE)
  14.607 +        irom_select_f <= `FALSE;
  14.608 +    else
  14.609 +    begin
  14.610 +        if (stall_f == `FALSE)
  14.611 +            irom_select_f <= irom_select_a;
  14.612 +    end
  14.613 +end
  14.614 +`endif
  14.615 +
  14.616 +`ifdef CFG_HW_DEBUG_ENABLED
  14.617 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
  14.618 +always @(*)
  14.619 +begin
  14.620 +    case (jtag_address[1:0])
  14.621 +    2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
  14.622 +    2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
  14.623 +    2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
  14.624 +    2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
  14.625 +    endcase 
  14.626 +end
  14.627 +`endif
  14.628 +
  14.629 +`ifdef CFG_IWB_ENABLED
  14.630 +// Instruction Wishbone interface
  14.631 +`ifdef CFG_ICACHE_ENABLED                
  14.632 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.633 +begin
  14.634 +    if (rst_i == `TRUE)
  14.635 +    begin
  14.636 +        i_cyc_o <= `FALSE;
  14.637 +        i_stb_o <= `FALSE;
  14.638 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  14.639 +        i_cti_o <= `LM32_CTYPE_END;
  14.640 +        i_lock_o <= `FALSE;
  14.641 +        icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  14.642 +        icache_refill_ready <= `FALSE;
  14.643 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.644 +        bus_error_f <= `FALSE;
  14.645 +`endif
  14.646 +`ifdef CFG_HW_DEBUG_ENABLED
  14.647 +        i_we_o <= `FALSE;
  14.648 +        i_sel_o <= 4'b1111;
  14.649 +        jtag_access <= `FALSE;
  14.650 +`endif
  14.651 +    end
  14.652 +    else
  14.653 +    begin   
  14.654 +        icache_refill_ready <= `FALSE;
  14.655 +        // Is a cycle in progress?
  14.656 +        if (i_cyc_o == `TRUE)
  14.657 +        begin
  14.658 +            // Has cycle completed?
  14.659 +            if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  14.660 +            begin
  14.661 +`ifdef CFG_HW_DEBUG_ENABLED
  14.662 +                if (jtag_access == `TRUE)
  14.663 +                begin
  14.664 +                    i_cyc_o <= `FALSE;
  14.665 +                    i_stb_o <= `FALSE;       
  14.666 +                    i_we_o <= `FALSE;  
  14.667 +                    jtag_access <= `FALSE;    
  14.668 +                end
  14.669 +                else
  14.670 +`endif
  14.671 +                begin
  14.672 +                    if (last_word == `TRUE)
  14.673 +                    begin
  14.674 +                        // Cache line fill complete 
  14.675 +                        i_cyc_o <= `FALSE;
  14.676 +                        i_stb_o <= `FALSE;
  14.677 +                        i_lock_o <= `FALSE;
  14.678 +                    end
  14.679 +                    // Fetch next word in cache line
  14.680 +                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
  14.681 +                    i_cti_o <= next_cycle_type;
  14.682 +                    // Write fetched data into instruction cache
  14.683 +                    icache_refill_ready <= `TRUE;
  14.684 +                    icache_refill_data <= i_dat_i;
  14.685 +                end
  14.686 +            end
  14.687 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.688 +            if (i_err_i == `TRUE)
  14.689 +            begin
  14.690 +                bus_error_f <= `TRUE;
  14.691 +                $display ("Instruction bus error. Address: %x", i_adr_o);
  14.692 +            end
  14.693 +`endif
  14.694 +        end
  14.695 +        else
  14.696 +        begin
  14.697 +            if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
  14.698 +            begin
  14.699 +                // Read first word of cache line
  14.700 +`ifdef CFG_HW_DEBUG_ENABLED     
  14.701 +                i_sel_o <= 4'b1111;
  14.702 +`endif
  14.703 +                i_adr_o <= {first_address, 2'b00};
  14.704 +                i_cyc_o <= `TRUE;
  14.705 +                i_stb_o <= `TRUE;                
  14.706 +                i_cti_o <= first_cycle_type;
  14.707 +                //i_lock_o <= `TRUE;
  14.708 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.709 +                bus_error_f <= `FALSE;
  14.710 +`endif
  14.711 +            end
  14.712 +`ifdef CFG_HW_DEBUG_ENABLED
  14.713 +            else
  14.714 +            begin
  14.715 +                if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
  14.716 +                begin
  14.717 +                    case (jtag_address[1:0])
  14.718 +                    2'b00: i_sel_o <= 4'b1000;
  14.719 +                    2'b01: i_sel_o <= 4'b0100;
  14.720 +                    2'b10: i_sel_o <= 4'b0010;
  14.721 +                    2'b11: i_sel_o <= 4'b0001;
  14.722 +                    endcase
  14.723 +                    i_adr_o <= jtag_address;
  14.724 +                    i_dat_o <= {4{jtag_write_data}};
  14.725 +                    i_cyc_o <= `TRUE;
  14.726 +                    i_stb_o <= `TRUE;
  14.727 +                    i_we_o <= jtag_write_enable;
  14.728 +                    i_cti_o <= `LM32_CTYPE_END;
  14.729 +                    jtag_access <= `TRUE;
  14.730 +                end
  14.731 +            end 
  14.732 +`endif                    
  14.733 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.734 +            // Clear bus error when exception taken, otherwise they would be 
  14.735 +            // continually generated if exception handler is cached
  14.736 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  14.737 +            if (branch_taken_x == `TRUE)
  14.738 +                bus_error_f <= `FALSE;
  14.739 +`endif
  14.740 +            if (branch_taken_m == `TRUE)
  14.741 +                bus_error_f <= `FALSE;
  14.742 +`endif
  14.743 +        end
  14.744 +    end
  14.745 +end
  14.746 +`else
  14.747 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.748 +begin
  14.749 +    if (rst_i == `TRUE)
  14.750 +    begin
  14.751 +        i_cyc_o <= `FALSE;
  14.752 +        i_stb_o <= `FALSE;
  14.753 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
  14.754 +        i_cti_o <= `LM32_CTYPE_END;
  14.755 +        i_lock_o <= `FALSE;
  14.756 +        wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  14.757 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.758 +        bus_error_f <= `FALSE;
  14.759 +`endif
  14.760 +    end
  14.761 +    else
  14.762 +    begin   
  14.763 +        // Is a cycle in progress?
  14.764 +        if (i_cyc_o == `TRUE)
  14.765 +        begin
  14.766 +            // Has cycle completed?
  14.767 +            if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
  14.768 +            begin
  14.769 +                // Cycle complete
  14.770 +                i_cyc_o <= `FALSE;
  14.771 +                i_stb_o <= `FALSE;
  14.772 +                // Register fetched instruction
  14.773 +                wb_data_f <= i_dat_i;
  14.774 +            end
  14.775 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.776 +            if (i_err_i == `TRUE)
  14.777 +            begin
  14.778 +                bus_error_f <= `TRUE;
  14.779 +                $display ("Instruction bus error. Address: %x", i_adr_o);
  14.780 +            end
  14.781 +`endif
  14.782 +        end
  14.783 +        else
  14.784 +        begin
  14.785 +            // Wait for an instruction fetch from an external address 
  14.786 +            if (   (stall_a == `FALSE) 
  14.787 +`ifdef CFG_IROM_ENABLED 
  14.788 +                && (irom_select_a == `FALSE)
  14.789 +`endif       
  14.790 +               )
  14.791 +            begin
  14.792 +                // Fetch instruction
  14.793 +`ifdef CFG_HW_DEBUG_ENABLED     
  14.794 +                i_sel_o <= 4'b1111;
  14.795 +`endif
  14.796 +                i_adr_o <= {pc_a, 2'b00};
  14.797 +                i_cyc_o <= `TRUE;
  14.798 +                i_stb_o <= `TRUE;
  14.799 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.800 +                bus_error_f <= `FALSE;
  14.801 +`endif
  14.802 +            end
  14.803 +	    else
  14.804 +	    begin
  14.805 +	        if (   (stall_a == `FALSE) 
  14.806 +`ifdef CFG_IROM_ENABLED 
  14.807 +		    && (irom_select_a == `TRUE)
  14.808 +`endif       
  14.809 +	           )
  14.810 +		begin
  14.811 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.812 +		    bus_error_f <= `FALSE;
  14.813 +`endif
  14.814 +		end
  14.815 +	    end
  14.816 +        end
  14.817 +    end
  14.818 +end
  14.819 +`endif
  14.820 +`endif
  14.821 +
  14.822 +// Instruction register
  14.823 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  14.824 +begin
  14.825 +    if (rst_i == `TRUE)
  14.826 +    begin
  14.827 +        instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
  14.828 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.829 +        bus_error_d <= `FALSE;
  14.830 +`endif
  14.831 +    end
  14.832 +    else
  14.833 +    begin
  14.834 +        if (stall_d == `FALSE)
  14.835 +        begin
  14.836 +            instruction_d <= instruction_f;
  14.837 +`ifdef CFG_BUS_ERRORS_ENABLED
  14.838 +            bus_error_d <= bus_error_f;
  14.839 +`endif
  14.840 +        end
  14.841 +    end
  14.842 +end  
  14.843 +  
  14.844 +endmodule
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/lm32_interrupt.v	Sun Apr 04 20:40:03 2010 +0100
    15.3 @@ -0,0 +1,335 @@
    15.4 +// =============================================================================
    15.5 +//                           COPYRIGHT NOTICE
    15.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    15.7 +// ALL RIGHTS RESERVED
    15.8 +// This confidential and proprietary software may be used only as authorised by
    15.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   15.10 +// The entire notice above must be reproduced on all authorized copies and
   15.11 +// copies may only be made to the extent permitted by a licensing agreement from
   15.12 +// Lattice Semiconductor Corporation.
   15.13 +//
   15.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   15.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   15.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   15.17 +// U.S.A                                   email: techsupport@latticesemi.com
   15.18 +// =============================================================================/
   15.19 +//                         FILE DETAILS
   15.20 +// Project          : LatticeMico32
   15.21 +// File             : lm32_interrupt.v
   15.22 +// Title            : Interrupt logic
   15.23 +// Dependencies     : lm32_include.v
   15.24 +// Version          : 6.1.17
   15.25 +//                  : Initial Release
   15.26 +// Version          : 7.0SP2, 3.0
   15.27 +//                  : No Change
   15.28 +// Version          : 3.1
   15.29 +//                  : No Change
   15.30 +// =============================================================================
   15.31 +
   15.32 +`include "lm32_include.v"
   15.33 +
   15.34 +/////////////////////////////////////////////////////
   15.35 +// Module interface
   15.36 +/////////////////////////////////////////////////////
   15.37 +
   15.38 +module lm32_interrupt (
   15.39 +    // ----- Inputs -------
   15.40 +    clk_i, 
   15.41 +    rst_i,
   15.42 +    // From external devices
   15.43 +    interrupt_n,
   15.44 +    // From pipeline
   15.45 +    stall_x,
   15.46 +`ifdef CFG_DEBUG_ENABLED
   15.47 +    non_debug_exception,
   15.48 +    debug_exception,
   15.49 +`else
   15.50 +    exception,
   15.51 +`endif
   15.52 +    eret_q_x,
   15.53 +`ifdef CFG_DEBUG_ENABLED
   15.54 +    bret_q_x,
   15.55 +`endif
   15.56 +    csr,
   15.57 +    csr_write_data,
   15.58 +    csr_write_enable,
   15.59 +    // ----- Outputs -------
   15.60 +    interrupt_exception,
   15.61 +    // To pipeline
   15.62 +    csr_read_data
   15.63 +    );
   15.64 +
   15.65 +/////////////////////////////////////////////////////
   15.66 +// Parameters
   15.67 +/////////////////////////////////////////////////////
   15.68 +
   15.69 +parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
   15.70 +
   15.71 +/////////////////////////////////////////////////////
   15.72 +// Inputs
   15.73 +/////////////////////////////////////////////////////
   15.74 +
   15.75 +input clk_i;                                    // Clock
   15.76 +input rst_i;                                    // Reset
   15.77 +
   15.78 +input [interrupts-1:0] interrupt_n;             // Interrupt pins, active-low
   15.79 +                           
   15.80 +input stall_x;                                  // Stall X pipeline stage
   15.81 +
   15.82 +`ifdef CFG_DEBUG_ENABLED
   15.83 +input non_debug_exception;                      // Non-debug related exception has been raised
   15.84 +input debug_exception;                          // Debug-related exception has been raised
   15.85 +`else
   15.86 +input exception;                                // Exception has been raised
   15.87 +`endif
   15.88 +input eret_q_x;                                 // Return from exception 
   15.89 +`ifdef CFG_DEBUG_ENABLED
   15.90 +input bret_q_x;                                 // Return from breakpoint 
   15.91 +`endif
   15.92 +
   15.93 +input [`LM32_CSR_RNG] csr;                      // CSR read/write index
   15.94 +input [`LM32_WORD_RNG] csr_write_data;          // Data to write to specified CSR
   15.95 +input csr_write_enable;                         // CSR write enable
   15.96 +
   15.97 +/////////////////////////////////////////////////////
   15.98 +// Outputs
   15.99 +/////////////////////////////////////////////////////
  15.100 +
  15.101 +output interrupt_exception;                     // Request to raide an interrupt exception
  15.102 +wire   interrupt_exception;
  15.103 +
  15.104 +output [`LM32_WORD_RNG] csr_read_data;          // Data read from CSR
  15.105 +reg    [`LM32_WORD_RNG] csr_read_data;
  15.106 +
  15.107 +/////////////////////////////////////////////////////
  15.108 +// Internal nets and registers 
  15.109 +/////////////////////////////////////////////////////
  15.110 +
  15.111 +wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
  15.112 +//pragma attribute asserted preserve_signal true
  15.113 +wire [interrupts-1:0] interrupt_n_exception;
  15.114 +
  15.115 +// Interrupt CSRs
  15.116 +
  15.117 +reg ie;                                         // Interrupt enable
  15.118 +reg eie;                                        // Exception interrupt enable
  15.119 +`ifdef CFG_DEBUG_ENABLED
  15.120 +reg bie;                                        // Breakpoint interrupt enable
  15.121 +`endif
  15.122 +reg [interrupts-1:0] ip;                        // Interrupt pending
  15.123 +reg [interrupts-1:0] im;                        // Interrupt mask
  15.124 +
  15.125 +/////////////////////////////////////////////////////
  15.126 +// Combinational Logic
  15.127 +/////////////////////////////////////////////////////
  15.128 +
  15.129 +// Determine which interrupts have occured and are unmasked
  15.130 +assign interrupt_n_exception = ip & im;
  15.131 +
  15.132 +// Determine if any unmasked interrupts have occured
  15.133 +assign interrupt_exception = (|interrupt_n_exception) & ie;
  15.134 +
  15.135 +// Determine which interrupts are currently being asserted (active-low) or are already pending
  15.136 +assign asserted = ip | ~interrupt_n;
  15.137 +       
  15.138 +assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  15.139 +`ifdef CFG_DEBUG_ENABLED
  15.140 +                           bie,
  15.141 +`else
  15.142 +                           1'b0,
  15.143 +`endif                             
  15.144 +                           eie, 
  15.145 +                           ie
  15.146 +                          };
  15.147 +assign ip_csr_read_data = ip;
  15.148 +assign im_csr_read_data = im;
  15.149 +generate
  15.150 +    if (interrupts > 1) 
  15.151 +    begin
  15.152 +// CSR read
  15.153 +always @(*)
  15.154 +begin
  15.155 +    case (csr)
  15.156 +    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  15.157 +`ifdef CFG_DEBUG_ENABLED
  15.158 +                                    bie,
  15.159 +`else
  15.160 +                                    1'b0,                                     
  15.161 +`endif
  15.162 +                                    eie, 
  15.163 +                                    ie
  15.164 +                                   };
  15.165 +    `LM32_CSR_IP:  csr_read_data = ip;
  15.166 +    `LM32_CSR_IM:  csr_read_data = im;
  15.167 +    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  15.168 +    endcase
  15.169 +end
  15.170 +    end
  15.171 +    else
  15.172 +    begin
  15.173 +// CSR read
  15.174 +always @(*)
  15.175 +begin
  15.176 +    case (csr)
  15.177 +    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
  15.178 +`ifdef CFG_DEBUG_ENABLED
  15.179 +                                    bie, 
  15.180 +`else
  15.181 +                                    1'b0,                                    
  15.182 +`endif
  15.183 +                                    eie, 
  15.184 +                                    ie
  15.185 +                                   };
  15.186 +    `LM32_CSR_IP:  csr_read_data = ip;
  15.187 +    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
  15.188 +    endcase
  15.189 +end
  15.190 +    end
  15.191 +endgenerate
  15.192 +    
  15.193 +/////////////////////////////////////////////////////
  15.194 +// Sequential Logic
  15.195 +/////////////////////////////////////////////////////
  15.196 +
  15.197 +generate
  15.198 +    if (interrupts > 1)
  15.199 +    begin
  15.200 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  15.201 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  15.202 +begin
  15.203 +    if (rst_i == `TRUE)
  15.204 +    begin
  15.205 +        ie <= `FALSE;
  15.206 +        eie <= `FALSE;
  15.207 +`ifdef CFG_DEBUG_ENABLED
  15.208 +        bie <= `FALSE;
  15.209 +`endif
  15.210 +        im <= {interrupts{1'b0}};
  15.211 +        ip <= {interrupts{1'b0}};
  15.212 +    end
  15.213 +    else
  15.214 +    begin
  15.215 +        // Set IP bit when interrupt line is asserted
  15.216 +        ip <= asserted;
  15.217 +`ifdef CFG_DEBUG_ENABLED
  15.218 +        if (non_debug_exception == `TRUE)
  15.219 +        begin
  15.220 +            // Save and then clear interrupt enable
  15.221 +            eie <= ie;
  15.222 +            ie <= `FALSE;
  15.223 +        end
  15.224 +        else if (debug_exception == `TRUE)
  15.225 +        begin
  15.226 +            // Save and then clear interrupt enable
  15.227 +            bie <= ie;
  15.228 +            ie <= `FALSE;
  15.229 +        end
  15.230 +`else
  15.231 +        if (exception == `TRUE)
  15.232 +        begin
  15.233 +            // Save and then clear interrupt enable
  15.234 +            eie <= ie;
  15.235 +            ie <= `FALSE;
  15.236 +        end
  15.237 +`endif
  15.238 +        else if (stall_x == `FALSE)
  15.239 +        begin
  15.240 +            if (eret_q_x == `TRUE)
  15.241 +                // Restore interrupt enable
  15.242 +                ie <= eie;          
  15.243 +`ifdef CFG_DEBUG_ENABLED
  15.244 +            else if (bret_q_x == `TRUE)
  15.245 +                // Restore interrupt enable
  15.246 +                ie <= bie;
  15.247 +`endif
  15.248 +            else if (csr_write_enable == `TRUE)
  15.249 +            begin
  15.250 +                // Handle wcsr write
  15.251 +                if (csr == `LM32_CSR_IE)
  15.252 +                begin
  15.253 +                    ie <= csr_write_data[0];
  15.254 +                    eie <= csr_write_data[1];
  15.255 +`ifdef CFG_DEBUG_ENABLED
  15.256 +                    bie <= csr_write_data[2];
  15.257 +`endif
  15.258 +                end
  15.259 +                if (csr == `LM32_CSR_IM)
  15.260 +                    im <= csr_write_data[interrupts-1:0];
  15.261 +                if (csr == `LM32_CSR_IP)
  15.262 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  15.263 +            end
  15.264 +        end
  15.265 +    end
  15.266 +end
  15.267 +    end
  15.268 +else
  15.269 +    begin
  15.270 +// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
  15.271 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  15.272 +begin
  15.273 +    if (rst_i == `TRUE)
  15.274 +    begin
  15.275 +        ie <= `FALSE;
  15.276 +        eie <= `FALSE;
  15.277 +`ifdef CFG_DEBUG_ENABLED
  15.278 +        bie <= `FALSE;
  15.279 +`endif
  15.280 +        ip <= {interrupts{1'b0}};
  15.281 +    end
  15.282 +    else
  15.283 +    begin
  15.284 +        // Set IP bit when interrupt line is asserted
  15.285 +        ip <= asserted;
  15.286 +`ifdef CFG_DEBUG_ENABLED
  15.287 +        if (non_debug_exception == `TRUE)
  15.288 +        begin
  15.289 +            // Save and then clear interrupt enable
  15.290 +            eie <= ie;
  15.291 +            ie <= `FALSE;
  15.292 +        end
  15.293 +        else if (debug_exception == `TRUE)
  15.294 +        begin
  15.295 +            // Save and then clear interrupt enable
  15.296 +            bie <= ie;
  15.297 +            ie <= `FALSE;
  15.298 +        end
  15.299 +`else
  15.300 +        if (exception == `TRUE)
  15.301 +        begin
  15.302 +            // Save and then clear interrupt enable
  15.303 +            eie <= ie;
  15.304 +            ie <= `FALSE;
  15.305 +        end
  15.306 +`endif
  15.307 +        else if (stall_x == `FALSE)
  15.308 +        begin
  15.309 +            if (eret_q_x == `TRUE)
  15.310 +                // Restore interrupt enable
  15.311 +                ie <= eie;          
  15.312 +`ifdef CFG_DEBUG_ENABLED
  15.313 +            else if (bret_q_x == `TRUE)
  15.314 +                // Restore interrupt enable
  15.315 +                ie <= bie;
  15.316 +`endif
  15.317 +            else if (csr_write_enable == `TRUE)
  15.318 +            begin
  15.319 +                // Handle wcsr write
  15.320 +                if (csr == `LM32_CSR_IE)
  15.321 +                begin
  15.322 +                    ie <= csr_write_data[0];
  15.323 +                    eie <= csr_write_data[1];
  15.324 +`ifdef CFG_DEBUG_ENABLED
  15.325 +                    bie <= csr_write_data[2];
  15.326 +`endif
  15.327 +                end
  15.328 +                if (csr == `LM32_CSR_IP)
  15.329 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
  15.330 +            end
  15.331 +        end
  15.332 +    end
  15.333 +end
  15.334 +    end
  15.335 +endgenerate
  15.336 +
  15.337 +endmodule
  15.338 +
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/lm32_jtag.v	Sun Apr 04 20:40:03 2010 +0100
    16.3 @@ -0,0 +1,479 @@
    16.4 +// =============================================================================
    16.5 +//                           COPYRIGHT NOTICE
    16.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    16.7 +// ALL RIGHTS RESERVED
    16.8 +// This confidential and proprietary software may be used only as authorised by
    16.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   16.10 +// The entire notice above must be reproduced on all authorized copies and
   16.11 +// copies may only be made to the extent permitted by a licensing agreement from
   16.12 +// Lattice Semiconductor Corporation.
   16.13 +//
   16.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   16.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   16.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   16.17 +// U.S.A                                   email: techsupport@latticesemi.com
   16.18 +// =============================================================================/
   16.19 +//                         FILE DETAILS
   16.20 +// Project          : LatticeMico32
   16.21 +// File             : lm32_jtag.v
   16.22 +// Title            : JTAG interface
   16.23 +// Dependencies     : lm32_include.v
   16.24 +// Version          : 6.1.17
   16.25 +//                  : Initial Release
   16.26 +// Version          : 7.0SP2, 3.0
   16.27 +//                  : No Change
   16.28 +// Version          : 3.1
   16.29 +//                  : No Change
   16.30 +// =============================================================================
   16.31 +
   16.32 +`include "lm32_include.v"
   16.33 +
   16.34 +`ifdef CFG_JTAG_ENABLED
   16.35 +
   16.36 +`define LM32_DP                             3'b000
   16.37 +`define LM32_TX                             3'b001
   16.38 +`define LM32_RX                             3'b010
   16.39 +
   16.40 +// LM32 Debug Protocol commands IDs
   16.41 +`define LM32_DP_RNG                         3:0
   16.42 +`define LM32_DP_READ_MEMORY                 4'b0001
   16.43 +`define LM32_DP_WRITE_MEMORY                4'b0010
   16.44 +`define LM32_DP_READ_SEQUENTIAL             4'b0011
   16.45 +`define LM32_DP_WRITE_SEQUENTIAL            4'b0100
   16.46 +`define LM32_DP_WRITE_CSR                   4'b0101
   16.47 +`define LM32_DP_BREAK                       4'b0110
   16.48 +`define LM32_DP_RESET                       4'b0111
   16.49 +
   16.50 +// States for FSM
   16.51 +`define LM32_JTAG_STATE_RNG                 3:0
   16.52 +`define LM32_JTAG_STATE_READ_COMMAND        4'h0
   16.53 +`define LM32_JTAG_STATE_READ_BYTE_0         4'h1
   16.54 +`define LM32_JTAG_STATE_READ_BYTE_1         4'h2
   16.55 +`define LM32_JTAG_STATE_READ_BYTE_2         4'h3
   16.56 +`define LM32_JTAG_STATE_READ_BYTE_3         4'h4
   16.57 +`define LM32_JTAG_STATE_READ_BYTE_4         4'h5
   16.58 +`define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
   16.59 +`define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
   16.60 +`define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
   16.61 +
   16.62 +/////////////////////////////////////////////////////
   16.63 +// Module interface
   16.64 +/////////////////////////////////////////////////////
   16.65 +
   16.66 +module lm32_jtag (
   16.67 +    // ----- Inputs -------
   16.68 +    clk_i,
   16.69 +    rst_i,
   16.70 +    jtag_clk, 
   16.71 +    jtag_update,
   16.72 +    jtag_reg_q,
   16.73 +    jtag_reg_addr_q,
   16.74 +`ifdef CFG_JTAG_UART_ENABLED
   16.75 +    csr,
   16.76 +    csr_write_enable,
   16.77 +    csr_write_data,
   16.78 +    stall_x,
   16.79 +`endif
   16.80 +`ifdef CFG_HW_DEBUG_ENABLED
   16.81 +    jtag_read_data,
   16.82 +    jtag_access_complete,
   16.83 +`endif
   16.84 +`ifdef CFG_DEBUG_ENABLED
   16.85 +    exception_q_w,
   16.86 +`endif
   16.87 +    // ----- Outputs -------
   16.88 +`ifdef CFG_JTAG_UART_ENABLED
   16.89 +    jtx_csr_read_data,
   16.90 +    jrx_csr_read_data,
   16.91 +`endif
   16.92 +`ifdef CFG_HW_DEBUG_ENABLED
   16.93 +    jtag_csr_write_enable,
   16.94 +    jtag_csr_write_data,
   16.95 +    jtag_csr,
   16.96 +    jtag_read_enable,
   16.97 +    jtag_write_enable,
   16.98 +    jtag_write_data,
   16.99 +    jtag_address,
  16.100 +`endif
  16.101 +`ifdef CFG_DEBUG_ENABLED
  16.102 +    jtag_break,
  16.103 +    jtag_reset,
  16.104 +`endif
  16.105 +    jtag_reg_d,
  16.106 +    jtag_reg_addr_d
  16.107 +    );
  16.108 +
  16.109 +   parameter lat_family = `LATTICE_FAMILY;
  16.110 +   
  16.111 +/////////////////////////////////////////////////////
  16.112 +// Inputs
  16.113 +/////////////////////////////////////////////////////
  16.114 +
  16.115 +input clk_i;                                            // Clock
  16.116 +input rst_i;                                            // Reset
  16.117 +
  16.118 +input jtag_clk;                                         // JTAG clock
  16.119 +input jtag_update;                                      // JTAG data register has been updated
  16.120 +input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
  16.121 +input [2:0] jtag_reg_addr_q;                            // JTAG data register
  16.122 +
  16.123 +`ifdef CFG_JTAG_UART_ENABLED
  16.124 +input [`LM32_CSR_RNG] csr;                              // CSR to write
  16.125 +input csr_write_enable;                                 // CSR write enable
  16.126 +input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
  16.127 +input stall_x;                                          // Stall instruction in X stage
  16.128 +`endif
  16.129 +`ifdef CFG_HW_DEBUG_ENABLED
  16.130 +input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
  16.131 +input jtag_access_complete;                             // Memory access if complete
  16.132 +`endif
  16.133 +`ifdef CFG_DEBUG_ENABLED
  16.134 +input exception_q_w;                                    // Indicates an exception has occured in W stage
  16.135 +`endif
  16.136 +
  16.137 +/////////////////////////////////////////////////////
  16.138 +// Outputs
  16.139 +/////////////////////////////////////////////////////
  16.140 +       
  16.141 +`ifdef CFG_JTAG_UART_ENABLED
  16.142 +output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
  16.143 +wire   [`LM32_WORD_RNG] jtx_csr_read_data;
  16.144 +output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
  16.145 +wire   [`LM32_WORD_RNG] jrx_csr_read_data;
  16.146 +`endif
  16.147 +`ifdef CFG_HW_DEBUG_ENABLED
  16.148 +output jtag_csr_write_enable;                           // CSR write enable
  16.149 +reg    jtag_csr_write_enable;
  16.150 +output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
  16.151 +wire   [`LM32_WORD_RNG] jtag_csr_write_data;
  16.152 +output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
  16.153 +wire   [`LM32_CSR_RNG] jtag_csr;
  16.154 +output jtag_read_enable;                                // Memory read enable
  16.155 +reg    jtag_read_enable;
  16.156 +output jtag_write_enable;                               // Memory write enable
  16.157 +reg    jtag_write_enable;
  16.158 +output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
  16.159 +wire   [`LM32_BYTE_RNG] jtag_write_data;        
  16.160 +output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
  16.161 +wire   [`LM32_WORD_RNG] jtag_address;
  16.162 +`endif
  16.163 +`ifdef CFG_DEBUG_ENABLED
  16.164 +output jtag_break;                                      // Request to raise a breakpoint exception
  16.165 +reg    jtag_break;
  16.166 +output jtag_reset;                                      // Request to raise a reset exception
  16.167 +reg    jtag_reset;
  16.168 +`endif
  16.169 +output [`LM32_BYTE_RNG] jtag_reg_d;
  16.170 +reg    [`LM32_BYTE_RNG] jtag_reg_d;
  16.171 +output [2:0] jtag_reg_addr_d;
  16.172 +wire   [2:0] jtag_reg_addr_d;
  16.173 +             
  16.174 +/////////////////////////////////////////////////////
  16.175 +// Internal nets and registers 
  16.176 +/////////////////////////////////////////////////////
  16.177 +
  16.178 +reg rx_toggle;                          // Clock-domain crossing registers
  16.179 +reg rx_toggle_r;                        // Registered version of rx_toggle
  16.180 +reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
  16.181 +reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
  16.182 +
  16.183 +reg [`LM32_BYTE_RNG] rx_byte;   
  16.184 +reg [2:0] rx_addr;
  16.185 +
  16.186 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.187 +reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
  16.188 +reg uart_tx_valid;                      // TX data is valid
  16.189 +reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
  16.190 +reg uart_rx_valid;                      // RX data is valid
  16.191 +`endif
  16.192 +
  16.193 +reg [`LM32_DP_RNG] command;             // The last received command
  16.194 +`ifdef CFG_HW_DEBUG_ENABLED
  16.195 +reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
  16.196 +reg [`LM32_BYTE_RNG] jtag_byte_1;
  16.197 +reg [`LM32_BYTE_RNG] jtag_byte_2;
  16.198 +reg [`LM32_BYTE_RNG] jtag_byte_3;
  16.199 +reg [`LM32_BYTE_RNG] jtag_byte_4;
  16.200 +reg processing;                         // Indicates if we're still processing a memory read/write
  16.201 +`endif
  16.202 +
  16.203 +reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
  16.204 +
  16.205 +/////////////////////////////////////////////////////
  16.206 +// Combinational Logic
  16.207 +/////////////////////////////////////////////////////
  16.208 +
  16.209 +`ifdef CFG_HW_DEBUG_ENABLED
  16.210 +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  16.211 +assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
  16.212 +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
  16.213 +assign jtag_write_data = jtag_byte_4;
  16.214 +`endif
  16.215 +                 
  16.216 +// Generate status flags for reading via the JTAG interface                 
  16.217 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.218 +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
  16.219 +`else
  16.220 +assign jtag_reg_addr_d[1:0] = 2'b00;
  16.221 +`endif
  16.222 +`ifdef CFG_HW_DEBUG_ENABLED
  16.223 +assign jtag_reg_addr_d[2] = processing;
  16.224 +`else
  16.225 +assign jtag_reg_addr_d[2] = 1'b0;
  16.226 +`endif
  16.227 +
  16.228 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.229 +assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
  16.230 +assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
  16.231 +`endif         
  16.232 +                 
  16.233 +/////////////////////////////////////////////////////
  16.234 +// Sequential Logic
  16.235 +/////////////////////////////////////////////////////
  16.236 +
  16.237 +// Toggle a flag when a JTAG write occurs
  16.238 + 
  16.239 +always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
  16.240 +begin
  16.241 +if (rst_i == `TRUE)
  16.242 +  rx_toggle <= 1'b0;
  16.243 +else 
  16.244 +  rx_toggle <= ~rx_toggle;
  16.245 +end
  16.246 +
  16.247 +always @(*)
  16.248 +begin
  16.249 +    rx_byte = jtag_reg_q;
  16.250 +    rx_addr = jtag_reg_addr_q;
  16.251 +end
  16.252 +
  16.253 +// Clock domain crossing from JTAG clock domain to CPU clock domain
  16.254 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  16.255 +begin
  16.256 +    if (rst_i == `TRUE)
  16.257 +    begin
  16.258 +        rx_toggle_r <= 1'b0;
  16.259 +        rx_toggle_r_r <= 1'b0;
  16.260 +        rx_toggle_r_r_r <= 1'b0;
  16.261 +    end
  16.262 +    else
  16.263 +    begin
  16.264 +        rx_toggle_r <= rx_toggle;
  16.265 +        rx_toggle_r_r <= rx_toggle_r;
  16.266 +        rx_toggle_r_r_r <= rx_toggle_r_r;
  16.267 +    end
  16.268 +end
  16.269 +
  16.270 +// LM32 debug protocol state machine
  16.271 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  16.272 +begin
  16.273 +    if (rst_i == `TRUE)
  16.274 +    begin
  16.275 +        state <= `LM32_JTAG_STATE_READ_COMMAND;
  16.276 +        command <= 4'b0000;
  16.277 +        jtag_reg_d <= 8'h00;
  16.278 +`ifdef CFG_HW_DEBUG_ENABLED
  16.279 +        processing <= `FALSE;
  16.280 +        jtag_csr_write_enable <= `FALSE;
  16.281 +        jtag_read_enable <= `FALSE;
  16.282 +        jtag_write_enable <= `FALSE;
  16.283 +`endif
  16.284 +`ifdef CFG_DEBUG_ENABLED
  16.285 +        jtag_break <= `FALSE;
  16.286 +        jtag_reset <= `FALSE;
  16.287 +`endif
  16.288 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.289 +        uart_tx_byte <= 8'h00;
  16.290 +        uart_tx_valid <= `FALSE;
  16.291 +        uart_rx_byte <= 8'h00;
  16.292 +        uart_rx_valid <= `FALSE;
  16.293 +`endif
  16.294 +    end
  16.295 +    else
  16.296 +    begin
  16.297 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.298 +        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
  16.299 +        begin
  16.300 +            case (csr)
  16.301 +            `LM32_CSR_JTX:
  16.302 +            begin
  16.303 +                // Set flag indicating data is available
  16.304 +                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
  16.305 +                uart_tx_valid <= `TRUE;
  16.306 +            end
  16.307 +            `LM32_CSR_JRX:
  16.308 +            begin
  16.309 +                // Clear flag indidicating data has been received
  16.310 +                uart_rx_valid <= `FALSE;
  16.311 +            end
  16.312 +            endcase
  16.313 +        end
  16.314 +`endif
  16.315 +`ifdef CFG_DEBUG_ENABLED
  16.316 +        // When an exception has occured, clear the requests
  16.317 +        if (exception_q_w == `TRUE)
  16.318 +        begin
  16.319 +            jtag_break <= `FALSE;
  16.320 +            jtag_reset <= `FALSE;
  16.321 +        end
  16.322 +`endif
  16.323 +        case (state)
  16.324 +        `LM32_JTAG_STATE_READ_COMMAND:
  16.325 +        begin
  16.326 +            // Wait for rx register to toggle which indicates new data is available
  16.327 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.328 +            begin
  16.329 +                command <= rx_byte[7:4];                
  16.330 +                case (rx_addr)
  16.331 +`ifdef CFG_DEBUG_ENABLED
  16.332 +                `LM32_DP:
  16.333 +                begin
  16.334 +                    case (rx_byte[7:4])
  16.335 +`ifdef CFG_HW_DEBUG_ENABLED
  16.336 +                    `LM32_DP_READ_MEMORY:
  16.337 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  16.338 +                    `LM32_DP_READ_SEQUENTIAL:
  16.339 +                    begin
  16.340 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  16.341 +                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  16.342 +                    end
  16.343 +                    `LM32_DP_WRITE_MEMORY:
  16.344 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  16.345 +                    `LM32_DP_WRITE_SEQUENTIAL:
  16.346 +                    begin
  16.347 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
  16.348 +                        state <= 5;
  16.349 +                    end
  16.350 +                    `LM32_DP_WRITE_CSR:
  16.351 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
  16.352 +`endif                    
  16.353 +                    `LM32_DP_BREAK:
  16.354 +                    begin
  16.355 +`ifdef CFG_JTAG_UART_ENABLED     
  16.356 +                        uart_rx_valid <= `FALSE;    
  16.357 +                        uart_tx_valid <= `FALSE;         
  16.358 +`endif
  16.359 +                        jtag_break <= `TRUE;
  16.360 +                    end
  16.361 +                    `LM32_DP_RESET:
  16.362 +                    begin
  16.363 +`ifdef CFG_JTAG_UART_ENABLED     
  16.364 +                        uart_rx_valid <= `FALSE;    
  16.365 +                        uart_tx_valid <= `FALSE;         
  16.366 +`endif
  16.367 +                        jtag_reset <= `TRUE;
  16.368 +                    end
  16.369 +                    endcase                               
  16.370 +                end
  16.371 +`endif
  16.372 +`ifdef CFG_JTAG_UART_ENABLED                 
  16.373 +                `LM32_TX:
  16.374 +                begin
  16.375 +                    uart_rx_byte <= rx_byte;
  16.376 +                    uart_rx_valid <= `TRUE;
  16.377 +                end                    
  16.378 +                `LM32_RX:
  16.379 +                begin
  16.380 +                    jtag_reg_d <= uart_tx_byte;
  16.381 +                    uart_tx_valid <= `FALSE;
  16.382 +                end
  16.383 +`endif
  16.384 +                default:
  16.385 +                    ;
  16.386 +                endcase                
  16.387 +            end
  16.388 +        end
  16.389 +`ifdef CFG_HW_DEBUG_ENABLED
  16.390 +        `LM32_JTAG_STATE_READ_BYTE_0:
  16.391 +        begin
  16.392 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.393 +            begin
  16.394 +                jtag_byte_0 <= rx_byte;
  16.395 +                state <= `LM32_JTAG_STATE_READ_BYTE_1;
  16.396 +            end
  16.397 +        end
  16.398 +        `LM32_JTAG_STATE_READ_BYTE_1:
  16.399 +        begin
  16.400 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.401 +            begin
  16.402 +                jtag_byte_1 <= rx_byte;
  16.403 +                state <= `LM32_JTAG_STATE_READ_BYTE_2;
  16.404 +            end
  16.405 +        end
  16.406 +        `LM32_JTAG_STATE_READ_BYTE_2:
  16.407 +        begin
  16.408 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.409 +            begin
  16.410 +                jtag_byte_2 <= rx_byte;
  16.411 +                state <= `LM32_JTAG_STATE_READ_BYTE_3;
  16.412 +            end
  16.413 +        end
  16.414 +        `LM32_JTAG_STATE_READ_BYTE_3:
  16.415 +        begin
  16.416 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.417 +            begin
  16.418 +                jtag_byte_3 <= rx_byte;
  16.419 +                if (command == `LM32_DP_READ_MEMORY)
  16.420 +                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  16.421 +                else 
  16.422 +                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
  16.423 +            end
  16.424 +        end
  16.425 +        `LM32_JTAG_STATE_READ_BYTE_4:
  16.426 +        begin
  16.427 +            if (rx_toggle_r_r != rx_toggle_r_r_r)
  16.428 +            begin
  16.429 +                jtag_byte_4 <= rx_byte;
  16.430 +                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
  16.431 +            end
  16.432 +        end
  16.433 +        `LM32_JTAG_STATE_PROCESS_COMMAND:
  16.434 +        begin
  16.435 +            case (command)
  16.436 +            `LM32_DP_READ_MEMORY,
  16.437 +            `LM32_DP_READ_SEQUENTIAL:
  16.438 +            begin
  16.439 +                jtag_read_enable <= `TRUE;
  16.440 +                processing <= `TRUE;
  16.441 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  16.442 +            end
  16.443 +            `LM32_DP_WRITE_MEMORY,
  16.444 +            `LM32_DP_WRITE_SEQUENTIAL:
  16.445 +            begin
  16.446 +                jtag_write_enable <= `TRUE;
  16.447 +                processing <= `TRUE;
  16.448 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
  16.449 +            end
  16.450 +            `LM32_DP_WRITE_CSR:
  16.451 +            begin
  16.452 +                jtag_csr_write_enable <= `TRUE;
  16.453 +                processing <= `TRUE;
  16.454 +                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
  16.455 +            end
  16.456 +            endcase
  16.457 +        end
  16.458 +        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
  16.459 +        begin
  16.460 +            if (jtag_access_complete == `TRUE)
  16.461 +            begin          
  16.462 +                jtag_read_enable <= `FALSE;
  16.463 +                jtag_reg_d <= jtag_read_data;
  16.464 +                jtag_write_enable <= `FALSE;  
  16.465 +                processing <= `FALSE;
  16.466 +                state <= `LM32_JTAG_STATE_READ_COMMAND;
  16.467 +            end
  16.468 +        end    
  16.469 +        `LM32_JTAG_STATE_WAIT_FOR_CSR:
  16.470 +        begin
  16.471 +            jtag_csr_write_enable <= `FALSE;
  16.472 +            processing <= `FALSE;
  16.473 +            state <= `LM32_JTAG_STATE_READ_COMMAND;
  16.474 +        end    
  16.475 +`endif
  16.476 +        endcase
  16.477 +    end
  16.478 +end
  16.479 +  
  16.480 +endmodule
  16.481 +
  16.482 +`endif
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/lm32_load_store_unit.v	Sun Apr 04 20:40:03 2010 +0100
    17.3 @@ -0,0 +1,808 @@
    17.4 +// =============================================================================
    17.5 +//                           COPYRIGHT NOTICE
    17.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    17.7 +// ALL RIGHTS RESERVED
    17.8 +// This confidential and proprietary software may be used only as authorised by
    17.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   17.10 +// The entire notice above must be reproduced on all authorized copies and
   17.11 +// copies may only be made to the extent permitted by a licensing agreement from
   17.12 +// Lattice Semiconductor Corporation.
   17.13 +//
   17.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   17.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   17.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   17.17 +// U.S.A                                   email: techsupport@latticesemi.com
   17.18 +// =============================================================================/
   17.19 +//                         FILE DETAILS
   17.20 +// Project      : LatticeMico32
   17.21 +// File         : lm32_load_store_unit.v
   17.22 +// Title        : Load and store unit
   17.23 +// Dependencies : lm32_include.v
   17.24 +// Version      : 6.1.17
   17.25 +//              : Initial Release
   17.26 +// Version      : 7.0SP2, 3.0
   17.27 +//              : No Change
   17.28 +// Version      : 3.1
   17.29 +//              : Instead of disallowing an instruction cache miss on a data cache 
   17.30 +//              : miss, both can now occur at the same time. If both occur at same 
   17.31 +//              : time, then restart address is the address of instruction that 
   17.32 +//              : caused data cache miss.
   17.33 +// Version      : 3.2
   17.34 +//              : EBRs use SYNC resets instead of ASYNC resets.
   17.35 +// Version      : 3.3
   17.36 +//              : Support for new non-cacheable Data Memory that is accessible by 
   17.37 +//              : the data port and has a one cycle access latency.
   17.38 +// Version      : 3.4
   17.39 +//              : No change
   17.40 +// Version      : 3.5
   17.41 +//              : Bug fix: Inline memory is correctly generated if it is not a
   17.42 +//              : power-of-two
   17.43 +// =============================================================================
   17.44 +
   17.45 +`include "lm32_include.v"
   17.46 +
   17.47 +/////////////////////////////////////////////////////
   17.48 +// Module interface
   17.49 +/////////////////////////////////////////////////////
   17.50 +
   17.51 +module lm32_load_store_unit (
   17.52 +    // ----- Inputs -------
   17.53 +    clk_i,
   17.54 +    rst_i,
   17.55 +    // From pipeline
   17.56 +    stall_a,
   17.57 +    stall_x,
   17.58 +    stall_m,
   17.59 +    kill_x,
   17.60 +    kill_m,
   17.61 +    exception_m,
   17.62 +    store_operand_x,
   17.63 +    load_store_address_x,
   17.64 +    load_store_address_m,
   17.65 +    load_store_address_w,
   17.66 +    load_x,
   17.67 +    store_x,
   17.68 +    load_q_x,
   17.69 +    store_q_x,
   17.70 +    load_q_m,
   17.71 +    store_q_m,
   17.72 +    sign_extend_x,
   17.73 +    size_x,
   17.74 +`ifdef CFG_DCACHE_ENABLED
   17.75 +    dflush,
   17.76 +`endif
   17.77 +`ifdef CFG_IROM_ENABLED
   17.78 +    irom_data_m,
   17.79 +`endif
   17.80 +    // From Wishbone
   17.81 +    d_dat_i,
   17.82 +    d_ack_i,
   17.83 +    d_err_i,
   17.84 +    d_rty_i,
   17.85 +    // ----- Outputs -------
   17.86 +    // To pipeline
   17.87 +`ifdef CFG_DCACHE_ENABLED
   17.88 +    dcache_refill_request,
   17.89 +    dcache_restart_request,
   17.90 +    dcache_stall_request,
   17.91 +    dcache_refilling,
   17.92 +`endif    
   17.93 +`ifdef CFG_IROM_ENABLED
   17.94 +    irom_store_data_m,
   17.95 +    irom_address_xm,
   17.96 +    irom_we_xm,
   17.97 +    irom_stall_request_x,
   17.98 +`endif			     
   17.99 +    load_data_w,
  17.100 +    stall_wb_load,
  17.101 +    // To Wishbone
  17.102 +    d_dat_o,
  17.103 +    d_adr_o,
  17.104 +    d_cyc_o,
  17.105 +    d_sel_o,
  17.106 +    d_stb_o,
  17.107 +    d_we_o,
  17.108 +    d_cti_o,
  17.109 +    d_lock_o,
  17.110 +    d_bte_o
  17.111 +    );
  17.112 +
  17.113 +/////////////////////////////////////////////////////
  17.114 +// Parameters
  17.115 +/////////////////////////////////////////////////////
  17.116 +
  17.117 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
  17.118 +parameter sets = 512;                                   // Number of sets
  17.119 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
  17.120 +parameter base_address = 0;                             // Base address of cachable memory
  17.121 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
  17.122 +
  17.123 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
  17.124 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
  17.125 +localparam addr_offset_lsb = 2;
  17.126 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
  17.127 +
  17.128 +/////////////////////////////////////////////////////
  17.129 +// Inputs
  17.130 +/////////////////////////////////////////////////////
  17.131 +
  17.132 +input clk_i;                                            // Clock 
  17.133 +input rst_i;                                            // Reset
  17.134 +
  17.135 +input stall_a;                                          // A stage stall 
  17.136 +input stall_x;                                          // X stage stall        
  17.137 +input stall_m;                                          // M stage stall
  17.138 +input kill_x;                                           // Kill instruction in X stage
  17.139 +input kill_m;                                           // Kill instruction in M stage
  17.140 +input exception_m;                                      // An exception occured in the M stage
  17.141 +
  17.142 +input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
  17.143 +input [`LM32_WORD_RNG] load_store_address_x;            // X stage load/store address
  17.144 +input [`LM32_WORD_RNG] load_store_address_m;            // M stage load/store address
  17.145 +input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
  17.146 +input load_x;                                           // Load instruction in X stage
  17.147 +input store_x;                                          // Store instruction in X stage
  17.148 +input load_q_x;                                         // Load instruction in X stage
  17.149 +input store_q_x;                                        // Store instruction in X stage
  17.150 +input load_q_m;                                         // Load instruction in M stage
  17.151 +input store_q_m;                                        // Store instruction in M stage
  17.152 +input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
  17.153 +input [`LM32_SIZE_RNG] size_x;                          // Size of load or store (byte, hword, word)
  17.154 +
  17.155 +`ifdef CFG_DCACHE_ENABLED
  17.156 +input dflush;                                           // Flush the data cache
  17.157 +`endif
  17.158 +
  17.159 +`ifdef CFG_IROM_ENABLED   
  17.160 +input [`LM32_WORD_RNG] irom_data_m;                     // Data from Instruction-ROM
  17.161 +`endif
  17.162 +
  17.163 +input [`LM32_WORD_RNG] d_dat_i;                         // Data Wishbone interface read data
  17.164 +input d_ack_i;                                          // Data Wishbone interface acknowledgement
  17.165 +input d_err_i;                                          // Data Wishbone interface error
  17.166 +input d_rty_i;                                          // Data Wishbone interface retry
  17.167 +
  17.168 +/////////////////////////////////////////////////////
  17.169 +// Outputs
  17.170 +/////////////////////////////////////////////////////
  17.171 +
  17.172 +`ifdef CFG_DCACHE_ENABLED
  17.173 +output dcache_refill_request;                           // Request to refill data cache
  17.174 +wire   dcache_refill_request;
  17.175 +output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
  17.176 +wire   dcache_restart_request;
  17.177 +output dcache_stall_request;                            // Data cache stall request
  17.178 +wire   dcache_stall_request;
  17.179 +output dcache_refilling;
  17.180 +wire   dcache_refilling;
  17.181 +`endif
  17.182 +
  17.183 +`ifdef CFG_IROM_ENABLED   
  17.184 +output irom_store_data_m;                               // Store data to Instruction ROM
  17.185 +wire   [`LM32_WORD_RNG] irom_store_data_m;
  17.186 +output [`LM32_WORD_RNG] irom_address_xm;                // Load/store address to Instruction ROM
  17.187 +wire   [`LM32_WORD_RNG] irom_address_xm;
  17.188 +output irom_we_xm;                                      // Write-enable of 2nd port of Instruction ROM
  17.189 +wire   irom_we_xm;
  17.190 +output irom_stall_request_x;                            // Stall instruction in D stage  
  17.191 +wire   irom_stall_request_x;                            
  17.192 +`endif
  17.193 +   
  17.194 +output [`LM32_WORD_RNG] load_data_w;                    // Result of a load instruction
  17.195 +reg    [`LM32_WORD_RNG] load_data_w;
  17.196 +output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
  17.197 +reg    stall_wb_load;
  17.198 +
  17.199 +output [`LM32_WORD_RNG] d_dat_o;                        // Data Wishbone interface write data
  17.200 +reg    [`LM32_WORD_RNG] d_dat_o;
  17.201 +output [`LM32_WORD_RNG] d_adr_o;                        // Data Wishbone interface address
  17.202 +reg    [`LM32_WORD_RNG] d_adr_o;
  17.203 +output d_cyc_o;                                         // Data Wishbone interface cycle
  17.204 +reg    d_cyc_o;
  17.205 +output [`LM32_BYTE_SELECT_RNG] d_sel_o;                 // Data Wishbone interface byte select
  17.206 +reg    [`LM32_BYTE_SELECT_RNG] d_sel_o;
  17.207 +output d_stb_o;                                         // Data Wishbone interface strobe
  17.208 +reg    d_stb_o; 
  17.209 +output d_we_o;                                          // Data Wishbone interface write enable
  17.210 +reg    d_we_o;
  17.211 +output [`LM32_CTYPE_RNG] d_cti_o;                       // Data Wishbone interface cycle type 
  17.212 +reg    [`LM32_CTYPE_RNG] d_cti_o;
  17.213 +output d_lock_o;                                        // Date Wishbone interface lock bus
  17.214 +reg    d_lock_o;
  17.215 +output [`LM32_BTYPE_RNG] d_bte_o;                       // Data Wishbone interface burst type 
  17.216 +wire   [`LM32_BTYPE_RNG] d_bte_o;
  17.217 +
  17.218 +/////////////////////////////////////////////////////
  17.219 +// Internal nets and registers 
  17.220 +/////////////////////////////////////////////////////
  17.221 +
  17.222 +// Microcode pipeline registers - See inputs for description
  17.223 +reg [`LM32_SIZE_RNG] size_m;
  17.224 +reg [`LM32_SIZE_RNG] size_w;
  17.225 +reg sign_extend_m;
  17.226 +reg sign_extend_w;
  17.227 +reg [`LM32_WORD_RNG] store_data_x;       
  17.228 +reg [`LM32_WORD_RNG] store_data_m;       
  17.229 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
  17.230 +reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
  17.231 +wire [`LM32_WORD_RNG] data_m;
  17.232 +reg [`LM32_WORD_RNG] data_w;
  17.233 +
  17.234 +`ifdef CFG_DCACHE_ENABLED
  17.235 +wire dcache_select_x;                                   // Select data cache to load from / store to
  17.236 +reg dcache_select_m;
  17.237 +wire [`LM32_WORD_RNG] dcache_data_m;                    // Data read from cache
  17.238 +wire [`LM32_WORD_RNG] dcache_refill_address;            // Address to refill data cache from
  17.239 +reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
  17.240 +wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
  17.241 +wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
  17.242 +wire last_word;                                         // Indicates if this is the last word in the cache line
  17.243 +wire [`LM32_WORD_RNG] first_address;                    // First cache refill address
  17.244 +`endif
  17.245 +`ifdef CFG_DRAM_ENABLED
  17.246 +wire dram_select_x;                                     // Select data RAM to load from / store to
  17.247 +reg dram_select_m;
  17.248 +reg dram_bypass_en;                                     // RAW in data RAM; read latched (bypass) value rather than value from memory
  17.249 +reg [`LM32_WORD_RNG] dram_bypass_data;                  // Latched value of store'd data to data RAM
  17.250 +wire [`LM32_WORD_RNG] dram_data_out;                    // Data read from data RAM
  17.251 +wire [`LM32_WORD_RNG] dram_data_m;                      // Data read from data RAM: bypass value or value from memory
  17.252 +wire [`LM32_WORD_RNG] dram_store_data_m;                // Data to write to RAM
  17.253 +`endif
  17.254 +wire wb_select_x;                                       // Select Wishbone to load from / store to
  17.255 +`ifdef CFG_IROM_ENABLED
  17.256 +wire irom_select_x;                                     // Select instruction ROM to load from / store to
  17.257 +reg  irom_select_m;
  17.258 +`endif
  17.259 +reg wb_select_m;
  17.260 +reg [`LM32_WORD_RNG] wb_data_m;                         // Data read from Wishbone
  17.261 +reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
  17.262 +
  17.263 +/////////////////////////////////////////////////////
  17.264 +// Functions
  17.265 +/////////////////////////////////////////////////////
  17.266 +
  17.267 +`include "lm32_functions.v"
  17.268 +
  17.269 +/////////////////////////////////////////////////////
  17.270 +// Instantiations
  17.271 +/////////////////////////////////////////////////////
  17.272 +
  17.273 +`ifdef CFG_DRAM_ENABLED
  17.274 +   // Data RAM
  17.275 +   pmi_ram_dp_true 
  17.276 +     #(
  17.277 +       // ----- Parameters -------
  17.278 +       .pmi_family             (`LATTICE_FAMILY),
  17.279 +
  17.280 +       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  17.281 +       //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  17.282 +       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
  17.283 +       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  17.284 +       //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
  17.285 +       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
  17.286 +	
  17.287 +       .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  17.288 +       .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  17.289 +       .pmi_data_width_a       (`LM32_WORD_WIDTH),
  17.290 +       .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
  17.291 +       .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  17.292 +       .pmi_data_width_b       (`LM32_WORD_WIDTH),
  17.293 +
  17.294 +       .pmi_regmode_a          ("noreg"),
  17.295 +       .pmi_regmode_b          ("noreg"),
  17.296 +       .pmi_gsr                ("enable"),
  17.297 +       .pmi_resetmode          ("sync"),
  17.298 +       .pmi_init_file          (`CFG_DRAM_INIT_FILE),
  17.299 +       .pmi_init_file_format   (`CFG_DRAM_INIT_FILE_FORMAT),
  17.300 +       .module_type            ("pmi_ram_dp_true")
  17.301 +       ) 
  17.302 +       ram (
  17.303 +	    // ----- Inputs -------
  17.304 +	    .ClockA                 (clk_i),
  17.305 +	    .ClockB                 (clk_i),
  17.306 +	    .ResetA                 (rst_i),
  17.307 +	    .ResetB                 (rst_i),
  17.308 +	    .DataInA                ({32{1'b0}}),
  17.309 +	    .DataInB                (dram_store_data_m),
  17.310 +	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
  17.311 +	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_L