Initial commit, DMAC version 3.1

Fri, 13 Aug 2010 10:43:05 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 13 Aug 2010 10:43:05 +0100
changeset 0
11aef665a5d8
child 1
522426d22baa

Initial commit, DMAC version 3.1

dma.xml file | annotate | diff | revisions
document/dma.htm file | annotate | diff | revisions
document/dma.pdf file | annotate | diff | revisions
document/ds_icon.jpg file | annotate | diff | revisions
document/ds_icon_ast.jpg file | annotate | diff | revisions
document/dsb_icon.jpg file | annotate | diff | revisions
document/lever40.css file | annotate | diff | revisions
document/lever40_ns.css file | annotate | diff | revisions
document/qm_icon.jpg file | annotate | diff | revisions
drivers/device/MicoDMA.c file | annotate | diff | revisions
drivers/device/MicoDMA.h file | annotate | diff | revisions
drivers/peripheral.mk file | annotate | diff | revisions
drivers/service/MicoDMAService.c file | annotate | diff | revisions
drivers/service/MicoDMAService.h file | annotate | diff | revisions
rtl/verilog/master_ctrl.v file | annotate | diff | revisions
rtl/verilog/slave_reg.v file | annotate | diff | revisions
rtl/verilog/wb_dma_ctrl.v file | annotate | diff | revisions
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/dma.xml	Fri Aug 13 10:43:05 2010 +0100
     1.3 @@ -0,0 +1,52 @@
     1.4 +<?xml version="1.0" encoding="UTF-8"?>
     1.5 +<Component Name="wb_dma_ctrl" Text="DMA" Type="IO" Ver="3.1" Help="wb_dma_ctrl\document\dma.htm">
     1.6 +      <MasterSlavePorts>
     1.7 +            <MasterPort Prefix="MA" Name="Read Master Port" Type="DMAR" Priority="2" />
     1.8 +            <MasterPort Prefix="MB" Name="Write Master Port" Type="DMAW" Priority="3"/>
     1.9 +            <SlavePort Prefix="S" Name="Control Port" Type="DATA"/>
    1.10 +      </MasterSlavePorts>
    1.11 +      <ClockPort Name="CLK_I " Description="Clock one"/>
    1.12 +      <ResetPort Name="RST_I " Description="Reset"/>
    1.13 +      <Interrupt Name="S_INT_O" Active="high" IRQ=""/>
    1.14 +      <Files>
    1.15 +	    <File Name="../components/wb_dma_ctrl/rtl/verilog/master_ctrl.v" />
    1.16 +	    <File Name="../components/wb_dma_ctrl/rtl/verilog/slave_reg.v" />
    1.17 +	    <File Name="../components/wb_dma_ctrl/rtl/verilog/wb_dma_ctrl.v" />
    1.18 +      </Files>
    1.19 +      <DeviceDriver InitRoutine="MicoDMAInit" StructName="MicoDMACtx_t">
    1.20 +	<DDInclude Include="LookupServices.h"/>
    1.21 +        <DDstruct>
    1.22 +           <DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string"/>
    1.23 +	   <DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" />
    1.24 +	   <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type = "uninitialized" Value=""/>
    1.25 +           <DDSElem MemberName = "irq" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" />
    1.26 +           <DDSElem MemberName = "maxLength" MemberType = "unsigned int" Type = "Parm" Value = "LENGTH_WIDTH" />
    1.27 +           <DDSElem MemberName = "flags" MemberType = "unsigned int" Type = "uninitialized" Value = "" />
    1.28 +           <DDSElem MemberName = "pCurr" MemberType = "void *" Type = "uninitialized" Value = "" />
    1.29 +	   <DDSElem MemberName = "pHead" MemberType = "void *" Type = "uninitialized" Value = "" />
    1.30 +           <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" />
    1.31 +           <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" />
    1.32 +        </DDstruct>
    1.33 +      </DeviceDriver>
    1.34 +      <PMIDef>
    1.35 +	    <Module Name="pmi_fifo" />
    1.36 +	    <Module Name="pmi_fifo_dc" />
    1.37 +      </PMIDef>
    1.38 +      <Parms>
    1.39 +            <Parm Name="InstanceName"    Value="dma"     Type="string" isiname="true" Text="Instance Name"/>
    1.40 +            <Parm Name="BASE_ADDRESS"    Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/>
    1.41 +            <Parm Name="FIFO_IMPLEMENTATION"  Value="EBR" Type="String" ListValues="EBR,LUT" Text="FIFO Implementation" isparm="true"/>
    1.42 +            <Parm Name="SIZE"            Value="128"         Type="Integer" issize="true" Text="Size" Enable="false"/>
    1.43 +            <Parm Name="DISABLE" Type="define" Value="undef" isdisable="true" Text="Disable Component"/>
    1.44 +            <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address "/>
    1.45 +            <Parm Name="LENGTH_WIDTH"    Value="16" Type="Integer" ValueRange="1-32" Text="Length Width" isparm="true"/>
    1.46 +      </Parms>
    1.47 +      <GUIS Columns="2" Help="document\dma.htm" Name="WB_DMA_CTRL">
    1.48 +            <GUI Widget="Text" Span="1" Name="InstanceName" Width="40"/>
    1.49 +            <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/>
    1.50 +            <GUI Widget="Combo" Span="1" Name="FIFO_IMPLEMENTATION"/>
    1.51 +            <GUI Widget="Group" Span="2" Name="SETTINGS" Text="Settings" Columns="3"/>
    1.52 +            <GUI Widget="Label" Span="1" Name=""/>
    1.53 +            <GUI Widget="Spinner" Span="1" Name="LENGTH_WIDTH"/>
    1.54 +      </GUIS>
    1.55 +</Component>
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/document/dma.htm	Fri Aug 13 10:43:05 2010 +0100
     2.3 @@ -0,0 +1,251 @@
     2.4 +<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
     2.5 +
     2.6 +<html>
     2.7 +
     2.8 +<head>
     2.9 +<title>DMA Controller</title>
    2.10 +<meta http-equiv="content-type" content="text/html; charset=windows-1252">
    2.11 +<meta name="generator" content="RoboHelp by eHelp Corporation www.ehelp.com">
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    2.80 +<script type="text/javascript" language="javascript" src="whver.js"></script>
    2.81 +<script type="text/javascript" language="javascript1.2" src="whproxy.js"></script>
    2.82 +<script type="text/javascript" language="javascript1.2" src="whutils.js"></script>
    2.83 +<script type="text/javascript" language="javascript1.2" src="whtopic.js"></script>
    2.84 +<script type="text/javascript" language="javascript1.2">
    2.85 +<!--
    2.86 +if (window.gbWhTopic)
    2.87 +{
    2.88 +	if (window.setRelStartPage)
    2.89 +	{
    2.90 +	addTocInfo("DMA");
    2.91 +
    2.92 +	}
    2.93 +
    2.94 +
    2.95 +	if (window.setRelStartPage)
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   2.110 +</head>
   2.111 +<body><script type="text/javascript" language="javascript1.2">
   2.112 +<!--
   2.113 +if (window.writeIntopicBar)
   2.114 +	writeIntopicBar(4);
   2.115 +//-->
   2.116 +</script>
   2.117 +<h1>LatticeMico32 DMA Controller &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Data Sheet" href="dma.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   2.118 +
   2.119 +<p>The LatticeMico32 direct memory access controller (DMA) provides a master 
   2.120 + read port, a master write port, and a slave port to control data transmission. 
   2.121 + </p>
   2.122 +
   2.123 +<p class="whs2"><span style="font-style: italic;"><I>*If the 
   2.124 + data sheet fails to open, see the note at the bottom of this page.</I></span></p>
   2.125 +
   2.126 +<h2>Revision History </h2>
   2.127 +
   2.128 +<table x-use-null-cells cellspacing="0" width="637" height="84" class="whs3">
   2.129 +<script language='JavaScript'><!--
   2.130 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='637' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   2.131 +//--></script>
   2.132 +<col class="whs4">
   2.133 +<col class="whs5">
   2.134 +
   2.135 +<tr valign="top" class="whs6">
   2.136 +<td bgcolor="#DEE8F4" width="86px" class="whs7">
   2.137 +<p class=Table
   2.138 +	style="font-weight: bold;">Version</td>
   2.139 +<td bgcolor="#DEE8F4" width="504px" class="whs8">
   2.140 +<p class=Table
   2.141 +	style="font-weight: bold;">Description</td></tr>
   2.142 +
   2.143 +<tr valign="top" class="whs6">
   2.144 +<td colspan="1" rowspan="1" width="86px" class="whs9">
   2.145 +<p class=Table
   2.146 +	style="font-weight: normal;">3.1 (8.0)</td>
   2.147 +<td colspan="1" rowspan="1" width="504px" class="whs10">
   2.148 +<p class=Table>DMA Engine upgraded to comply with Rule 3.100 of Wishbone 
   2.149 + Specifications, which deal with byte alignment for transfers that are 
   2.150 + less than the width of Wishbone data bus.</td></tr>
   2.151 +
   2.152 +<tr valign="top" class="whs6">
   2.153 +<td colspan="1" rowspan="1" width="86px" class="whs9">
   2.154 +<p class=Table
   2.155 +	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   2.156 + (7.0 SP2)</span></td>
   2.157 +<td colspan="1" rowspan="1" width="504px" class="whs10">
   2.158 +<p class=Table>Because the read and write channel worked in parallel, the 
   2.159 + write channel started writing data to the slave as soon as the FIFO is 
   2.160 + not empty.</p>
   2.161 +<p class=Table>Increased burst size to support bigger bursts from a current 
   2.162 + value of 4 and 8 to 16 and 32, respectively. DMA now supports four burst 
   2.163 + sizes: 4, 8, 16, and 32. The Burst Size field of the control register 
   2.164 + was increased to 2 bits.</p>
   2.165 +<p class=Table>A glitch was removed on the S_ACK_O signal.</td></tr>
   2.166 +
   2.167 +<tr valign="top" class="whs6">
   2.168 +<td colspan="1" rowspan="1" width="86px" class="whs9">
   2.169 +<p class="whs11">1.0</td>
   2.170 +<td colspan="1" rowspan="1" width="504px" class="whs10">
   2.171 +<p class=Table>Initial release.</td></tr>
   2.172 +<script language='JavaScript'><!--
   2.173 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   2.174 +//--></script>
   2.175 +</table>
   2.176 +
   2.177 +&nbsp; 
   2.178 +
   2.179 +<h2>Dialog Box Parameters</h2>
   2.180 +
   2.181 +<table x-use-null-cells cellspacing="0" class="whs12">
   2.182 +<script language='JavaScript'><!--
   2.183 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   2.184 +//--></script>
   2.185 +<col>
   2.186 +<col>
   2.187 +
   2.188 +<tr valign="top" class="whs13">
   2.189 +<td bgcolor="#DEE8F4" class="whs14">
   2.190 +<p class=Table
   2.191 +	style="font-weight: bold; margin-right: 2px;">Parameter</td>
   2.192 +<td bgcolor="#DEE8F4" class="whs15">
   2.193 +<p class=Table
   2.194 +	style="font-weight: bold;">Description</td></tr>
   2.195 +
   2.196 +<tr valign="top" class="whs13">
   2.197 +<td colspan="1" rowspan="1" class="whs16">
   2.198 +<p class=Table
   2.199 +	style="margin-right: 2px;">Instance Name</td>
   2.200 +<td colspan="1" rowspan="1" class="whs17">
   2.201 +<p class=Table>Specifies the name of the DMA controller instance. Alphanumeric 
   2.202 + values and underscores are supported. The default is dma.</td></tr>
   2.203 +
   2.204 +<tr valign="top" class="whs13">
   2.205 +<td colspan="1" rowspan="1" class="whs16">
   2.206 +<p class=Table
   2.207 +	style="margin-right: 2px;">Base Address</td>
   2.208 +<td colspan="1" rowspan="1" class="whs17">
   2.209 +<p class=Table>Specifies the base address for accessing the internal registers. 
   2.210 + The minimum boundary alignment is 0X80. Supported values are 0X80000000 
   2.211 + to 0XFFFFFFFF. The default is 0X80000000.</td></tr>
   2.212 +
   2.213 +<tr valign="top" class="whs13">
   2.214 +<td colspan="1" rowspan="1" class="whs18">
   2.215 +<p class=Table
   2.216 +	style="margin-right: 2px;">FIFO Implementation</td>
   2.217 +<td colspan="1" rowspan="1" class="whs19">
   2.218 +<p class=Table>Determines whether the FIFO is implemented as an EBR or 
   2.219 + a LUT. The default is EBR.</td></tr>
   2.220 +
   2.221 +<tr valign="top" class="whs13">
   2.222 +<td colspan="1" rowspan="1" class="whs18">
   2.223 +<p class=Table
   2.224 +	style="margin-right: 2px;">Length Width</td>
   2.225 +<td colspan="1" rowspan="1" class="whs19">
   2.226 +<p class=Table>Specifies the number of bits in the length register. The 
   2.227 + length register holds a count value that determines the number of DMA 
   2.228 + transactions to be performed. Supported values are 1 to 32. The default 
   2.229 + is 16. The default value permits up to 65535 (0XFFFF) memory transactions 
   2.230 + to be performed.</td></tr>
   2.231 +<script language='JavaScript'><!--
   2.232 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   2.233 +//--></script>
   2.234 +</table>
   2.235 +
   2.236 +&nbsp; 
   2.237 +
   2.238 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the data sheet fails 
   2.239 + to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs20"> on the Available Components toolbar, and 
   2.240 + then click the note button.</p>
   2.241 +
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   2.250 +	writeIntopicBar(0);
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   2.253 +</body>
   2.254 +</html>
     3.1 Binary file document/dma.pdf has changed
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     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
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     9.1 Binary file document/qm_icon.jpg has changed
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/drivers/device/MicoDMA.c	Fri Aug 13 10:43:05 2010 +0100
    10.3 @@ -0,0 +1,376 @@
    10.4 +/****************************************************************************
    10.5 +**
    10.6 +**  Name: MicoDMA.c
    10.7 +**
    10.8 +**  Description:
    10.9 +**        Implements functions for manipulating LatticeMico32 DMA
   10.10 +**
   10.11 +**  Revision: 3.0
   10.12 +**
   10.13 +** Disclaimer:
   10.14 +**
   10.15 +**   This source code is intended as a design reference which
   10.16 +**   illustrates how these types of functions can be implemented.  It
   10.17 +**   is the user's responsibility to verify their design for
   10.18 +**   consistency and functionality through the use of formal
   10.19 +**   verification methods.  Lattice Semiconductor provides no warranty
   10.20 +**   regarding the use or functionality of this code.
   10.21 +**
   10.22 +** --------------------------------------------------------------------
   10.23 +**
   10.24 +**                     Lattice Semiconductor Corporation
   10.25 +**                     5555 NE Moore Court
   10.26 +**                     Hillsboro, OR 97214
   10.27 +**                     U.S.A
   10.28 +**
   10.29 +**                     TEL: 1-800-Lattice (USA and Canada)
   10.30 +**                          (503)268-8001 (other locations)
   10.31 +**
   10.32 +**                     web:   http://www.latticesemi.com
   10.33 +**                     email: techsupport@latticesemi.com
   10.34 +**
   10.35 +** --------------------------------------------------------------------------
   10.36 +**
   10.37 +**  Change History (Latest changes on top)
   10.38 +**
   10.39 +**  Ver    Date        Description
   10.40 +** --------------------------------------------------------------------------
   10.41 +**
   10.42 +**  3.0   Mar-25-2008  Added Header
   10.43 +**
   10.44 +**---------------------------------------------------------------------------
   10.45 +*****************************************************************************/
   10.46 +
   10.47 +
   10.48 +#include "MicoDMA.h"
   10.49 +#include "MicoDMAService.h"
   10.50 +#include "MicoInterrupts.h"
   10.51 +
   10.52 +
   10.53 +#ifdef __cplusplus
   10.54 +extern "C" {
   10.55 +#endif
   10.56 +
   10.57 +#define MICODMA_CTX_DMA_PAUSED  (0x00000001)
   10.58 +
   10.59 +
   10.60 +/* program a DMA operation based on the descriptor contents */
   10.61 +static void MicoDMA_Program(unsigned int DMABase, DMADesc_t *desc)
   10.62 +{
   10.63 +    volatile MicoDMA_t *dma = (volatile MicoDMA_t *)DMABase;
   10.64 +
   10.65 +    /* program the source-address */
   10.66 +    dma->sAddr = desc->sAddr;
   10.67 +
   10.68 +    /* program the destination-address */
   10.69 +    dma->dAddr = desc->dAddr;
   10.70 +
   10.71 +    /* program length */
   10.72 +    dma->len = desc->reserved;
   10.73 +
   10.74 +    /* program type */
   10.75 +    dma->control = desc->type;
   10.76 +
   10.77 +    /* start DMA */
   10.78 +    dma->status = (MICODMA_STATUS_IE|MICODMA_STATUS_START);
   10.79 +
   10.80 +    /* all done */
   10.81 +    return;
   10.82 +}
   10.83 +
   10.84 +
   10.85 +/* handles interrupts from the DMA device */
   10.86 +static void MicoDMA_ISR(unsigned int isrCtx, void *data)
   10.87 +{
   10.88 +    volatile unsigned int iStatus;
   10.89 +    DMADesc_t *desc;    
   10.90 +    MicoDMACtx_t *ctx;
   10.91 +    volatile MicoDMA_t *dma;
   10.92 +
   10.93 +    ctx = (MicoDMACtx_t *)data;
   10.94 +    dma = (volatile MicoDMA_t *)ctx->base;
   10.95 +    desc = (DMADesc_t *)ctx->pHead;
   10.96 +
   10.97 +
   10.98 +    /* read the status: this acknowledges device's interrupt */
   10.99 +    iStatus = dma->status;
  10.100 +
  10.101 +    /* if this is a spurious interrupt, ignore it */
  10.102 +    if(desc == 0){
  10.103 +        return;
  10.104 +    }
  10.105 +
  10.106 +    /* set the head-descriptor's status accordingly */
  10.107 +    desc->state = ((iStatus & MICODMA_STATUS_SUCCESS) == 0)?MICODMA_STATE_SUCCESS:
  10.108 +        MICODMA_STATE_ERROR;
  10.109 +
  10.110 +    /* fetch the next descriptor */
  10.111 +    if(desc->next == desc){
  10.112 +        /* this was the last descriptor in the list */
  10.113 +        ctx->pHead = 0;
  10.114 +    }else{
  10.115 +        /* there are more descriptors queued up */
  10.116 +        desc->prev->next = desc->next;
  10.117 +        desc->next->prev = desc->prev;
  10.118 +        ctx->pHead = (void *)desc->next;
  10.119 +    }
  10.120 +    
  10.121 +    /* invoke the callback routine if there's one specified */
  10.122 +    if(desc->onCompletion)
  10.123 +        desc->onCompletion(desc, desc->state);
  10.124 +
  10.125 +
  10.126 +    /* 
  10.127 +     * If pause-flag isn't set, go ahead and start
  10.128 +     * the next dma transaction
  10.129 +     */
  10.130 +    if( ((ctx->flags & MICODMA_CTX_DMA_PAUSED)==0) && ctx->pHead)
  10.131 +        MicoDMA_Program(ctx->base, (DMADesc_t *)ctx->pHead);
  10.132 +
  10.133 +
  10.134 +    /* all done */
  10.135 +    return;
  10.136 +}
  10.137 +
  10.138 +
  10.139 +#ifdef __cplusplus
  10.140 +}
  10.141 +#endif
  10.142 +
  10.143 +
  10.144 +/* initialization routine */
  10.145 +void MicoDMAInit(MicoDMACtx_t *ctx)
  10.146 +{
  10.147 +    /* 
  10.148 +     * Unfortunately, we cannot "stop" the DMA if it was already
  10.149 +     * running..
  10.150 +     */
  10.151 +    volatile int i;
  10.152 +    volatile MicoDMA_t *dma = (volatile MicoDMA_t *)ctx->base;
  10.153 +
  10.154 +
  10.155 +    i = dma->status;
  10.156 +    dma->status = 0;
  10.157 +
  10.158 +
  10.159 +    /* set to "no flags" */
  10.160 +    ctx->flags = 0;
  10.161 +
  10.162 +
  10.163 +    /* compute max-length based on the length-register width */
  10.164 +    if(ctx->maxLength > 0){
  10.165 +        i = ctx->maxLength;
  10.166 +        ctx->maxLength = 1;
  10.167 +        do{
  10.168 +            ctx->maxLength += ctx->maxLength;
  10.169 +        }while(--i > 0);
  10.170 +        ctx->maxLength--;
  10.171 +    }
  10.172 +
  10.173 +
  10.174 +    /* initialize descriptor to null */
  10.175 +    ctx->pCurr = 0;
  10.176 +    ctx->pHead = 0;
  10.177 +
  10.178 +
  10.179 +    /* register ISR for this DMA */
  10.180 +    MicoRegisterISR(ctx->irq, (void *)ctx, MicoDMA_ISR);
  10.181 +
  10.182 +
  10.183 +    /* Register this DMA as an available device for the lookup service */
  10.184 +    ctx->lookupReg.name = ctx->name;
  10.185 +    ctx->lookupReg.deviceType = "DMADevice";
  10.186 +    ctx->lookupReg.priv = ctx;
  10.187 +    MicoRegisterDevice( &(ctx->lookupReg) );
  10.188 +
  10.189 +
  10.190 +    /* all done */
  10.191 +    return;
  10.192 +}
  10.193 +
  10.194 +
  10.195 +/* queue a new descriptor */
  10.196 +unsigned int MicoDMAQueueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, DMACallback_t callback)
  10.197 +{
  10.198 +    int byteLength;
  10.199 +    DMADesc_t *pPrevTail, *pHead;
  10.200 +
  10.201 +
  10.202 +    /* make sure descriptor and context are valid */
  10.203 +    if((ctx == 0) || (desc == 0))
  10.204 +        return(MICODMA_ERR_INVALID_POINTERS);
  10.205 +
  10.206 +
  10.207 +    /* convert read/write length into byte-length */
  10.208 +    byteLength = desc->length;
  10.209 +    if(desc->type & DMA_16BIT_TRANSFER){
  10.210 +        byteLength += byteLength;   /* left-shift by 1 to multiply by 2 for 16-bit transfer */
  10.211 +    } else if(desc->type & DMA_32BIT_TRANSFER) {
  10.212 +        byteLength += byteLength;   /* left-shift by 1 to multiply by 2         */
  10.213 +        byteLength += byteLength;   /* left-shift by 1 to multiply by 2, again  */
  10.214 +    }
  10.215 +
  10.216 +
  10.217 +
  10.218 +    /* make sure length of transaction is okay */
  10.219 +    if((byteLength > ctx->maxLength) || (byteLength == 0))
  10.220 +        return(MICODMA_ERR_DESC_LEN_ERR);
  10.221 +
  10.222 +
  10.223 +    /* save the new byte-length */
  10.224 +    desc->reserved = byteLength;
  10.225 +
  10.226 +
  10.227 +    /* prepare descriptor */
  10.228 +    desc->state = MICODMA_STATE_PENDING;
  10.229 +    desc->onCompletion = callback;
  10.230 +
  10.231 +
  10.232 +    /* disable this DMA's interrupt */
  10.233 +    MicoDisableInterrupt(ctx->irq);
  10.234 +
  10.235 +
  10.236 +    /* attach to this DMA's descriptor list */
  10.237 +    if(ctx->pHead == 0){
  10.238 +        ctx->pHead = (void *)desc;
  10.239 +        desc->next = desc;
  10.240 +        desc->prev = desc;
  10.241 +
  10.242 +        /* 
  10.243 +         * Since this is the first element in the list,
  10.244 +         * kick-off the DMA, if we're not paused
  10.245 +         */
  10.246 +        if((ctx->flags & MICODMA_CTX_DMA_PAUSED)==0)
  10.247 +            MicoDMA_Program(ctx->base, desc);
  10.248 +
  10.249 +    }else{
  10.250 +        pHead = (DMADesc_t *)(ctx->pHead);
  10.251 +        pPrevTail = pHead->prev;
  10.252 +
  10.253 +        pPrevTail->next = desc;
  10.254 +        pHead->prev = desc;
  10.255 +        desc->next = pHead;
  10.256 +        desc->prev = pPrevTail;
  10.257 +    }
  10.258 +
  10.259 +    /* reenable this DMA's interrupts */
  10.260 +    MicoEnableInterrupt(ctx->irq);
  10.261 +
  10.262 +    return(0);
  10.263 +}
  10.264 +
  10.265 +
  10.266 +/* dequeue an existing descriptor */
  10.267 +unsigned int MicoDMADequeueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, unsigned int callback)
  10.268 +{
  10.269 +    DMADesc_t *pHead, *pTail;
  10.270 +
  10.271 +    /* cannot dequeue a request if it is in a state other than pending */
  10.272 +    if((ctx == 0) || (desc == 0) || (desc->next == 0) || (desc->prev == 0))
  10.273 +        return(MICODMA_ERR_INVALID_POINTERS);
  10.274 +
  10.275 +
  10.276 +    /* disable interrupts */
  10.277 +    MicoDisableInterrupt(ctx->irq);
  10.278 +
  10.279 +    if(desc->state != MICODMA_STATE_PENDING){
  10.280 +
  10.281 +        /* cannot dequeue a request that isn't "pending" */
  10.282 +        MicoEnableInterrupt(ctx->irq);
  10.283 +        return(MICODMA_ERR_DESCRIPTOR_NOT_PENDING);
  10.284 +
  10.285 +    }else{
  10.286 +        /*
  10.287 +         *  mark this descriptor as non-pending and
  10.288 +         * remove it from the queue
  10.289 +         */
  10.290 +        desc->state = MICODMA_STATE_ABORTED;
  10.291 +        if(desc->next != desc){
  10.292 +            /* this isn't the only descriptor in the list */
  10.293 +            pHead = (DMADesc_t *)ctx->pHead;
  10.294 +            pTail = pHead->prev;
  10.295 +
  10.296 +            /* adjust pointers */
  10.297 +            desc->prev->next = desc->next;
  10.298 +            desc->next->prev = desc->prev;
  10.299 +
  10.300 +            /* if this was the head, readjust the head */
  10.301 +            if(pHead == desc)
  10.302 +                pHead = desc->next;
  10.303 +        }else{
  10.304 +            /* this was the only descriptor */
  10.305 +            ctx->pHead = 0;
  10.306 +        }
  10.307 +        desc->prev = 0;
  10.308 +        desc->next = 0;
  10.309 +
  10.310 +        /* call the callback with 'abort status' if requested */
  10.311 +        if(callback != 0){
  10.312 +            (desc->onCompletion)(desc, MICODMA_STATE_ABORTED);
  10.313 +        }
  10.314 +
  10.315 +        /* reenable interrupt */
  10.316 +        MicoEnableInterrupt(ctx->irq);
  10.317 +
  10.318 +        /* all done successfully */
  10.319 +        return(0);
  10.320 +    }
  10.321 +
  10.322 +}
  10.323 +
  10.324 +
  10.325 +/* query status of a descriptor */
  10.326 +unsigned int MicoDMAGetState(DMADesc_t *desc)
  10.327 +{
  10.328 +    return(desc->state);
  10.329 +}
  10.330 +
  10.331 +
  10.332 +/* pause DMA operations (after completion of the currently active descr.) */
  10.333 +unsigned int MicoDMAPause(MicoDMACtx_t *ctx)
  10.334 +{
  10.335 +    if(ctx == 0)
  10.336 +        return(MICODMA_ERR_INVALID_POINTERS);
  10.337 +
  10.338 +    /* disable interrupt for this DMA device */
  10.339 +    MicoDisableInterrupt(ctx->irq);
  10.340 +
  10.341 +    /* set the pause flag */
  10.342 +    ctx->flags |= MICODMA_CTX_DMA_PAUSED;
  10.343 +
  10.344 +    /* enable interrupts */
  10.345 +    MicoEnableInterrupt(ctx->irq);
  10.346 +
  10.347 +    return(0);
  10.348 +}
  10.349 +
  10.350 +
  10.351 +
  10.352 +/* resume DMA operations */
  10.353 +unsigned int MicoDMAResume(MicoDMACtx_t *ctx)
  10.354 +{
  10.355 +    if(ctx == 0)
  10.356 +        return(MICODMA_ERR_INVALID_POINTERS);
  10.357 +
  10.358 +    /* disable interrupt for the dma-device */
  10.359 +    MicoDisableInterrupt(ctx->irq);
  10.360 +
  10.361 +    if(ctx->flags & MICODMA_CTX_DMA_PAUSED){
  10.362 +        /* reset the pause-flag */
  10.363 +        ctx->flags &= ~(MICODMA_CTX_DMA_PAUSED);
  10.364 +
  10.365 +        /*
  10.366 +         * If there are descriptors queued up,
  10.367 +         * kick-start the dma process
  10.368 +         */
  10.369 +        if(ctx->pHead)
  10.370 +            MicoDMA_Program(ctx->base, (DMADesc_t *)ctx->pHead);
  10.371 +
  10.372 +    }
  10.373 +
  10.374 +    /* reenable interrupt for this dma device */
  10.375 +    MicoEnableInterrupt(ctx->irq);
  10.376 +
  10.377 +    return(0);
  10.378 +}
  10.379 +
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/drivers/device/MicoDMA.h	Fri Aug 13 10:43:05 2010 +0100
    11.3 @@ -0,0 +1,218 @@
    11.4 +/****************************************************************************
    11.5 +**
    11.6 +**  Name: MicoDMA.h
    11.7 +**
    11.8 +**  Description:
    11.9 +**        Declares prototypes of functions for manipulating LatticeMico32 DMA
   11.10 +**
   11.11 +**  Revision: 3.0
   11.12 +**
   11.13 +** Disclaimer:
   11.14 +**
   11.15 +**   This source code is intended as a design reference which
   11.16 +**   illustrates how these types of functions can be implemented.  It
   11.17 +**   is the user's responsibility to verify their design for
   11.18 +**   consistency and functionality through the use of formal
   11.19 +**   verification methods.  Lattice Semiconductor provides no warranty
   11.20 +**   regarding the use or functionality of this code.
   11.21 +**
   11.22 +** --------------------------------------------------------------------
   11.23 +**
   11.24 +**                     Lattice Semiconductor Corporation
   11.25 +**                     5555 NE Moore Court
   11.26 +**                     Hillsboro, OR 97214
   11.27 +**                     U.S.A
   11.28 +**
   11.29 +**                     TEL: 1-800-Lattice (USA and Canada)
   11.30 +**                          (503)268-8001 (other locations)
   11.31 +**
   11.32 +**                     web:   http://www.latticesemi.com
   11.33 +**                     email: techsupport@latticesemi.com
   11.34 +**
   11.35 +** --------------------------------------------------------------------------
   11.36 +**
   11.37 +**  Change History (Latest changes on top)
   11.38 +**
   11.39 +**  Ver    Date        Description
   11.40 +** --------------------------------------------------------------------------
   11.41 +**
   11.42 +**  3.0   Mar-25-2008  Added Header
   11.43 +**
   11.44 +**---------------------------------------------------------------------------
   11.45 +*****************************************************************************/
   11.46 +
   11.47 +#ifndef MICODMA_H_
   11.48 +#define MICODMA_H_
   11.49 +
   11.50 +#include "DDStructs.h"
   11.51 +
   11.52 +#ifdef __cplusplus
   11.53 +extern "C" {
   11.54 +#endif
   11.55 +
   11.56 +/***************************************************************
   11.57 + ***************************************************************
   11.58 + *                                                             *
   11.59 + *   DMA PHYSICAL DEVICE SPECIFIC INFORMATION                  *
   11.60 + *                                                             *
   11.61 + ***************************************************************
   11.62 + ***************************************************************/
   11.63 +
   11.64 +    /*
   11.65 +     ------------------------------------------------------
   11.66 +     - DMA registers specific bit definitions used        -
   11.67 +     - in the driver implementation                       -
   11.68 +     ------------------------------------------------------
   11.69 +     */
   11.70 +    /* CONTROL-REGISTER BIT-MASKS */
   11.71 +    #define MICODMA_CONTROL_SADDR_CONSTANT    (0x01)
   11.72 +    #define MICODMA_CONTROL_DADDR_CONSTANT    (0x02)
   11.73 +    #define MICODMA_CONTROL_USHORT_TRANSFER   (0x04)
   11.74 +    #define MICODMA_CONTROL_UINT_TRANSFER     (0x08)
   11.75 +    #define MICODMA_CONTROL_BURST_SIZE        (0x30)
   11.76 +    #define MICODMA_CONTROL_BURST_ENABLE      (0x40)
   11.77 +
   11.78 +    /* STATUS-REGISTER BIT-MASKS */
   11.79 +    #define MICODMA_STATUS_BUSY         (0x01)
   11.80 +    #define MICODMA_STATUS_IE           (0x02)
   11.81 +    #define MICODMA_STATUS_SUCCESS      (0x04)
   11.82 +    #define MICODMA_STATUS_START        (0x08)
   11.83 +
   11.84 +
   11.85 +    /* DMA OPERATIONAL CODES (USED INTERNALLY) */
   11.86 +    #define MICODMA_STATE_SUCCESS       (0x00)
   11.87 +    #define MICODMA_STATE_PENDING       (0x01)
   11.88 +    #define MICODMA_STATE_ACTIVE        (0x02)
   11.89 +    #define MICODMA_STATE_ERROR         (0x03)
   11.90 +    #define MICODMA_STATE_ABORTED       (0x04)
   11.91 +
   11.92 +
   11.93 +    /*
   11.94 +     ------------------------------------------------------
   11.95 +     -                                                    -
   11.96 +     - DMA  Device Register-map                           -
   11.97 +     -                                                    -
   11.98 +     ------------------------------------------------------
   11.99 +     */
  11.100 +    typedef struct st_MicoDMA{
  11.101 +        /* address to read data from */
  11.102 +        volatile unsigned int sAddr;
  11.103 +
  11.104 +        /* address to write data to */
  11.105 +        volatile unsigned int dAddr;
  11.106 +
  11.107 +        /* dma-length */
  11.108 +        volatile unsigned int len;
  11.109 +
  11.110 +        /* control register */
  11.111 +        volatile unsigned int control;
  11.112 +
  11.113 +        /* status register */
  11.114 +        volatile unsigned int status;
  11.115 +    }MicoDMA_t;
  11.116 +
  11.117 +
  11.118 +
  11.119 +/***************************************************************
  11.120 + ***************************************************************
  11.121 + *                                                             *
  11.122 + *  DMA  SOFTWARE DRIVER SPECIFIC INFORMATION                  *
  11.123 + *                                                             *
  11.124 + ***************************************************************
  11.125 + ***************************************************************/
  11.126 + 
  11.127 +    /* DMA-TYPE QUALIFIERS */
  11.128 +	/* DMA-type enumerator */
  11.129 +	typedef enum e_DMAType_t{
  11.130 +		DMA_CONSTANT_SRC_ADDR = 0x01,
  11.131 +		DMA_CONSTANT_DST_ADDR = 0x02,
  11.132 +		DMA_16BIT_TRANSFER    = 0x04,
  11.133 +		DMA_32BIT_TRANSFER    = 0x08,
  11.134 +                DMA_BURST_SIZE_4      = 0x40,
  11.135 +                DMA_BURST_SIZE_8      = 0x50,
  11.136 +                DMA_BURST_SIZE_16     = 0x60,
  11.137 +                DMA_BURST_SIZE_32     = 0x70,
  11.138 +                DMA_BURST_SIZE        = DMA_BURST_SIZE_8, /* Legacy: replaced by BURST_SIZE_X above */
  11.139 +                DMA_BURST_ENABLE      = 0x40              /* Legacy: replaced by BURST_SIZE_X above */
  11.140 +
  11.141 +        }DMAType_t;
  11.142 +
  11.143 + 
  11.144 +    typedef struct st_DMADesc_t DMADesc_t;
  11.145 +
  11.146 +    /* DMA Completion callback type */
  11.147 +    typedef void(*DMACallback_t)(DMADesc_t *desc, unsigned int status);
  11.148 +
  11.149 + 
  11.150 +    /* DMA Descriptor that defines a DMA operation */
  11.151 +    struct st_DMADesc_t{
  11.152 +        /* address to read data from */
  11.153 +        unsigned int sAddr;
  11.154 +
  11.155 +        /* address to write data to */
  11.156 +        unsigned int dAddr;
  11.157 +
  11.158 +        /* length of transfer */
  11.159 +        unsigned int length;
  11.160 +
  11.161 +        /* DMA transfer-qualifier */
  11.162 +        unsigned int type;
  11.163 +
  11.164 +        /* User-provided private data */
  11.165 +        void *priv;
  11.166 +
  11.167 +        /* descriptor state */
  11.168 +        unsigned int state;
  11.169 +
  11.170 +        /* used internally by the driver: Stores byte-length */
  11.171 +        unsigned int reserved;
  11.172 +
  11.173 +        /* used internally for chaining descriptors */
  11.174 +        DMACallback_t onCompletion;
  11.175 +        DMADesc_t *prev;
  11.176 +        DMADesc_t *next;
  11.177 +    };
  11.178 +
  11.179 +
  11.180 +
  11.181 +    /*
  11.182 +     ------------------------------------------------------
  11.183 +     -                                                    -
  11.184 +     - FUNCTIONS                                          -
  11.185 +     -                                                    -
  11.186 +     ------------------------------------------------------
  11.187 +     */
  11.188 +
  11.189 +
  11.190 +    /* well-known DMA specific return values */
  11.191 +    #define MICODMA_ERR_INVALID_POINTERS        (1)
  11.192 +    #define MICODMA_ERR_DESCRIPTOR_NOT_PENDING  (2)
  11.193 +    #define MICODMA_ERR_DESC_LEN_ERR            (3)
  11.194 +
  11.195 +
  11.196 +    /* initialization routine */
  11.197 +    void MicoDMAInit(MicoDMACtx_t *ctx);
  11.198 +
  11.199 +    /* queue a new descriptor */
  11.200 +    unsigned int MicoDMAQueueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, DMACallback_t callback);
  11.201 +
  11.202 +    /* dequeue an existing queued descriptor */
  11.203 +    unsigned int MicoDMADequeueRequest(MicoDMACtx_t *ctx, DMADesc_t *desc, unsigned int callback);
  11.204 +
  11.205 +    /* query status of a descriptor */
  11.206 +    unsigned int MicoDMAGetState(DMADesc_t *desc);
  11.207 +
  11.208 +    /* pause DMA operations (after completion of the currently active descr.) */
  11.209 +    unsigned int MicoDMAPause(MicoDMACtx_t *ctx);
  11.210 +
  11.211 +    /* resume DMA operations */
  11.212 +    unsigned int MicoDMAResume(MicoDMACtx_t *ctx);
  11.213 +
  11.214 +
  11.215 +#ifdef __cplusplus
  11.216 +}
  11.217 +#endif
  11.218 +
  11.219 +
  11.220 +#endif /*MICODMA_H_*/
  11.221 +
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/drivers/peripheral.mk	Fri Aug 13 10:43:05 2010 +0100
    12.3 @@ -0,0 +1,10 @@
    12.4 +#---------------------------------------------------------
    12.5 +# Identify source-paths for this device's driver-sources,
    12.6 +# compiled when building the library
    12.7 +#---------------------------------------------------------
    12.8 +LIBRARY_C_SRCS	+= MicoDMA.c	\
    12.9 +		MicoDMAService.c
   12.10 +LIBRARY_ASM_SRCS += 
   12.11 +
   12.12 +
   12.13 +
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/drivers/service/MicoDMAService.c	Fri Aug 13 10:43:05 2010 +0100
    13.3 @@ -0,0 +1,1 @@
    13.4 +/* NO IMPLEMENTATION, BY DESIGN */
\ No newline at end of file
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/drivers/service/MicoDMAService.h	Fri Aug 13 10:43:05 2010 +0100
    14.3 @@ -0,0 +1,17 @@
    14.4 +#ifndef MICO32_DMASERVICE_HEADER_FILE
    14.5 +#define MICO32_DMASERVICE_HEADER_FILE
    14.6 +
    14.7 +#ifdef __cplusplus
    14.8 +extern "C"
    14.9 +{
   14.10 +#endif /* __cplusplus */
   14.11 +
   14.12 +
   14.13 +
   14.14 +#ifdef __cplusplus
   14.15 +};
   14.16 +#endif /* __cplusplus */
   14.17 +
   14.18 +
   14.19 +#endif /* MICO32_DMASERVICE_HEADER_FILE */
   14.20 +
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/rtl/verilog/master_ctrl.v	Fri Aug 13 10:43:05 2010 +0100
    15.3 @@ -0,0 +1,1188 @@
    15.4 +// =============================================================================
    15.5 +//                           COPYRIGHT NOTICE
    15.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    15.7 +// ALL RIGHTS RESERVED
    15.8 +// This confidential and proprietary software may be used only as authorised by
    15.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   15.10 +// The entire notice above must be reproduced on all authorized copies and
   15.11 +// copies may only be made to the extent permitted by a licensing agreement from
   15.12 +// Lattice Semiconductor Corporation.
   15.13 +//
   15.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   15.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   15.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   15.17 +// U.S.A                                   email: techsupport@latticesemi.com
   15.18 +// =============================================================================/
   15.19 +//                         FILE DETAILS
   15.20 +// Project          : LM32 DMA Component
   15.21 +// File             : master_ctrl.v
   15.22 +// Title            : DMA Master controller 
   15.23 +// Dependencies     : None
   15.24 +//
   15.25 +// Version 3.1
   15.26 +//   1. Make DMA Engine compliant to Rule 3.100 of Wishbone Spec which defines 
   15.27 +//      alignement of bytes in sub-word transfers.
   15.28 +//   2. Removed glitch that did not pause the burst write when the read burst
   15.29 +//      was paused by the "read slave".
   15.30 +//
   15.31 +// Version 7.0SP2, 3.0
   15.32 +//   1. Read and Write channel of DMA controller are working in parallel,
   15.33 +//      due to that now as soon as FIFO is not empty write channel of the DMA
   15.34 +//      controller start writing data to the slave.
   15.35 +//   2. Burst Size supported by DMA controller is increased to support bigger
   15.36 +//      burst (from current value of 4 and 8 to 16 and 32). Now 4 different type
   15.37 +//      of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 
   15.38 +//      For this Burst Size field of the control register is increased to 2 bits.
   15.39 +//   3. Glitch is removed on the S_ACK_O signal. 
   15.40 +//
   15.41 +// Version 7.0
   15.42 +//   1. Initial Release
   15.43 +//
   15.44 +// =============================================================================
   15.45 +
   15.46 +`ifndef MASTER_CTRL_FILE
   15.47 + `define MASTER_CTRL_FILE
   15.48 + `include "system_conf.v"
   15.49 +module MASTER_CTRL 
   15.50 +  #(parameter LENGTH_WIDTH = 16,
   15.51 +    parameter FIFO_IMPLEMENTATION = "EBR")
   15.52 +    (
   15.53 +     //master read port
   15.54 +     MA_ADR_O,
   15.55 +     MA_SEL_O,
   15.56 +     MA_WE_O,
   15.57 +     MA_STB_O,
   15.58 +     MA_CYC_O,
   15.59 +     MA_CTI_O,
   15.60 +     MA_LOCK_O,
   15.61 +     MA_DAT_I,    //32bits
   15.62 +     MA_ACK_I,
   15.63 +     MA_ERR_I,
   15.64 +     MA_RTY_I,
   15.65 +     //master write port
   15.66 +     MB_ADR_O,
   15.67 +     MB_SEL_O,
   15.68 +     MB_DAT_O,    //32bits
   15.69 +     MB_WE_O,
   15.70 +     MB_STB_O,
   15.71 +     MB_CYC_O,
   15.72 +     MB_CTI_O,
   15.73 +     MB_LOCK_O,
   15.74 +     MB_ACK_I,
   15.75 +     MB_ERR_I,
   15.76 +     MB_RTY_I,
   15.77 +     //register interface
   15.78 +     M_SEL_O,
   15.79 +     reg_start,
   15.80 +     reg_status,
   15.81 +     reg_interrupt,
   15.82 +     reg_busy,
   15.83 +     data_length,
   15.84 +     reg_cntlg,
   15.85 +     reg_bt2,reg_bt1,reg_bt0,
   15.86 +     incr_unit,
   15.87 +     reg_s_con,
   15.88 +     reg_d_con,
   15.89 +     reg_00_data,
   15.90 +     reg_04_data,
   15.91 +     //system clock and reset
   15.92 +     CLK_I,
   15.93 +     RST_I
   15.94 +     );
   15.95 +   //master read port
   15.96 +   output [31:0] MA_ADR_O;
   15.97 +   output [3:0]  MA_SEL_O;
   15.98 +   output        MA_WE_O;
   15.99 +   output        MA_STB_O;
  15.100 +   output        MA_CYC_O;
  15.101 +   output [2:0]  MA_CTI_O;
  15.102 +   output        MA_LOCK_O;
  15.103 +   input [31:0]  MA_DAT_I;    //32bits
  15.104 +   input         MA_ACK_I;
  15.105 +   input         MA_ERR_I;
  15.106 +   input         MA_RTY_I;
  15.107 +   //master write port
  15.108 +   output [31:0] MB_ADR_O;
  15.109 +   output [3:0]  MB_SEL_O;
  15.110 +   output [31:0] MB_DAT_O;    //32bits
  15.111 +   output        MB_WE_O;
  15.112 +   output        MB_STB_O;
  15.113 +   output        MB_CYC_O;
  15.114 +   output [2:0]  MB_CTI_O;
  15.115 +   output        MB_LOCK_O;
  15.116 +   input         MB_ACK_I;
  15.117 +   input         MB_ERR_I;
  15.118 +   input         MB_RTY_I;
  15.119 +
  15.120 +   //register interface
  15.121 +   input [3:0] M_SEL_O;
  15.122 +   input                    reg_start;
  15.123 +   output                   reg_status;
  15.124 +   output                   reg_interrupt;
  15.125 +   output                   reg_busy;
  15.126 +   input [LENGTH_WIDTH-1:0] data_length;
  15.127 +   output                   reg_cntlg;
  15.128 +   input                    reg_bt2,reg_bt1,reg_bt0;
  15.129 +   input [2:0]              incr_unit;
  15.130 +   input                    reg_s_con;
  15.131 +   input                    reg_d_con;
  15.132 +   input [31:0]             reg_00_data;
  15.133 +   input [31:0]             reg_04_data;
  15.134 +   //system clock and reset
  15.135 +   input                    CLK_I;
  15.136 +   input                    RST_I;
  15.137 +
  15.138 +   parameter 		    lat_family   = `LATTICE_FAMILY;   
  15.139 +   parameter                UDLY         = 1;
  15.140 +   //Read FSM States encoding 
  15.141 +   parameter                ST_IDLE                 = 3'b000;
  15.142 +   parameter                ST_READ                 = 3'b001;
  15.143 +   parameter                ST_RDADDR               = 3'b010;
  15.144 +   parameter                ST_RDFIFO               = 3'b011;
  15.145 +   parameter                ST_WAIT_WRITE_FINISH    = 3'b100;
  15.146 +
  15.147 +   //Write FSM States encoding
  15.148 +   parameter                ST_WRITE_IDLE  = 4'b0000;
  15.149 +   parameter                ST_WRITE       = 4'b0001;
  15.150 +   parameter                ST_WRADDR      = 4'b0010;
  15.151 +   parameter                ST_CNTLNGTH    = 4'b0011;
  15.152 +   parameter                ST_JUSTICE     = 4'b0100;
  15.153 +   parameter                ST_FIFO_EMPTY  = 4'b0101;
  15.154 +   parameter                ST_WRITE_WAIT  = 4'b0110;
  15.155 +   parameter                ST_FIFO_AEMPTY = 4'b1010;
  15.156 +   parameter                ST_FIFO_RESUME = 4'b1000;
  15.157 +   
  15.158 +   // FSM for normal data transfer
  15.159 +   parameter                ST_IDLE1       = 3'b000;
  15.160 +   parameter                ST_READ1       = 3'b001;
  15.161 +   parameter                ST_WRITE1      = 3'b010;
  15.162 +   parameter                ST_RDADDR1     = 3'b011;
  15.163 +   parameter                ST_WRADDR1     = 3'b100;
  15.164 +   parameter                ST_CNTLNGTH1   = 3'b101;
  15.165 +   parameter                ST_JUSTICE1    = 3'b110;
  15.166 +   parameter                ST_RDFIFO1     = 3'b111;
  15.167 +   reg [2:0]                status;
  15.168 +   reg                      var_length;
  15.169 +
  15.170 +
  15.171 +   //fifo status
  15.172 +
  15.173 +   reg [2:0] 		    status1;
  15.174 +   reg [3:0] 		    status2;
  15.175 +   reg                      var_length2;
  15.176 +   reg                      var_length1;
  15.177 +   reg                      MA_STB_O;
  15.178 +   reg                      MB_STB_O;
  15.179 +   reg                      MA_CYC_O;
  15.180 +   reg                      MB_CYC_O;
  15.181 +   reg [2:0] 		    MA_CTI_O;
  15.182 +   reg [2:0] 		    MB_CTI_O;
  15.183 +   wire                     MA_WE_O      = 1'b0;
  15.184 +   wire                     MB_WE_O      = 1'b1;
  15.185 +   reg [31:0] 		    MA_ADR_O;
  15.186 +   reg [31:0] 		    MB_ADR_O;
  15.187 +   reg [3:0] 		    MA_SEL_O;
  15.188 +   reg [3:0] 		    MB_SEL_O;
  15.189 +   wire                     MA_LOCK_O   = 0; //reg_bt2 ? (status1 == ST_READ) && (!(MA_CTI_O == 3'h7)) : 1'b0;
  15.190 +   wire                     MB_LOCK_O   = 0; //reg_bt2 ? (status2 == ST_WRITE) && (!(MB_CTI_O == 3'h7)) : 1'b0;
  15.191 +
  15.192 +   wire                     reg_busy    = reg_bt2 ? !(status1 == ST_IDLE) : !(status == ST_IDLE1);
  15.193 +   wire                     reg_interrupt;
  15.194 +   wire                     reg_status;
  15.195 +
  15.196 +   wire 		    reg_cntlg;   
  15.197 +   reg                      start_flag;
  15.198 +   reg [5:0] 		    burst_size;
  15.199 +   reg [5:0] 		    burst_cnt;
  15.200 +   reg                      fifo_wr;
  15.201 +   reg                      fifo_rd;
  15.202 +   reg [31:0] 		    fifo_din;
  15.203 +   wire [31:0] 		    fifo_dout;
  15.204 +   wire                     fifo_empty;
  15.205 +   wire 		    fifo_aempty;
  15.206 +   reg                      fifo_clear;
  15.207 +   reg [31:0] 		    first_data;
  15.208 +   reg                      first_data_flag;
  15.209 +   wire [31:0] 		    MB_DAT_O =  first_data_flag ? first_data : fifo_dout;
  15.210 +   reg                      latch_start;
  15.211 +   
  15.212 +   reg                      reg_status1, reg_status2;
  15.213 +   reg                      reg_interrupt1, reg_interrupt2;
  15.214 +   reg                      end_of_transfer;
  15.215 +   reg                      burst_completed;
  15.216 +   reg                      donot_start_again;
  15.217 +   reg [5:0] 		    burst_size2;
  15.218 +   reg [5:0] 		    burst_cnt2; 
  15.219 +
  15.220 +   reg                      reg_cntlg_burst, reg_cntlg_normal;
  15.221 +   reg                      reg_status_normal, reg_interrupt_normal;
  15.222 +   reg                      direct_data;
  15.223 +
  15.224 +   always @(posedge CLK_I or posedge RST_I)
  15.225 +     if(RST_I)
  15.226 +       begin
  15.227 +          first_data                   <= #UDLY 'h0;
  15.228 +          first_data_flag              <= #UDLY 1'b0;
  15.229 +       end
  15.230 +     else if((start_flag || direct_data) & !reg_bt2 & MA_ACK_I)
  15.231 +       begin
  15.232 +          first_data                   <= #UDLY MA_DAT_I;
  15.233 +          first_data_flag              <= #UDLY 1'b1;
  15.234 +       end
  15.235 +     else if(first_data_flag & MB_ACK_I)
  15.236 +       begin
  15.237 +          first_data_flag              <= #UDLY 1'b0;
  15.238 +       end
  15.239 +
  15.240 +   assign reg_status = reg_bt2 ? (reg_status1 | reg_status2) : reg_status_normal;
  15.241 +   assign reg_interrupt = reg_bt2 ? (reg_interrupt1 | reg_interrupt2) : reg_interrupt_normal;
  15.242 +   assign reg_cntlg     = reg_bt2 ? reg_cntlg_burst : reg_cntlg_normal;  
  15.243 +
  15.244 +
  15.245 +   //FSM 
  15.246 +   always @(posedge CLK_I or posedge RST_I)
  15.247 +     if(RST_I) 
  15.248 +       begin
  15.249 +          status1                         <= #UDLY ST_IDLE;
  15.250 +          var_length1                     <= #UDLY 1'b0;
  15.251 +          MA_ADR_O                        <= #UDLY 32'h0;
  15.252 +          MA_SEL_O                        <= #UDLY 4'b1111;
  15.253 +          MA_CYC_O                        <= #UDLY 1'b0;
  15.254 +          MA_CTI_O                        <= #UDLY 3'h0;
  15.255 +          MA_STB_O                        <= #UDLY 1'b0;
  15.256 +          reg_status1                     <= #UDLY 1'b0;
  15.257 +          reg_interrupt1                  <= #UDLY 1'b0;
  15.258 +          start_flag                      <= #UDLY 1'b0;
  15.259 +          burst_size                      <= #UDLY 5'h0;
  15.260 +          burst_cnt                       <= #UDLY 5'h0;
  15.261 +          fifo_clear                      <= #UDLY 1'b0;
  15.262 +          latch_start                     <= #UDLY 1'b0;
  15.263 +	  fifo_wr                         <= #UDLY 1'b0;
  15.264 +
  15.265 +          status2                          <= #UDLY ST_WRITE_IDLE;
  15.266 +          MB_ADR_O                        <= #UDLY 32'h0;
  15.267 +          MB_SEL_O                        <= #UDLY 4'b1111;
  15.268 +          MB_CYC_O                        <= #UDLY 1'b0;
  15.269 +          MB_CTI_O                        <= #UDLY 3'h0; 
  15.270 +	  MB_STB_O                        <= #UDLY 1'b0;  
  15.271 +          reg_status2                     <= #UDLY 1'b0;
  15.272 +          reg_interrupt2                  <= #UDLY 1'b0;
  15.273 +          reg_cntlg_burst                 <= #UDLY 1'b0;
  15.274 +	  burst_size2                     <= #UDLY 5'h0;
  15.275 +          burst_cnt2                      <= #UDLY 5'h0;	  
  15.276 +          fifo_rd                         <= #UDLY 1'b0;
  15.277 +          end_of_transfer                 <= #UDLY 1'b0;
  15.278 +	  var_length2                     <= #UDLY 1'b0;
  15.279 +	  burst_completed                 <= #UDLY 1'b0;
  15.280 +	  donot_start_again               <= #UDLY 1'b0;
  15.281 +
  15.282 +          status                          <= #UDLY ST_IDLE1;
  15.283 +          var_length                      <= #UDLY 1'b0;
  15.284 +          reg_status_normal               <= #UDLY 1'b0;
  15.285 +          reg_interrupt_normal            <= #UDLY 1'b0;
  15.286 +          reg_cntlg_normal                <= #UDLY 1'b0;
  15.287 +          direct_data                     <= #UDLY 1'b0;	  
  15.288 +       end
  15.289 +     else 
  15.290 +       begin
  15.291 +	  if (reg_bt2) begin
  15.292 +	     // Read Burst
  15.293 +       	     if ((MB_RTY_I && (!(|data_length))) || (MB_ERR_I && (status2 == ST_WRITE)))
  15.294 +               begin		
  15.295 +		  status1           <= #UDLY ST_IDLE; 
  15.296 +	       end 
  15.297 +	     else
  15.298 +               begin
  15.299 +   		  case(status1)
  15.300 +		    ST_IDLE:
  15.301 +		      begin
  15.302 +			 if(fifo_wr)
  15.303 +			   fifo_wr <= #UDLY 1'b0;      	 
  15.304 +			 if(MA_ACK_I) 
  15.305 +			   begin	     
  15.306 +                              MA_CYC_O          <= #UDLY 1'b0;
  15.307 +                              MA_STB_O          <= #UDLY 1'b0;
  15.308 +                              MA_CTI_O          <= #UDLY 3'h0; 
  15.309 +			   end
  15.310 +			 if(reg_start | latch_start) 
  15.311 +			   begin
  15.312 +			      if(fifo_empty)
  15.313 +				begin
  15.314 +				   if(latch_start)
  15.315 +				     latch_start   <= #UDLY 1'b0;
  15.316 +				   status1       <= #UDLY ST_READ;
  15.317 +				   MA_CYC_O      <= #UDLY 1'b1;
  15.318 +				   MA_STB_O      <= #UDLY 1'b1;
  15.319 +				   MA_ADR_O      <= #UDLY reg_00_data;
  15.320 +				   case (reg_00_data[1:0])
  15.321 +				     2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
  15.322 +				     2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
  15.323 +				     2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
  15.324 +				     default:
  15.325 +				       MA_SEL_O <= #UDLY M_SEL_O;
  15.326 +				   endcase
  15.327 +				   set_cti_a;
  15.328 +				   start_flag    <= #UDLY 1'b1;
  15.329 +				   if(!(|data_length))
  15.330 +				     var_length1   <= #UDLY 1'b1;
  15.331 +				   else
  15.332 +				     var_length1   <= #UDLY 1'b0;
  15.333 +				   burst_size     <=  #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.334 +				   burst_cnt      <=  #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.335 +				end
  15.336 +			      else
  15.337 +				status1            <= #UDLY ST_RDFIFO;
  15.338 +			   end 
  15.339 +			 else 
  15.340 +			   status1                 <= #UDLY ST_IDLE;	     
  15.341 +			 reg_interrupt1          <= #UDLY 1'b0;
  15.342 +		      end
  15.343 +
  15.344 +		    ST_WAIT_WRITE_FINISH:
  15.345 +		      begin 	    
  15.346 +			 fifo_wr <= #UDLY 1'b0;	
  15.347 +			 if (status2 == ST_WRITE)
  15.348 +			   start_flag  <= #UDLY 1'b0;      
  15.349 +			 if(end_of_transfer)
  15.350 +			   begin 
  15.351 +			      if(!reg_s_con)
  15.352 +				MA_ADR_O   <= #UDLY MA_ADR_O + incr_unit;
  15.353 +			      if (incr_unit == 3'b001)
  15.354 +				MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
  15.355 +			      else
  15.356 +				if (incr_unit == 3'b010)
  15.357 +				  MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
  15.358 +			      
  15.359 +			      status1    <= #UDLY ST_RDADDR;
  15.360 +			      burst_cnt  <= #UDLY burst_size;
  15.361 +			   end
  15.362 +			 else
  15.363 +			   begin
  15.364 +			      if(burst_completed)
  15.365 +				status1     <= #UDLY ST_IDLE;		      
  15.366 +			   end			  
  15.367 +		      end
  15.368 +
  15.369 +		    ST_RDFIFO:
  15.370 +		      begin
  15.371 +			 if(fifo_empty)
  15.372 +			   begin
  15.373 +			      status1            <= #UDLY ST_IDLE;
  15.374 +			      fifo_clear         <= #UDLY 1'b0;
  15.375 +			      latch_start        <= #UDLY 1'b1;
  15.376 +			   end
  15.377 +			 else
  15.378 +			   fifo_clear            <= #UDLY !fifo_clear;
  15.379 +		      end
  15.380 +
  15.381 +		    ST_RDADDR:
  15.382 +		      begin
  15.383 +			 MA_CYC_O                <= #UDLY 1'b1;
  15.384 +			 MA_STB_O                <= #UDLY 1'b1;
  15.385 +			 set_cti_a;
  15.386 +			 status1                 <= #UDLY ST_READ;
  15.387 +		      end
  15.388 +
  15.389 +		    ST_READ:
  15.390 +		      begin
  15.391 +			 write_fifo;
  15.392 +			 if(MA_ACK_I) 
  15.393 +			   begin
  15.394 +			      if(start_flag) 
  15.395 +				begin
  15.396 +				   if(burst_cnt == 0)
  15.397 +				     begin
  15.398 +					MA_CYC_O      <= #UDLY 1'b0;
  15.399 +					MA_STB_O      <= #UDLY 1'b0;
  15.400 +					MA_CTI_O      <= #UDLY 3'h0;
  15.401 +					status1       <= #UDLY ST_WAIT_WRITE_FINISH;
  15.402 +				     end
  15.403 +				   else
  15.404 +				     begin
  15.405 +					if(burst_cnt == 1)
  15.406 +					  MA_CTI_O   <= #UDLY 3'h7;
  15.407 +					burst_cnt  <= #UDLY burst_cnt - 1;
  15.408 +					if(!reg_s_con)
  15.409 +					  MA_ADR_O   <= #UDLY MA_ADR_O + incr_unit;
  15.410 +					if (incr_unit == 3'b001)
  15.411 +					  MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
  15.412 +					else
  15.413 +					  if (incr_unit == 3'b010)
  15.414 +					    MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
  15.415 +				     end
  15.416 +				end 
  15.417 +			      else 
  15.418 +				begin
  15.419 +				   if(burst_cnt == 0)
  15.420 +				     begin
  15.421 +					MA_CYC_O      <= #UDLY 1'b0;
  15.422 +					MA_STB_O      <= #UDLY 1'b0;
  15.423 +					MA_CTI_O      <= #UDLY 3'h0;
  15.424 +					status1       <= #UDLY ST_WAIT_WRITE_FINISH;
  15.425 +				     end
  15.426 +				   else
  15.427 +				     begin
  15.428 +					if(burst_cnt == 1)
  15.429 +					  MA_CTI_O   <= #UDLY 3'h7;
  15.430 +					if(!reg_s_con)
  15.431 +					  MA_ADR_O   <= #UDLY MA_ADR_O + incr_unit;
  15.432 +					if (incr_unit == 3'b001)
  15.433 +					  MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
  15.434 +					else
  15.435 +					  if (incr_unit == 3'b010)
  15.436 +					    MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
  15.437 +					burst_cnt  <= #UDLY burst_cnt - 1;
  15.438 +				     end
  15.439 +				end
  15.440 +			   end
  15.441 +			 else if(MA_RTY_I) 
  15.442 +			   begin
  15.443 +			      if(var_length1) 
  15.444 +				begin
  15.445 +				   MA_CYC_O         <= #UDLY 1'b0;
  15.446 +				   MA_STB_O         <= #UDLY 1'b0;
  15.447 +				   MA_CTI_O         <= #UDLY 3'h0;
  15.448 +				   status1          <= #UDLY ST_IDLE;
  15.449 +				   reg_status1      <= #UDLY 1'b0;
  15.450 +				   reg_interrupt1   <= #UDLY 1'b1;
  15.451 +				   start_flag       <= #UDLY 1'b0;
  15.452 +				end
  15.453 +			   end 
  15.454 +			 else if(MA_ERR_I) 
  15.455 +			   begin
  15.456 +			      MA_CYC_O              <= #UDLY 1'b0;
  15.457 +			      MA_STB_O              <= #UDLY 1'b0;
  15.458 +			      MA_CTI_O              <= #UDLY 3'h0;
  15.459 +			      status1               <= #UDLY ST_IDLE;
  15.460 +			      reg_status1           <= #UDLY 1'b1;
  15.461 +			      reg_interrupt1        <= #UDLY 1'b1;
  15.462 +			      start_flag            <= #UDLY 1'b0;
  15.463 +			   end
  15.464 +		      end
  15.465 +
  15.466 +		    default:
  15.467 +		      begin
  15.468 +			 status1                     <= #UDLY ST_IDLE;
  15.469 +			 var_length1                 <= #UDLY 1'b0;
  15.470 +			 MA_ADR_O                    <= #UDLY 32'h0;
  15.471 +			 MA_SEL_O                    <= #UDLY 4'b1111;
  15.472 +			 MA_CYC_O                    <= #UDLY 1'b0;
  15.473 +			 MA_CTI_O                    <= #UDLY 3'h0;
  15.474 +			 MA_STB_O                    <= #UDLY 1'b0;
  15.475 +			 reg_status1                 <= #UDLY 1'b0;
  15.476 +			 reg_interrupt1              <= #UDLY 1'b0;
  15.477 +			 start_flag                  <= #UDLY 1'b0;
  15.478 +			 burst_size                  <= #UDLY 5'h0;
  15.479 +			 burst_cnt                   <= #UDLY 5'h0;
  15.480 +			 fifo_clear                  <= #UDLY 1'b0;
  15.481 +			 latch_start                 <= #UDLY 1'b0;
  15.482 +			 fifo_wr                     <= #UDLY 1'b0; 
  15.483 +		      end
  15.484 +		  endcase
  15.485 +               end
  15.486 +             // Write Burst
  15.487 +	     if ((MA_RTY_I && (!(|data_length))) || (MA_ERR_I && (status1 == ST_READ)))
  15.488 +	       begin
  15.489 +		  status2           <= #UDLY ST_WRITE_IDLE;
  15.490 +		  donot_start_again <= #UDLY 1'b1;	   
  15.491 +               end  
  15.492 +	     else
  15.493 +               begin 		 
  15.494 +		  case(status2)
  15.495 +		    ST_WRITE_IDLE: 
  15.496 +		      begin 	     		   
  15.497 +			 if(reg_start)
  15.498 +			   begin
  15.499 +	                      MB_ADR_O         <= #UDLY reg_04_data;
  15.500 +			      case (reg_04_data[1:0])
  15.501 +				2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
  15.502 +				2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
  15.503 +				2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
  15.504 +				default:
  15.505 +				  MB_SEL_O     <= #UDLY M_SEL_O;
  15.506 +			      endcase
  15.507 +                              if(!(|data_length))
  15.508 +				var_length2    <= #UDLY 1'b1;
  15.509 +                              else
  15.510 +				var_length2    <= #UDLY 1'b0;
  15.511 +                              burst_size2    <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.512 +                              burst_cnt2     <= #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.513 +                              if(!fifo_empty)
  15.514 +				status2        <= #UDLY ST_FIFO_EMPTY;
  15.515 +	                      else
  15.516 +				donot_start_again <= #UDLY 1'b0;		 
  15.517 +			   end
  15.518 +			 if(fifo_empty)
  15.519 +			   begin
  15.520 +			      if(MB_ACK_I) 
  15.521 +				begin	     
  15.522 +				   MB_CYC_O          <= #UDLY 1'b0;
  15.523 +				   MB_STB_O          <= #UDLY 1'b0;
  15.524 +				   MB_CTI_O          <= #UDLY 3'h0;
  15.525 +				   fifo_rd           <= #UDLY 1'b0;  
  15.526 +				end
  15.527 +			      burst_cnt2        <= #UDLY 5'h0; 		       
  15.528 +			   end
  15.529 +			 else
  15.530 +			   begin
  15.531 +			      if(donot_start_again)
  15.532 +				begin
  15.533 +				   if(MB_ACK_I)
  15.534 +				     begin     	 
  15.535 +					if(!reg_d_con)
  15.536 +					  MB_ADR_O   <= #UDLY MB_ADR_O + incr_unit;
  15.537 +					if (incr_unit == 3'b001)
  15.538 +					  MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.539 +					else
  15.540 +					  if (incr_unit == 3'b010)
  15.541 +					    MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.542 +				     end
  15.543 +				end
  15.544 +			   end
  15.545 +			 
  15.546 +			 if(!fifo_empty && !donot_start_again)
  15.547 +			   begin
  15.548 +			      if(start_flag)
  15.549 +				begin
  15.550 +				   set_cti_b;
  15.551 +				   status2        <= #UDLY ST_WRITE_WAIT;
  15.552 +				   read_fifo;
  15.553 +				   burst_cnt2     <=  #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.554 +				end
  15.555 +			      else
  15.556 +				begin
  15.557 +				   if(!reg_d_con)
  15.558 +				     MB_ADR_O   <= #UDLY MB_ADR_O + incr_unit;
  15.559 +				   if (incr_unit == 3'b001)
  15.560 +				     MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.561 +				   else
  15.562 +				     if (incr_unit == 3'b010)
  15.563 +				       MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.564 +				   status2        <= #UDLY ST_WRADDR;
  15.565 +				   read_fifo;
  15.566 +				   burst_cnt2     <=  #UDLY reg_bt1 ? (reg_bt0 ? 5'h1f : 5'hf) : (reg_bt0 ? 5'h7 : 5'h3);
  15.567 +				end
  15.568 +			   end		      
  15.569 +			 end_of_transfer <= #UDLY 1'b0;
  15.570 +			 burst_completed <= #UDLY 1'b0;
  15.571 +			 reg_interrupt2  <= #UDLY 1'b0; 
  15.572 +		      end
  15.573 +		    
  15.574 +  		    ST_FIFO_EMPTY:
  15.575 +		      begin
  15.576 +			 if(fifo_empty)
  15.577 +			   begin		 
  15.578 +			      status2           <= #UDLY ST_WRITE_IDLE;
  15.579 +			      donot_start_again <= #UDLY 1'b0;
  15.580 +			   end   
  15.581 +		      end
  15.582 +		    
  15.583 +		    ST_WRADDR:
  15.584 +		      begin
  15.585 +			 burst_cnt2 <= #UDLY burst_size2;
  15.586 +			 MB_CYC_O   <= #UDLY 1'b1;
  15.587 +			 MB_STB_O   <= #UDLY 1'b1;
  15.588 +			 
  15.589 +			 if (fifo_aempty && (burst_size2 > 5'h2))
  15.590 +			   begin
  15.591 +			      MB_CTI_O   <= #UDLY 3'b000;
  15.592 +			      status2    <= #UDLY ST_FIFO_AEMPTY;
  15.593 +			      fifo_rd    <= #UDLY 1'b0;
  15.594 +			   end
  15.595 +			 else
  15.596 +			   begin
  15.597 +			      set_cti_b;
  15.598 +			      status2    <= #UDLY ST_WRITE;
  15.599 +			   end
  15.600 +		      end
  15.601 +		    
  15.602 +		    ST_WRITE_WAIT:
  15.603 +		      begin
  15.604 +			 MB_CYC_O   <= #UDLY 1'b1;
  15.605 +			 MB_STB_O   <= #UDLY 1'b1;
  15.606 +			 
  15.607 +			 if (fifo_aempty && (burst_size2 > 5'h2))
  15.608 +			   begin
  15.609 +			      MB_CTI_O   <= #UDLY 3'b000;
  15.610 +			      status2    <= #UDLY ST_FIFO_AEMPTY;
  15.611 +			      fifo_rd    <= #UDLY 1'b0;
  15.612 +			   end
  15.613 +			 else
  15.614 +			   begin
  15.615 +			      set_cti_b;
  15.616 +			      status2    <= #UDLY ST_WRITE;
  15.617 +			   end
  15.618 +		      end
  15.619 +		    
  15.620 +		    ST_FIFO_AEMPTY:
  15.621 +		      begin
  15.622 +			 if (MB_ACK_I)
  15.623 +			   begin
  15.624 +			      MB_CYC_O     <= #UDLY 1'b0;
  15.625 +			      MB_STB_O     <= #UDLY 1'b0;
  15.626 +			      
  15.627 +			      burst_cnt2 <= #UDLY burst_cnt2 - 1;
  15.628 +			      
  15.629 +			      if (!reg_d_con)
  15.630 +				MB_ADR_O   <= #UDLY MB_ADR_O + incr_unit;
  15.631 +			      
  15.632 +			      if (incr_unit == 3'b001)
  15.633 +				MB_SEL_O   <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.634 +			      else
  15.635 +				if (incr_unit == 3'b010)
  15.636 +				  MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.637 +			   end
  15.638 +			 
  15.639 +			 if (!MB_CYC_O && !fifo_aempty)
  15.640 +			   begin
  15.641 +			      status2    <= #UDLY ST_FIFO_RESUME;
  15.642 +			      read_fifo;
  15.643 +			   end
  15.644 +		      end
  15.645 +		    
  15.646 +		    ST_FIFO_RESUME:
  15.647 +		      begin
  15.648 +			 MB_CYC_O   <= #UDLY 1'b1;
  15.649 +			 MB_STB_O   <= #UDLY 1'b1;
  15.650 +			 
  15.651 +			 if (fifo_aempty && (burst_cnt2 > 5'h2))
  15.652 +			   begin
  15.653 +			      MB_CTI_O   <= #UDLY 3'b000;
  15.654 +			      status2    <= #UDLY ST_FIFO_AEMPTY;
  15.655 +			      fifo_rd    <= #UDLY 1'b0;
  15.656 +			   end
  15.657 +			 else
  15.658 +			   begin
  15.659 +			      set_cti_b;
  15.660 +			      status2    <= #UDLY ST_WRITE;
  15.661 +			   end
  15.662 +		      end
  15.663 +		    
  15.664 +		    ST_WRITE:
  15.665 +		      begin
  15.666 +			 if (MB_ACK_I)
  15.667 +			   begin
  15.668 +			      if(var_length2) 
  15.669 +				begin
  15.670 +				   if(burst_cnt2 == 0)
  15.671 +				     begin
  15.672 +					MB_CYC_O        <= #UDLY 1'b0;
  15.673 +					MB_STB_O        <= #UDLY 1'b0;
  15.674 +					MB_CTI_O        <= #UDLY 3'h0;
  15.675 +					end_of_transfer <= #UDLY 1'b1;  
  15.676 +					status2         <= #UDLY ST_WRITE_IDLE; 
  15.677 +					fifo_rd         <= #UDLY 1'b0;
  15.678 +					burst_cnt2      <= #UDLY burst_size2;
  15.679 +				     end
  15.680 +				   else
  15.681 +				     begin
  15.682 +					if(burst_cnt2 == 1)
  15.683 +					  MB_CTI_O   <= #UDLY 3'h7;
  15.684 +					else
  15.685 +					  set_cti_b;
  15.686 +					if(!reg_d_con)
  15.687 +					  MB_ADR_O   <= #UDLY MB_ADR_O + incr_unit;
  15.688 +					if (incr_unit == 3'b001)
  15.689 +					  MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.690 +					else
  15.691 +					  if (incr_unit == 3'b010)
  15.692 +					    MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.693 +					read_fifo;
  15.694 +					burst_cnt2 <= #UDLY burst_cnt2 - 1;
  15.695 +				     end
  15.696 +				end 
  15.697 +			      else 
  15.698 +				begin
  15.699 +				   if(burst_cnt2 == 0)
  15.700 +				     begin
  15.701 +					MB_CYC_O      <= #UDLY 1'b0;
  15.702 +					MB_STB_O      <= #UDLY 1'b0;
  15.703 +					MB_CTI_O      <= #UDLY 3'h0;
  15.704 +					reg_cntlg_burst     <= #UDLY 1'b1;
  15.705 +					status2       <= #UDLY ST_CNTLNGTH;
  15.706 +					fifo_rd       <= #UDLY 1'b0;
  15.707 +					burst_cnt2    <= #UDLY burst_size2;
  15.708 +				     end
  15.709 +				   else
  15.710 + 				     begin
  15.711 +					if ((fifo_aempty && (burst_cnt2 > 5'h2)) || (burst_cnt2 == 5'h1))
  15.712 +					  MB_CTI_O    <= #UDLY 3'h7;
  15.713 +					else
  15.714 +					  set_cti_b;
  15.715 +					
  15.716 +					burst_cnt2    <= #UDLY burst_cnt2 - 1;
  15.717 +					
  15.718 +					if(!reg_d_con)
  15.719 +					  MB_ADR_O    <= #UDLY MB_ADR_O + incr_unit;
  15.720 +					
  15.721 +					if (incr_unit == 3'b001)
  15.722 +					  MB_SEL_O    <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.723 +					else
  15.724 +					  if (incr_unit == 3'b010)
  15.725 +					    MB_SEL_O  <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.726 +					
  15.727 +					if (fifo_aempty && (burst_cnt2 > 5'h2))
  15.728 +					  begin
  15.729 +					     status2     <= #UDLY ST_FIFO_AEMPTY;
  15.730 +					     fifo_rd     <= 1'b0;
  15.731 +					  end
  15.732 +					else
  15.733 +					  read_fifo;
  15.734 +				     end
  15.735 +				end
  15.736 +			   end
  15.737 +			 
  15.738 +			 else if(MB_RTY_I) 
  15.739 +			   begin
  15.740 +			      if(var_length2) 
  15.741 +				begin
  15.742 +				   MB_CYC_O          <= #UDLY 1'b0;
  15.743 +				   MB_STB_O          <= #UDLY 1'b0;
  15.744 +				   MB_CTI_O          <= #UDLY 3'h0;
  15.745 +				   status2           <= #UDLY ST_WRITE_IDLE;
  15.746 +				   reg_status2       <= #UDLY 1'b0;
  15.747 +				   reg_interrupt2    <= #UDLY 1'b1;
  15.748 +				   var_length2       <= #UDLY 1'b0;
  15.749 +				   donot_start_again <= #UDLY 1'b1;
  15.750 +				   fifo_rd           <= #UDLY 1'b0;
  15.751 +				end
  15.752 +			   end // if (MB_RTY_I)
  15.753 +			 
  15.754 +			 else if(MB_ERR_I) 
  15.755 +			   begin
  15.756 +			      MB_CYC_O             <= #UDLY 1'b0;
  15.757 +			      MB_STB_O             <= #UDLY 1'b0;
  15.758 +			      MB_CTI_O             <= #UDLY 3'h0;
  15.759 +			      status2              <= #UDLY ST_WRITE_IDLE;
  15.760 +			      reg_status2          <= #UDLY 1'b1;
  15.761 +			      reg_interrupt2       <= #UDLY 1'b1;
  15.762 +			      donot_start_again    <= #UDLY 1'b1;
  15.763 +			      fifo_rd              <= #UDLY 1'b0;
  15.764 +			   end // if (MB_ERR_I)
  15.765 +			 
  15.766 +		      end
  15.767 +
  15.768 +		    ST_CNTLNGTH:
  15.769 +		      begin
  15.770 +			 reg_cntlg_burst        <= #UDLY 1'b0;
  15.771 +			 status2                <= #UDLY ST_JUSTICE;
  15.772 +		      end
  15.773 +
  15.774 +		    ST_JUSTICE:
  15.775 +		      begin
  15.776 +			 if(!(|data_length)) 
  15.777 +			   begin
  15.778 +			      status2              <= #UDLY ST_WRITE_IDLE;
  15.779 +			      reg_status2          <= #UDLY 1'b0;
  15.780 +			      reg_interrupt2       <= #UDLY 1'b1;
  15.781 +			      burst_completed      <= #UDLY 1'b1;
  15.782 +			   end 
  15.783 +			 else 
  15.784 +			   begin
  15.785 +			      end_of_transfer <= #UDLY 1'b1;
  15.786 +			      status2         <= ST_WRITE_IDLE;
  15.787 +			   end
  15.788 +		      end
  15.789 +		    
  15.790 +		    default:
  15.791 +		      begin
  15.792 +			 status2                <= #UDLY ST_WRITE_IDLE;
  15.793 +			 MB_ADR_O               <= #UDLY 32'h0;
  15.794 +			 MB_SEL_O               <= #UDLY 4'b1111;
  15.795 +			 MB_CYC_O               <= #UDLY 1'b0;
  15.796 +			 MB_CTI_O               <= #UDLY 3'h0;
  15.797 +			 MB_STB_O               <= #UDLY 1'b0;
  15.798 +			 reg_status2            <= #UDLY 1'b0;
  15.799 +			 reg_interrupt2         <= #UDLY 1'b0;
  15.800 +			 reg_cntlg_burst        <= #UDLY 1'b0;
  15.801 +			 burst_size2            <= #UDLY 5'h0;
  15.802 +			 burst_cnt2             <= #UDLY 5'h0;
  15.803 +			 fifo_rd                <= #UDLY 1'b0;
  15.804 +			 end_of_transfer        <= #UDLY 1'b0; 
  15.805 +			 var_length2            <= #UDLY 1'b0; 
  15.806 +			 burst_completed        <= #UDLY 1'b0; 
  15.807 +			 donot_start_again      <= #UDLY 1'b0;	 
  15.808 +		      end
  15.809 +		  endcase
  15.810 +               end
  15.811 +	  end
  15.812 +	  else begin
  15.813 +             // Read/Write Normal
  15.814 +	     case(status)
  15.815 +
  15.816 +               ST_IDLE1:
  15.817 +		 begin
  15.818 +                    if(reg_start | latch_start) 
  15.819 +                      begin
  15.820 +			 if(fifo_empty)
  15.821 +                           begin
  15.822 +                              if(latch_start)
  15.823 +				latch_start   <= #UDLY 1'b0;
  15.824 +                              status           <= #UDLY ST_READ1;
  15.825 +                              MA_CYC_O         <= #UDLY 1'b1;
  15.826 +                              MA_STB_O         <= #UDLY 1'b1;
  15.827 +                              MA_ADR_O         <= #UDLY reg_00_data;
  15.828 +			      case (reg_00_data[1:0])
  15.829 +				2'b01: MA_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
  15.830 +				2'b10: MA_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
  15.831 +				2'b11: MA_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
  15.832 +				default:
  15.833 +				  MA_SEL_O <= #UDLY M_SEL_O;
  15.834 +			      endcase
  15.835 +                              MB_ADR_O         <= #UDLY reg_04_data;
  15.836 +			      case (reg_04_data[1:0])
  15.837 +				2'b01: MB_SEL_O <= #UDLY {1'b0,M_SEL_O[3:1]};
  15.838 +				2'b10: MB_SEL_O <= #UDLY {2'b00,M_SEL_O[3:2]};
  15.839 +				2'b11: MB_SEL_O <= #UDLY {3'b00,M_SEL_O[3:3]};
  15.840 +				default:
  15.841 +				  MB_SEL_O     <= #UDLY M_SEL_O;
  15.842 +			      endcase
  15.843 +                              set_cti_a;
  15.844 +                              start_flag       <= #UDLY 1'b1;
  15.845 +                              if(!(|data_length))
  15.846 +				var_length    <= #UDLY 1'b1;
  15.847 +                              else
  15.848 +				var_length    <= #UDLY 1'b0;
  15.849 +                              burst_size       <= #UDLY 5'h0;
  15.850 +                              burst_cnt        <= #UDLY 5'h0;
  15.851 +                           end
  15.852 +			 else
  15.853 +                           begin
  15.854 +                              status           <= #UDLY ST_RDFIFO1;
  15.855 +                           end
  15.856 +                      end 
  15.857 +                    else 
  15.858 +                      begin
  15.859 +			 status              <= #UDLY ST_IDLE1;
  15.860 +                      end
  15.861 +                    reg_interrupt_normal     <= #UDLY 1'b0;
  15.862 +		 end
  15.863 +               ST_RDFIFO1:
  15.864 +		 begin
  15.865 +                    if(fifo_empty)
  15.866 +                      begin
  15.867 +			 status             <= #UDLY ST_IDLE1;
  15.868 +			 fifo_clear         <= #UDLY 1'b0;
  15.869 +			 latch_start        <= #UDLY 1'b1;
  15.870 +                      end
  15.871 +                    else
  15.872 +                      fifo_clear         <= #UDLY !fifo_clear;
  15.873 +		 end
  15.874 +
  15.875 +               ST_RDADDR1:
  15.876 +		 begin
  15.877 +                    MA_CYC_O               <= #UDLY 1'b1;
  15.878 +                    MA_STB_O               <= #UDLY 1'b1;
  15.879 +                    set_cti_a;
  15.880 +                    status                 <= #UDLY ST_READ1;
  15.881 +		    direct_data            <= #UDLY 1'b1;
  15.882 +		 end
  15.883 +
  15.884 +               ST_READ1:
  15.885 +		 begin
  15.886 +                    if(!start_flag)
  15.887 +                      write_fifo;
  15.888 +                    if(MA_ACK_I) 
  15.889 +                      begin
  15.890 +			 if(start_flag) 
  15.891 +                           begin
  15.892 +                              MA_CYC_O      <= #UDLY 1'b0;
  15.893 +                              MA_STB_O      <= #UDLY 1'b0;
  15.894 +                              MA_CTI_O      <= #UDLY 3'h0;
  15.895 +                              MB_CYC_O      <= #UDLY 1'b1;
  15.896 +                              MB_STB_O      <= #UDLY 1'b1;
  15.897 +                              set_cti_b;
  15.898 +                              status        <= #UDLY ST_WRITE1;
  15.899 +                              start_flag    <= #UDLY 1'b0;
  15.900 +                              burst_cnt     <= #UDLY burst_size;
  15.901 +                           end 
  15.902 +			 else 
  15.903 +                           begin
  15.904 +                              MA_CYC_O      <= #UDLY 1'b0;
  15.905 +                              MA_STB_O      <= #UDLY 1'b0;
  15.906 +                              MA_CTI_O      <= #UDLY 3'h0;
  15.907 +                              if(!reg_d_con)
  15.908 +				begin
  15.909 +                                   MB_ADR_O   <= #UDLY MB_ADR_O + incr_unit;
  15.910 +				   if (incr_unit == 3'b001)
  15.911 +				     MB_SEL_O <= #UDLY {MB_SEL_O[0], MB_SEL_O[3:1]};
  15.912 +				   else
  15.913 +				     if (incr_unit == 3'b010)
  15.914 +				       MB_SEL_O <= #UDLY {MB_SEL_O[1:0], MB_SEL_O[3:2]};
  15.915 +				end
  15.916 +                              status        <= #UDLY ST_WRADDR1;
  15.917 +                              burst_cnt     <= #UDLY burst_size;
  15.918 +                           end
  15.919 +                      end
  15.920 +                    else if(MA_RTY_I) 
  15.921 +                      begin
  15.922 +			 if(var_length) 
  15.923 +                           begin
  15.924 +                              MA_CYC_O         <= #UDLY 1'b0;
  15.925 +                              MA_STB_O         <= #UDLY 1'b0;
  15.926 +                              MA_CTI_O         <= #UDLY 3'h0;
  15.927 +                              status           <= #UDLY ST_IDLE1;
  15.928 +                              reg_status_normal       <= #UDLY 1'b0;
  15.929 +                              reg_interrupt_normal    <= #UDLY 1'b1;
  15.930 +                           end
  15.931 +                      end 
  15.932 +                    else if(MA_ERR_I) 
  15.933 +                      begin
  15.934 +			 MA_CYC_O            <= #UDLY 1'b0;
  15.935 +			 MA_STB_O            <= #UDLY 1'b0;
  15.936 +			 MA_CTI_O            <= #UDLY 3'h0;
  15.937 +			 status              <= #UDLY ST_IDLE1;
  15.938 +			 reg_status_normal          <= #UDLY 1'b1;
  15.939 +			 reg_interrupt_normal       <= #UDLY 1'b1;
  15.940 +                      end
  15.941 +		 end
  15.942 +
  15.943 +               ST_WRADDR1:
  15.944 +		 begin
  15.945 +                    fifo_wr                <= #UDLY 1'b0;
  15.946 +                    MB_CYC_O               <= #UDLY 1'b1;
  15.947 +                    MB_STB_O               <= #UDLY 1'b1;
  15.948 +                    burst_cnt              <= #UDLY burst_size;
  15.949 +                    set_cti_b;
  15.950 +                    status                 <= #UDLY ST_WRITE1;
  15.951 +                    read_fifo;
  15.952 +		 end
  15.953 +
  15.954 +               ST_WRITE1:
  15.955 +		 begin
  15.956 +                    if(fifo_wr)
  15.957 +                      fifo_wr             <= #UDLY 1'b0;
  15.958 +                    if(MB_ACK_I) 
  15.959 +                      begin
  15.960 +			 direct_data      <= #UDLY 1'b0; 
  15.961 +     			 if(var_length) 
  15.962 +                           begin
  15.963 +                              MB_CYC_O      <= #UDLY 1'b0;
  15.964 +                              MB_STB_O      <= #UDLY 1'b0;
  15.965 +                              MB_CTI_O      <= #UDLY 3'h0;
  15.966 +                              if(!reg_s_con)
  15.967 +				begin
  15.968 +                                   MA_ADR_O   <= #UDLY MA_ADR_O + incr_unit;
  15.969 +				   if (incr_unit == 3'b001)
  15.970 +				     MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
  15.971 +				   else
  15.972 +				     if (incr_unit == 3'b010)
  15.973 +				       MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
  15.974 +				end
  15.975 +                              status        <= #UDLY ST_RDADDR1;
  15.976 +                              fifo_rd       <= #UDLY 1'b0;
  15.977 +                              burst_cnt     <= #UDLY burst_size;
  15.978 +                           end 
  15.979 +			 else 
  15.980 +                           begin
  15.981 +                              MB_CYC_O      <= #UDLY 1'b0;
  15.982 +                              MB_STB_O      <= #UDLY 1'b0;
  15.983 +                              MB_CTI_O      <= #UDLY 3'h0;
  15.984 +                              reg_cntlg_normal     <= #UDLY 1'b1;
  15.985 +                              status        <= #UDLY ST_CNTLNGTH1;
  15.986 +                              fifo_rd       <= #UDLY 1'b0;
  15.987 +                              burst_cnt     <= #UDLY burst_size;
  15.988 +                           end
  15.989 +                      end 
  15.990 +                    else if(MB_RTY_I) 
  15.991 +                      begin
  15.992 +			 if(var_length) 
  15.993 +                           begin
  15.994 +                              MB_CYC_O         <= #UDLY 1'b0;
  15.995 +                              MB_STB_O         <= #UDLY 1'b0;
  15.996 +                              MB_CTI_O         <= #UDLY 3'h0;
  15.997 +                              status           <= #UDLY ST_IDLE1;
  15.998 +                              reg_status_normal       <= #UDLY 1'b0;
  15.999 +                              reg_interrupt_normal    <= #UDLY 1'b1;
 15.1000 +                              var_length       <= #UDLY 1'b0;
 15.1001 +			      fifo_rd          <= #UDLY 1'b0;
 15.1002 +                           end
 15.1003 +                      end 
 15.1004 +                    else if(MB_ERR_I) 
 15.1005 +                      begin
 15.1006 +			 MB_CYC_O            <= #UDLY 1'b0;
 15.1007 +			 MB_STB_O            <= #UDLY 1'b0;
 15.1008 +			 MB_CTI_O            <= #UDLY 3'h0;
 15.1009 +			 status              <= #UDLY ST_IDLE1;
 15.1010 +			 reg_status_normal          <= #UDLY 1'b1;
 15.1011 +			 reg_interrupt_normal       <= #UDLY 1'b1;
 15.1012 +			 fifo_rd             <= #UDLY 1'b0;
 15.1013 +                      end
 15.1014 +		 end
 15.1015 +
 15.1016 +               ST_CNTLNGTH1:
 15.1017 +		 begin
 15.1018 +                    reg_cntlg_normal       <= #UDLY 1'b0;
 15.1019 +                    status                 <= #UDLY ST_JUSTICE1;
 15.1020 +		 end
 15.1021 +
 15.1022 +               ST_JUSTICE1:
 15.1023 +		 begin
 15.1024 +                    if(!(|data_length)) 
 15.1025 +                      begin
 15.1026 +			 status              <= #UDLY ST_IDLE1;
 15.1027 +			 reg_status_normal          <= #UDLY 1'b0;
 15.1028 +			 reg_interrupt_normal       <= #UDLY 1'b1;
 15.1029 +                      end 
 15.1030 +                    else 
 15.1031 +                      begin
 15.1032 +			 if(!reg_s_con)
 15.1033 +			   begin
 15.1034 +                              MA_ADR_O          <= #UDLY MA_ADR_O + incr_unit;
 15.1035 +			      if (incr_unit == 3'b001)
 15.1036 +				MA_SEL_O <= #UDLY {MA_SEL_O[0], MA_SEL_O[3:1]};
 15.1037 +			      else
 15.1038 +				if (incr_unit == 3'b010)
 15.1039 +				  MA_SEL_O <= #UDLY {MA_SEL_O[1:0], MA_SEL_O[3:2]};
 15.1040 +			   end
 15.1041 +			 status              <= #UDLY ST_RDADDR1;
 15.1042 +                      end
 15.1043 +		 end
 15.1044 +
 15.1045 +               default:
 15.1046 +		 begin
 15.1047 +                    status                 <= #UDLY ST_IDLE1;
 15.1048 +                    var_length             <= #UDLY 1'b0;
 15.1049 +                    MA_CYC_O               <= #UDLY 1'b0;
 15.1050 +                    MA_CTI_O               <= #UDLY 3'h0;
 15.1051 +                    MB_CYC_O               <= #UDLY 1'b0;
 15.1052 +                    MB_CTI_O               <= #UDLY 3'h0;
 15.1053 +                    MA_STB_O               <= #UDLY 1'b0;
 15.1054 +                    MB_STB_O               <= #UDLY 1'b0;
 15.1055 +                    reg_status_normal             <= #UDLY 1'b0;
 15.1056 +                    reg_interrupt_normal          <= #UDLY 1'b0;
 15.1057 +                    reg_cntlg_normal       <= #UDLY 1'b0;
 15.1058 +                    burst_size             <= #UDLY 3'h0;
 15.1059 +                    burst_cnt              <= #UDLY 3'h0;
 15.1060 +                    fifo_wr                <= #UDLY 1'b0;
 15.1061 +                    fifo_rd                <= #UDLY 1'b0;
 15.1062 +                    fifo_clear             <= #UDLY 1'b0;
 15.1063 +                    latch_start            <= #UDLY 1'b0;
 15.1064 +		    direct_data            <= #UDLY 1'b0;
 15.1065 +		 end
 15.1066 +             endcase	       
 15.1067 +	  end 	       
 15.1068 +       end 
 15.1069 +
 15.1070 +   //Task for generating write enable to the FIFO
 15.1071 +   task write_fifo;
 15.1072 +      begin
 15.1073 +         if(MA_ACK_I)
 15.1074 +           begin
 15.1075 +              fifo_wr         <= #UDLY 1'b1;
 15.1076 +              fifo_din        <= #UDLY MA_DAT_I;
 15.1077 +           end
 15.1078 +         else
 15.1079 +           begin
 15.1080 +              fifo_wr         <= #UDLY 1'b0;
 15.1081 +           end
 15.1082 +      end
 15.1083 +   endtask
 15.1084 +
 15.1085 +   //Task for generating read enable signal to the FIFO
 15.1086 +   task read_fifo;
 15.1087 +      begin
 15.1088 +         fifo_rd              <= #UDLY 1'b1;
 15.1089 +      end
 15.1090 +   endtask
 15.1091 +
 15.1092 +   //Task for setting wishbone CTI signal for read 
 15.1093 +   //master port depending upon whether request is for burst
 15.1094 +   //transfer or classic cycle.
 15.1095 +   task set_cti_a;
 15.1096 +      begin
 15.1097 +         if(reg_bt2)
 15.1098 +           begin
 15.1099 +              if(reg_s_con)
 15.1100 +                MA_CTI_O      <= #UDLY 3'b001;
 15.1101 +              else
 15.1102 +                MA_CTI_O      <= #UDLY 3'b010;
 15.1103 +           end
 15.1104 +         else
 15.1105 +           MA_CTI_O           <= #UDLY 3'b000;
 15.1106 +      end
 15.1107 +   endtask
 15.1108 +
 15.1109 +   //Task for setting wishbone CTI signal for write 
 15.1110 +   //master port depending upon whether request is for burst
 15.1111 +   //transfer or classic cycle.      
 15.1112 +   task set_cti_b;
 15.1113 +      begin
 15.1114 +         if(reg_bt2) begin
 15.1115 +            if(reg_d_con)
 15.1116 +              MB_CTI_O      <= #UDLY 3'b001;
 15.1117 +            else
 15.1118 +              MB_CTI_O      <= #UDLY 3'b010;
 15.1119 +         end else
 15.1120 +           MB_CTI_O           <= #UDLY 3'b000;
 15.1121 +      end
 15.1122 +   endtask
 15.1123 +
 15.1124 +   //RdEn
 15.1125 +   reg fifo_rd_dly;
 15.1126 +   always @(posedge CLK_I or posedge RST_I)
 15.1127 +     if(RST_I)
 15.1128 +       fifo_rd_dly            <= #UDLY 1'b0;
 15.1129 +     else
 15.1130 +       fifo_rd_dly            <= #UDLY fifo_rd;
 15.1131 +
 15.1132 +   wire RdEn = fifo_rd & (!fifo_rd_dly | (reg_bt2 ? (burst_cnt2[5:0] != 5'b00000) : (burst_cnt[5:0] != 5'b00000)) & MB_ACK_I) | fifo_clear;
 15.1133 +
 15.1134 +   generate
 15.1135 +      if (lat_family == "SC" || lat_family == "SCM") begin
 15.1136 +
 15.1137 +         pmi_fifo_dc #(.pmi_data_width_w(32),
 15.1138 +		       .pmi_data_width_r(32),
 15.1139 +		       .pmi_data_depth_w(32),
 15.1140 +		       .pmi_data_depth_r(32),
 15.1141 +		       .pmi_full_flag(32),
 15.1142 +		       .pmi_empty_flag(0),
 15.1143 +		       .pmi_almost_full_flag(28),
 15.1144 +		       .pmi_almost_empty_flag(4),
 15.1145 +		       .pmi_regmode("noreg"),
 15.1146 +		       .pmi_family(`LATTICE_FAMILY),
 15.1147 +		       .module_type("pmi_fifo_dc"),
 15.1148 +                       .pmi_implementation(FIFO_IMPLEMENTATION))
 15.1149 +	   dma_fifo_dc (
 15.1150 +                        .Data(fifo_din),
 15.1151 +                        .WrClock(CLK_I),
 15.1152 +			.RdClock(CLK_I),
 15.1153 +			.WrEn	(fifo_wr),
 15.1154 +			.RdEn	(RdEn),
 15.1155 +			.Reset	(RST_I),
 15.1156 +			.RPReset(RST_I),
 15.1157 +			.Q	(fifo_dout),
 15.1158 +			.Empty	(fifo_empty),
 15.1159 +			.Full	(),
 15.1160 +			.AlmostEmpty (),
 15.1161 +			.AlmostFull ());
 15.1162 +         
 15.1163 +	
 15.1164 +      
 15.1165 +      end else begin
 15.1166 +	 pmi_fifo #(.pmi_data_width(32),
 15.1167 +		    .pmi_data_depth(32),
 15.1168 +		    .pmi_full_flag(32),
 15.1169 +		    .pmi_empty_flag(0),
 15.1170 +		    .pmi_almost_full_flag(28),
 15.1171 +		    .pmi_almost_empty_flag(1),
 15.1172 +		    .pmi_regmode("noreg"),
 15.1173 +		    .pmi_family(`LATTICE_FAMILY),
 15.1174 +		    .module_type("pmi_fifo"),
 15.1175 +                    .pmi_implementation(FIFO_IMPLEMENTATION))
 15.1176 +	   dma_fifo (.Data 	(fifo_din),
 15.1177 +		     .Clock	(CLK_I),
 15.1178 +		     .WrEn	(fifo_wr),
 15.1179 +		     .RdEn	(RdEn),
 15.1180 +		     .Reset	(RST_I),
 15.1181 +		     .Q	        (fifo_dout),
 15.1182 +		     .Empty	(fifo_empty),
 15.1183 +		     .Full	(),
 15.1184 +		     .AlmostEmpty (fifo_aempty),
 15.1185 +		     .AlmostFull ());
 15.1186 +      end  
 15.1187 +   endgenerate
 15.1188 +   
 15.1189 +endmodule // MASTER_CTRL
 15.1190 +
 15.1191 +`endif // MASTER_CTRL_FILE
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/rtl/verilog/slave_reg.v	Fri Aug 13 10:43:05 2010 +0100
    16.3 @@ -0,0 +1,234 @@
    16.4 +// =============================================================================
    16.5 +//                           COPYRIGHT NOTICE
    16.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    16.7 +// ALL RIGHTS RESERVED
    16.8 +// This confidential and proprietary software may be used only as authorised by
    16.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   16.10 +// The entire notice above must be reproduced on all authorized copies and
   16.11 +// copies may only be made to the extent permitted by a licensing agreement from
   16.12 +// Lattice Semiconductor Corporation.
   16.13 +//
   16.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   16.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   16.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   16.17 +// U.S.A                                   email: techsupport@latticesemi.com
   16.18 +// =============================================================================/
   16.19 +//                         FILE DETAILS
   16.20 +// Project          : LM32 DMA Component
   16.21 +// File             : slave_reg.v
   16.22 +// Title            : DMA Slave controller 
   16.23 +// Dependencies     : None
   16.24 +// Version          : 7.0
   16.25 +//                  : Initial Release
   16.26 +// Version          : 7.0SP2, 3.0
   16.27 +//   1. Read and Write channel of DMA controller are working in parallel,
   16.28 +//      due to that now as soon as FIFO is not empty write channel of the DMA
   16.29 +//      controller start writing data to the slave.
   16.30 +//   2. Burst Size supported by DMA controller is increased to support bigger
   16.31 +//      burst (from current value of 4 and 8 to 16 and 32). Now 4 different type
   16.32 +//      of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 
   16.33 +//      For this Burst Size field of the control register is increased to 2 bits.
   16.34 +//   3. Glitch is removed on the S_ACK_O signal. 
   16.35 +// Version          : 3.1
   16.36 +//                  : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec
   16.37 +//                  : which defines alignement of bytes in sub-word transfers.
   16.38 +// =============================================================================
   16.39 +
   16.40 +`ifndef SLAVE_REG_FILE
   16.41 + `define SLAVE_REG_FILE
   16.42 + `include "system_conf.v"
   16.43 +module SLAVE_REG 
   16.44 +  #(parameter LENGTH_WIDTH = 16,
   16.45 +    parameter FIFO_IMPLEMENTATION = "EBR")
   16.46 +    (
   16.47 +     //slave port
   16.48 +     S_ADR_I,    //32bits
   16.49 +     S_DAT_I,    //32bits
   16.50 +     S_WE_I,
   16.51 +     S_STB_I,
   16.52 +     S_CYC_I,
   16.53 +     S_CTI_I,
   16.54 +     S_DAT_O,    //32bits
   16.55 +     S_ACK_O,
   16.56 +     S_INT_O,
   16.57 +     //Master Address
   16.58 +//      MA_SEL_O,
   16.59 +//      MB_SEL_O,
   16.60 +     M_SEL_O,
   16.61 +     //internal signals
   16.62 +     reg_start,
   16.63 +     reg_status,
   16.64 +     reg_interrupt,
   16.65 +     reg_busy,
   16.66 +     data_length,
   16.67 +     reg_cntlg,
   16.68 +     reg_bt2,reg_bt1,reg_bt0,
   16.69 +     incr_unit,
   16.70 +     reg_s_con,
   16.71 +     reg_d_con,
   16.72 +     reg_00_data,
   16.73 +     reg_04_data,
   16.74 +     //system clock and reset
   16.75 +     CLK_I,
   16.76 +     RST_I
   16.77 +     );
   16.78 +
   16.79 +   input [31:0]    S_ADR_I;
   16.80 +   input [31:0]    S_DAT_I;    //32bits
   16.81 +   input           S_WE_I;
   16.82 +   input           S_STB_I;
   16.83 +   input           S_CYC_I;
   16.84 +   input [2:0]     S_CTI_I;
   16.85 +   output [31:0]   S_DAT_O;    //32bits
   16.86 +   output          S_ACK_O;
   16.87 +   output          S_INT_O;    //interrupt signal
   16.88 +   //Master Address
   16.89 +   output [3:0] M_SEL_O;
   16.90 +//    output [3:0]    MA_SEL_O;
   16.91 +//    output [3:0]    MB_SEL_O;
   16.92 +   //internal signals
   16.93 +   output          reg_start;
   16.94 +   input           reg_status;
   16.95 +   input           reg_interrupt;
   16.96 +   input           reg_busy;
   16.97 +   output [LENGTH_WIDTH-1:0] data_length;
   16.98 +   input                     reg_cntlg;
   16.99 +   output                    reg_bt2,reg_bt1,reg_bt0;
  16.100 +   output [2:0]              incr_unit;
  16.101 +   output                    reg_s_con;
  16.102 +   output                    reg_d_con;
  16.103 +   output [31:0]             reg_00_data;
  16.104 +   output [31:0]             reg_04_data;
  16.105 +
  16.106 +   //system clock and reset
  16.107 +   input                     CLK_I;
  16.108 +   input                     RST_I;
  16.109 +
  16.110 +   parameter                 UDLY = 1;
  16.111 +
  16.112 +   reg [31:0]                reg_00_data;
  16.113 +   reg [31:0]                reg_04_data;
  16.114 +   reg [LENGTH_WIDTH-1:0]    reg_08_data;
  16.115 +   reg [6:0]                 reg_0c_data;
  16.116 +
  16.117 +   reg [3:0]                 M_SEL_O;
  16.118 +//    wire [3:0]                MA_SEL_O    = M_SEL_O;
  16.119 +//    wire [3:0]                MB_SEL_O    = M_SEL_O;
  16.120 +   wire [LENGTH_WIDTH-1:0]   data_length    = reg_08_data;
  16.121 +
  16.122 +   wire                      reg_bt2, reg_bt1, reg_bt0, reg_incw, reg_inchw, reg_d_con, reg_s_con;
  16.123 +   assign                    {reg_bt2,reg_bt1,reg_bt0,reg_incw,reg_inchw,reg_d_con,reg_s_con} = reg_0c_data;
  16.124 +   wire [2:0]                incr_unit = reg_incw ? 4 : reg_inchw ? 2 : 1;
  16.125 +
  16.126 +   wire [8:0]                burst_incr_unit = reg_bt2 ? (reg_bt1 ? (reg_bt0 ? incr_unit<<5 : incr_unit<<4) : (reg_bt0 ? incr_unit<<3 : incr_unit<<2)) : incr_unit;
  16.127 +   reg                       reg_ie;
  16.128 +   wire [2:0]                read_10_data    = {reg_status,reg_ie,reg_busy};
  16.129 +
  16.130 +   wire                      reg_wr_rd    = S_CYC_I && S_STB_I;
  16.131 +
  16.132 +   wire                      master_idle = !reg_busy;
  16.133 +   reg                       s_ack_o_pre;
  16.134 +   wire                      S_ACK_O    = s_ack_o_pre  && S_CYC_I && S_STB_I;
  16.135 +   
  16.136 +   always @(posedge CLK_I or posedge RST_I)
  16.137 +     if(RST_I)
  16.138 +       s_ack_o_pre         <= #UDLY 1'b0;
  16.139 +     else if(((master_idle && reg_wr_rd) || (!master_idle && reg_wr_rd && !S_WE_I)) && (!s_ack_o_pre)) 
  16.140 +       s_ack_o_pre         <= #UDLY 1'b1;
  16.141 +     else	     
  16.142 +       s_ack_o_pre         <= #UDLY 1'b0;
  16.143 +
  16.144 +
  16.145 +   //register write and read
  16.146 +   wire                      reg_wr          = reg_wr_rd && S_WE_I && master_idle && S_ACK_O;
  16.147 +   wire                      reg_rd          = reg_wr_rd && !S_WE_I && S_ACK_O;
  16.148 +
  16.149 +   wire                      dw00_cs         = (!(|S_ADR_I[5:2]));
  16.150 +   wire                      dw04_cs         = (S_ADR_I[5:2] == 4'h1);
  16.151 +   wire                      dw08_cs         = (S_ADR_I[5:2] == 4'h2);
  16.152 +   wire                      dw0c_cs         = (S_ADR_I[5:2] == 4'h3);
  16.153 +   wire                      dw10_cs         = (S_ADR_I[5:2] == 4'h4);
  16.154 +
  16.155 +   //S_DAT_O
  16.156 +   wire [31:0]               S_DAT_O = dw00_cs ? reg_00_data :
  16.157 +                             dw04_cs ? reg_04_data :
  16.158 +                             dw08_cs ? reg_08_data :
  16.159 +                             dw0c_cs ? {24'h0,1'h0,reg_0c_data} :
  16.160 +                             dw10_cs ? {24'h0,5'h0,read_10_data} : 32'h0;
  16.161 +
  16.162 +   always @(posedge CLK_I or posedge RST_I)
  16.163 +     if(RST_I)
  16.164 +       M_SEL_O             <= #UDLY 4'h0;
  16.165 +     else if(data_length < incr_unit)
  16.166 +       case(data_length[2:0])
  16.167 +         1:    M_SEL_O     <= #UDLY 4'h8;
  16.168 +         2:    M_SEL_O     <= #UDLY 4'hc;
  16.169 +         3:    M_SEL_O     <= #UDLY 4'he;
  16.170 +         default:M_SEL_O   <= #UDLY 4'hf;
  16.171 +       endcase
  16.172 +     else
  16.173 +       case(incr_unit)
  16.174 +         1:    M_SEL_O     <= #UDLY 4'h8;
  16.175 +         2:    M_SEL_O     <= #UDLY 4'hc;
  16.176 +         4:    M_SEL_O     <= #UDLY 4'hf;
  16.177 +         default:M_SEL_O   <= #UDLY 4'hf;
  16.178 +       endcase
  16.179 +   //interrupt
  16.180 +   reg                       S_INT_O;
  16.181 +   always @(posedge CLK_I or posedge RST_I)
  16.182 +     if(RST_I)
  16.183 +       S_INT_O             <= #UDLY 1'b0;
  16.184 +     else if(reg_interrupt && reg_ie)
  16.185 +       S_INT_O             <= #UDLY 1'b1;
  16.186 +     else if(dw10_cs && reg_rd)
  16.187 +       S_INT_O             <= #UDLY 1'b0;
  16.188 +
  16.189 +   //reg_00
  16.190 +   always @(posedge CLK_I or posedge RST_I)
  16.191 +     if(RST_I)
  16.192 +       reg_00_data         <= #UDLY 32'h0;
  16.193 +     else if(dw00_cs && reg_wr)
  16.194 +       reg_00_data         <= #UDLY S_DAT_I;
  16.195 +
  16.196 +   //reg_04
  16.197 +   always @(posedge CLK_I or posedge RST_I)
  16.198 +     if(RST_I)
  16.199 +       reg_04_data         <= #UDLY 32'h0;
  16.200 +     else if(dw04_cs && reg_wr)
  16.201 +       reg_04_data         <= #UDLY S_DAT_I;
  16.202 +
  16.203 +   //reg_08
  16.204 +   always @(posedge CLK_I or posedge RST_I)
  16.205 +     if(RST_I)
  16.206 +       reg_08_data         <= #UDLY 32'h0;
  16.207 +     else if(reg_cntlg)
  16.208 +       reg_08_data         <= #UDLY (reg_08_data < burst_incr_unit) ? 'h0 : (reg_08_data - burst_incr_unit);
  16.209 +     else if(dw08_cs && reg_wr)
  16.210 +       reg_08_data         <= #UDLY S_DAT_I;
  16.211 +
  16.212 +   //reg_0c
  16.213 +   always @(posedge CLK_I or posedge RST_I)
  16.214 +     if(RST_I)
  16.215 +       reg_0c_data         <= #UDLY 7'h0;
  16.216 +     else if(dw0c_cs && reg_wr)
  16.217 +       reg_0c_data         <= #UDLY S_DAT_I[6:0];
  16.218 +
  16.219 +   //reg_10
  16.220 +   reg                       reg_start;
  16.221 +   always @(posedge CLK_I or posedge RST_I)
  16.222 +     if(RST_I)
  16.223 +       begin
  16.224 +          reg_ie           <= #UDLY 1'b0;
  16.225 +          reg_start        <= #UDLY 1'b0;
  16.226 +       end 
  16.227 +     else if(dw10_cs && reg_wr) 
  16.228 +       begin
  16.229 +          reg_ie           <= #UDLY S_DAT_I[1];
  16.230 +          reg_start        <= #UDLY S_DAT_I[3];
  16.231 +       end 
  16.232 +     else 
  16.233 +       begin
  16.234 +          reg_start        <= #UDLY 1'b0;
  16.235 +       end
  16.236 +endmodule // SLAVE_REG
  16.237 +`endif // SLAVE_REG_FILE
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/rtl/verilog/wb_dma_ctrl.v	Fri Aug 13 10:43:05 2010 +0100
    17.3 @@ -0,0 +1,237 @@
    17.4 +// =============================================================================
    17.5 +//                           COPYRIGHT NOTICE
    17.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    17.7 +// ALL RIGHTS RESERVED
    17.8 +// This confidential and proprietary software may be used only as authorised by
    17.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   17.10 +// The entire notice above must be reproduced on all authorized copies and
   17.11 +// copies may only be made to the extent permitted by a licensing agreement from
   17.12 +// Lattice Semiconductor Corporation.
   17.13 +//
   17.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   17.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   17.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   17.17 +// U.S.A                                   email: techsupport@latticesemi.com
   17.18 +// =============================================================================/
   17.19 +//                         FILE DETAILS
   17.20 +// Project          : LM32 DMA Component
   17.21 +// File             : wb_dma_ctrl.v
   17.22 +// Title            : DMA controller top file
   17.23 +// Dependencies     : None
   17.24 +// Version          : 7.0
   17.25 +//                  : Initial Release
   17.26 +// Version          : 7.0SP2, 3.0
   17.27 +//   1. Read and Write channel of DMA controller are working in parallel,
   17.28 +//      due to that now as soon as FIFO is not empty write channel of the DMA
   17.29 +//      controller start writing data to the slave.
   17.30 +//   2. Burst Size supported by DMA controller is increased to support bigger
   17.31 +//      burst (from current value of 4 and 8 to 16 and 32). Now 4 different type
   17.32 +//      of burst sizes are supported by the DMA controller 4, 8, 16 and 32. 
   17.33 +//      For this Burst Size field of the control register is increased to 2 bits.
   17.34 +//   3. Glitch is removed on the S_ACK_O signal. 
   17.35 +// Version          : 3.1
   17.36 +//                  : Make DMA Engine compliant to Rule 3.100 of Wishbone Spec
   17.37 +//                  : which defines alignement of bytes in sub-word transfers.
   17.38 +// =============================================================================
   17.39 +
   17.40 +`ifndef WB_DMA_CTRL_FILE
   17.41 +`define WB_DMA_CTRL_FILE
   17.42 +`include "system_conf.v"
   17.43 +module wb_dma_ctrl #(parameter LENGTH_WIDTH = 16,
   17.44 +                     parameter FIFO_IMPLEMENTATION = "EBR")
   17.45 +(
   17.46 +         //master read port
   17.47 +         MA_ADR_O,    //32bits
   17.48 +         MA_WE_O,
   17.49 +         MA_SEL_O,    //4bits
   17.50 +         MA_STB_O,
   17.51 +         MA_CYC_O,
   17.52 +         MA_LOCK_O,
   17.53 +         MA_CTI_O,
   17.54 +         MA_BTE_O,
   17.55 +         MA_DAT_I,    //32bits
   17.56 +         MA_DAT_O,    //32bits
   17.57 +         MA_ACK_I,
   17.58 +         MA_ERR_I,
   17.59 +         MA_RTY_I,
   17.60 +         //master write port
   17.61 +         MB_ADR_O,    //32bits
   17.62 +         MB_DAT_O,    //32bits
   17.63 +         MB_WE_O,
   17.64 +         MB_SEL_O,    //4bits
   17.65 +         MB_STB_O,
   17.66 +         MB_CYC_O,
   17.67 +         MB_LOCK_O,
   17.68 +         MB_CTI_O,
   17.69 +         MB_BTE_O,
   17.70 +         MB_DAT_I,    //32bits
   17.71 +         MB_ACK_I,
   17.72 +         MB_ERR_I,
   17.73 +         MB_RTY_I,
   17.74 +         //slave port
   17.75 +         S_ADR_I,    //32bits
   17.76 +         S_DAT_I,    //32bits
   17.77 +         S_WE_I,
   17.78 +         S_STB_I,
   17.79 +         S_CYC_I,
   17.80 +         S_SEL_I,
   17.81 +         S_LOCK_I,
   17.82 +         S_CTI_I,
   17.83 +         S_BTE_I,
   17.84 +         S_DAT_O,    //32bits
   17.85 +         S_ACK_O,
   17.86 +         S_ERR_O,
   17.87 +         S_RTY_O,
   17.88 +         S_INT_O,
   17.89 +         //system clock and reset
   17.90 +         CLK_I,
   17.91 +         RST_I
   17.92 +         );
   17.93 +   //master read port
   17.94 +   output [31:0]    MA_ADR_O;    //32bits
   17.95 +   output           MA_WE_O;
   17.96 +   output [3:0]     MA_SEL_O;    //4bits
   17.97 +   output           MA_STB_O;
   17.98 +   output           MA_CYC_O;
   17.99 +   output           MA_LOCK_O;
  17.100 +   output [2:0]     MA_CTI_O;
  17.101 +   output [1:0]     MA_BTE_O;   
  17.102 +   output [31:0]    MA_DAT_O;    //32bits
  17.103 +   input [31:0]     MA_DAT_I;    //32bits
  17.104 +   input            MA_ACK_I;
  17.105 +   input            MA_ERR_I;
  17.106 +   input            MA_RTY_I;
  17.107 +   //master write port
  17.108 +   output [31:0]    MB_ADR_O;    //32bits
  17.109 +   output [31:0]    MB_DAT_O;    //32bits
  17.110 +   output           MB_WE_O;
  17.111 +   output [3:0]     MB_SEL_O;    //4bits
  17.112 +   output           MB_STB_O;
  17.113 +   output           MB_CYC_O;
  17.114 +   output [2:0]     MB_CTI_O;
  17.115 +   output           MB_LOCK_O;
  17.116 +   output [1:0]     MB_BTE_O;   
  17.117 +   input [31:0]     MB_DAT_I;    //32bits
  17.118 +   input            MB_ACK_I;
  17.119 +   input            MB_ERR_I;
  17.120 +   input            MB_RTY_I;
  17.121 +   //slave port
  17.122 +   input [31:0]     S_ADR_I;    //32bits
  17.123 +   input [31:0]     S_DAT_I;    //32bits
  17.124 +   input            S_WE_I;
  17.125 +   input            S_STB_I;
  17.126 +   input            S_CYC_I;
  17.127 +   input [2:0]      S_CTI_I;
  17.128 +   input [1:0]      S_BTE_I;   
  17.129 +   input [3:0]      S_SEL_I;
  17.130 +   input            S_LOCK_I;   
  17.131 +   output [31:0]    S_DAT_O;    //32bits
  17.132 +   output           S_ACK_O;
  17.133 +   output           S_ERR_O;
  17.134 +   output           S_RTY_O;
  17.135 +   output           S_INT_O;
  17.136 +   //system clock and reset
  17.137 +   input            CLK_I;
  17.138 +   input            RST_I;
  17.139 +
  17.140 +   wire [31:0]      MA_DAT_O = 0;
  17.141 +   wire [1:0]       MA_BTE_O = 0;
  17.142 +   wire             MA_LOCK_O;
  17.143 +   
  17.144 +   wire [1:0]       MB_BTE_O = 0;
  17.145 +   wire             MB_LOCK_O;
  17.146 +
  17.147 +   wire             S_ERR_O = 0;
  17.148 +   wire             S_RTY_O = 0;
  17.149 +   
  17.150 +   wire [LENGTH_WIDTH-1:0]   data_length;//read back data
  17.151 +   wire [2:0]   incr_unit;
  17.152 +   wire [31:0]  reg_00_data;
  17.153 +   wire [31:0]  reg_04_data;
  17.154 +   wire [3:0] 	M_SEL_O;
  17.155 +   
  17.156 +   //slave port:master write/read data to/from register file.
  17.157 +   SLAVE_REG  #(.LENGTH_WIDTH(LENGTH_WIDTH),
  17.158 +                .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION))  SLAVE_REG(
  17.159 +           .S_ADR_I            (S_ADR_I        ),
  17.160 +           .S_DAT_I            (S_DAT_I        ),
  17.161 +           .S_WE_I             (S_WE_I         ),
  17.162 +           .S_STB_I            (S_STB_I        ),
  17.163 +           .S_CYC_I            (S_CYC_I        ),
  17.164 +           .S_CTI_I            (S_CTI_I        ),
  17.165 +           .S_DAT_O            (S_DAT_O        ),
  17.166 +           .S_ACK_O            (S_ACK_O        ),
  17.167 +           .S_INT_O            (S_INT_O        ),
  17.168 +           //Master Addr
  17.169 +           .M_SEL_O            (M_SEL_O        ),
  17.170 +//            .MA_SEL_O           (MA_SEL_O       ),
  17.171 +//            .MB_SEL_O           (MB_SEL_O       ),
  17.172 +           //internal signals
  17.173 +           .reg_start          (reg_start      ),
  17.174 +           .reg_status         (reg_status     ),
  17.175 +           .reg_interrupt      (reg_interrupt  ),
  17.176 +           .reg_busy           (reg_busy       ),
  17.177 +           .data_length        (data_length    ),
  17.178 +           .reg_cntlg          (reg_cntlg      ),
  17.179 +	   .reg_bt2            (reg_bt2        ), 
  17.180 +           .reg_bt1            (reg_bt1        ),
  17.181 +           .reg_bt0            (reg_bt0        ),
  17.182 +           .reg_s_con          (reg_s_con      ),
  17.183 +           .reg_d_con          (reg_d_con      ),
  17.184 +           .incr_unit          (incr_unit      ),
  17.185 +           .reg_00_data        (reg_00_data    ),
  17.186 +           .reg_04_data        (reg_04_data    ),
  17.187 +           //system clock and reset
  17.188 +           .CLK_I              (CLK_I          ),
  17.189 +           .RST_I              (RST_I          )
  17.190 +           );
  17.191 +   
  17.192 +   //Master control
  17.193 +   MASTER_CTRL   #(.LENGTH_WIDTH(LENGTH_WIDTH),
  17.194 +                   .FIFO_IMPLEMENTATION(FIFO_IMPLEMENTATION))   MASTER_CTRL(
  17.195 +               //master read port
  17.196 +               .MA_ADR_O           (MA_ADR_O       ),
  17.197 +               .MA_SEL_O           (MA_SEL_O       ),
  17.198 +               .MA_WE_O            (MA_WE_O        ),
  17.199 +               .MA_STB_O           (MA_STB_O       ),
  17.200 +               .MA_CYC_O           (MA_CYC_O       ),
  17.201 +               .MA_CTI_O           (MA_CTI_O       ),
  17.202 +	       .MA_LOCK_O          (MA_LOCK_O      ),
  17.203 +               .MA_DAT_I           (MA_DAT_I       ),    //32bits
  17.204 +               .MA_ACK_I           (MA_ACK_I       ),
  17.205 +               .MA_ERR_I           (MA_ERR_I       ),
  17.206 +               .MA_RTY_I           (MA_RTY_I       ),
  17.207 +               //master write port
  17.208 +               .MB_ADR_O           (MB_ADR_O       ),
  17.209 +               .MB_SEL_O           (MB_SEL_O       ),
  17.210 +               .MB_DAT_O           (MB_DAT_O       ),    //32bits
  17.211 +               .MB_WE_O            (MB_WE_O        ),
  17.212 +               .MB_STB_O           (MB_STB_O       ),
  17.213 +               .MB_CYC_O           (MB_CYC_O       ),
  17.214 +               .MB_CTI_O           (MB_CTI_O       ),
  17.215 +	       .MB_LOCK_O          (MB_LOCK_O      ),
  17.216 +               .MB_ACK_I           (MB_ACK_I       ),
  17.217 +               .MB_ERR_I           (MB_ERR_I       ),
  17.218 +               .MB_RTY_I           (MB_RTY_I       ),
  17.219 +               //register interface
  17.220 +               .M_SEL_O            (M_SEL_O        ),
  17.221 +               .reg_start          (reg_start      ),
  17.222 +               .reg_status         (reg_status     ),
  17.223 +               .reg_interrupt      (reg_interrupt  ),
  17.224 +               .reg_busy           (reg_busy       ),
  17.225 +               .data_length        (data_length    ),
  17.226 +               .reg_cntlg          (reg_cntlg      ),
  17.227 +	       .reg_bt2            (reg_bt2        ),
  17.228 +               .reg_bt1            (reg_bt1        ),
  17.229 +               .reg_bt0            (reg_bt0        ),
  17.230 +               .reg_s_con          (reg_s_con      ),
  17.231 +               .reg_d_con          (reg_d_con      ),
  17.232 +               .incr_unit          (incr_unit      ),
  17.233 +               .reg_00_data        (reg_00_data    ),
  17.234 +               .reg_04_data        (reg_04_data    ),
  17.235 +               //system clock and reset
  17.236 +               .CLK_I              (CLK_I          ),
  17.237 +               .RST_I              (RST_I          )
  17.238 +               );
  17.239 +endmodule // WB_DMA_CTRL
  17.240 +`endif // WB_DMA_CTRL_FILE