Initial commit, GPIO v3.1

Fri, 13 Aug 2010 10:41:29 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 13 Aug 2010 10:41:29 +0100
changeset 0
267b5a25932f
child 1
dfc32cad81ba

Initial commit, GPIO v3.1

document/ds_icon.jpg file | annotate | diff | revisions
document/ds_icon_ast.jpg file | annotate | diff | revisions
document/dsb_icon.jpg file | annotate | diff | revisions
document/gpio.htm file | annotate | diff | revisions
document/gpio.pdf file | annotate | diff | revisions
document/lever40.css file | annotate | diff | revisions
document/lever40_ns.css file | annotate | diff | revisions
document/qm_icon.jpg file | annotate | diff | revisions
drivers/device/LCD.c file | annotate | diff | revisions
drivers/device/LCD.h file | annotate | diff | revisions
drivers/device/MicoGPIO.c file | annotate | diff | revisions
drivers/device/MicoGPIO.h file | annotate | diff | revisions
drivers/peripheral.mk file | annotate | diff | revisions
drivers/service/MicoGPIOService.c file | annotate | diff | revisions
drivers/service/MicoGPIOService.h file | annotate | diff | revisions
gpio.xml file | annotate | diff | revisions
rtl/verilog/gpio.v file | annotate | diff | revisions
rtl/verilog/tpio.v file | annotate | diff | revisions
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     3.1 Binary file document/dsb_icon.jpg has changed
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    4.87 +<!--
    4.88 +if (window.gbWhTopic)
    4.89 +{
    4.90 +	if (window.setRelStartPage)
    4.91 +	{
    4.92 +	addTocInfo("GPIO");
    4.93 +
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    4.95 +
    4.96 +
    4.97 +	if (window.setRelStartPage)
    4.98 +	{
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   4.112 +</head>
   4.113 +<body><script type="text/javascript" language="javascript1.2">
   4.114 +<!--
   4.115 +if (window.writeIntopicBar)
   4.116 +	writeIntopicBar(4);
   4.117 +//-->
   4.118 +</script>
   4.119 +<h1>LatticeMico32 GPIO &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Data Sheet" href="gpio.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Data Sheet');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   4.120 +
   4.121 +<p>The LatticeMico32 general-purpose input/output core (GPIO) provides 
   4.122 + a memory-mapped interface between a WISHBONE slave port and general-purpose 
   4.123 + I/O ports. The I/O ports can connect to either on-chip or off-chip logic.</p>
   4.124 +
   4.125 +<p class="whs2">*If the data sheet fails to open, see the 
   4.126 + note at the bottom of this page.</p>
   4.127 +
   4.128 +<h2>Revision History</h2>
   4.129 +
   4.130 +&nbsp; 
   4.131 +
   4.132 +<table x-use-null-cells cellspacing="0" width="637" height="84" class="whs3">
   4.133 +<script language='JavaScript'><!--
   4.134 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table><table x-use-null-cells cellspacing='0' width='637' height='84' border='1' bordercolor='silver' bordercolorlight='silver' bordercolordark='silver'>");
   4.135 +//--></script>
   4.136 +<col class="whs4">
   4.137 +<col class="whs5">
   4.138 +
   4.139 +<tr valign="top" class="whs6">
   4.140 +<td bgcolor="#DEE8F4" width="85px" class="whs7">
   4.141 +<p class=Table
   4.142 +	style="font-weight: bold;">Version</td>
   4.143 +<td bgcolor="#DEE8F4" width="505px" class="whs8">
   4.144 +<p class=Table
   4.145 +	style="font-weight: bold;">Description</td></tr>
   4.146 +
   4.147 +<tr valign="top" class="whs6">
   4.148 +<td colspan="1" rowspan="1" width="85px" class="whs9">
   4.149 +<p class=Table
   4.150 +	style="font-weight: normal;">3.1 (7.2)</td>
   4.151 +<td colspan="1" rowspan="1" width="505px" class="whs10">
   4.152 +<p class=Table>Updated the Edge Capture Register clean method</p>
   4.153 +<p class=Table>Made IRQ Mask register readable</td></tr>
   4.154 +
   4.155 +<tr valign="top" class="whs6">
   4.156 +<td colspan="1" rowspan="1" width="85px" class="whs9">
   4.157 +<p class=Table
   4.158 +	style="font-weight: normal;">3.0 (7.0 SP2)</td>
   4.159 +<td colspan="1" rowspan="1" width="505px" class="whs10">
   4.160 +<p class=Table>Cleaned up code. No function change.</td></tr>
   4.161 +
   4.162 +<tr valign="top" class="whs6">
   4.163 +<td colspan="1" rowspan="1" width="85px" class="whs9">
   4.164 +<p class=Table
   4.165 +	style="font-weight: normal;">1.0</td>
   4.166 +<td colspan="1" rowspan="1" width="505px" class="whs10">
   4.167 +<p class=Table>Initial release.</td></tr>
   4.168 +<script language='JavaScript'><!--
   4.169 +if ((navigator.appName == "Netscape") && (parseInt(navigator.appVersion) == 4)) document.write("</table></table><table>");
   4.170 +//--></script>
   4.171 +</table>
   4.172 +
   4.173 +<h2>Dialog Box Parameters</h2>
   4.174 +
   4.175 +<table x-use-null-cells cellspacing="0" class="whs11">
   4.176 +<col class="whs4">
   4.177 +<col class="whs12">
   4.178 +
   4.179 +<tr valign="top" class="whs13">
   4.180 +<td bgcolor="#DEE8F4" width="85px" class="whs14">
   4.181 +<p class=Table
   4.182 +	style="font-weight: bold;">Parameter</td>
   4.183 +<td bgcolor="#DEE8F4" width="503px" class="whs15">
   4.184 +<p class=Table
   4.185 +	style="font-weight: bold;">Description</td></tr>
   4.186 +
   4.187 +<tr valign="top" class="whs13">
   4.188 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.189 +<p class=Table>Instance Name</td>
   4.190 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.191 +<p class=Table>Specifies the name of the GPIO instance. Alphanumeric values 
   4.192 + and underscores are supported. The default is gpio.</td></tr>
   4.193 +
   4.194 +<tr valign="top" class="whs13">
   4.195 +<td width="85px" class="whs16">
   4.196 +<p class=Table>Base Address</td>
   4.197 +<td width="503px" class="whs17">
   4.198 +<p class=Table>Specifies the base address for the device. The minimum boundary 
   4.199 + alignment is 0X80. Supported values are 0X80000000 to 0XFFFFFF80. The 
   4.200 + default is 0x80000000. If other components are included in the platform, 
   4.201 + the allowable values will vary.</td></tr>
   4.202 +
   4.203 +<tr valign="top" class="whs13">
   4.204 +<td colspan="2" rowspan="1" width="588px" class="whs18">
   4.205 +<p class=Table
   4.206 +	style="font-weight: bold;">Port Types</td>
   4.207 +</tr>
   4.208 +
   4.209 +<tr valign="top" class="whs13">
   4.210 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.211 +<p class=Table>Output Ports Only</td>
   4.212 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.213 +<p class=Table>Specifies the transfer mode of PIO ports as output only. 
   4.214 + This option is selected by default.</td></tr>
   4.215 +
   4.216 +<tr valign="top" class="whs13">
   4.217 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.218 +<p class=Table>Input Ports Only</td>
   4.219 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.220 +<p class=Table>Specifies the transfer mode of PIO ports as input only. 
   4.221 + This option is deselected by default.</td></tr>
   4.222 +
   4.223 +<tr valign="top" class="whs13">
   4.224 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.225 +<p class=Table>Tristate Ports</td>
   4.226 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.227 +<p class=Table>Specifies the transfer mode of PIO ports as tristate only. 
   4.228 + This option is deselected by default.</td></tr>
   4.229 +
   4.230 +<tr valign="top" class="whs13">
   4.231 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.232 +<p class=Table>Both Input and Output</td>
   4.233 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.234 +<p class=Table>Specifies the transfer mode of PIO ports as both input and 
   4.235 + output. This option is deselected by default.</td></tr>
   4.236 +
   4.237 +<tr valign="top" class="whs13">
   4.238 +<td colspan="2" rowspan="1" width="588px" class="whs18">
   4.239 +<p class=Table
   4.240 +	style="font-weight: bold;">Port Width</td>
   4.241 +</tr>
   4.242 +
   4.243 +<tr valign="top" class="whs13">
   4.244 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.245 +<p class=Table>Data Width</td>
   4.246 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.247 +<p class=Table>Specifies the width of the I/O port, in bits. Supported 
   4.248 + values are 1 to 32. The default is 1.</td></tr>
   4.249 +
   4.250 +<tr valign="top" class="whs13">
   4.251 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.252 +<p class=Table>Input Width</td>
   4.253 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.254 +<p class=Table>Specifies the input data bus width for an independent input/output 
   4.255 + GPIO, in bits. Supported values are 1 to 32. The default is 1.</td></tr>
   4.256 +
   4.257 +<tr valign="top" class="whs13">
   4.258 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.259 +<p class=Table>Output Width</td>
   4.260 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.261 +<p class=Table>Specifies the output data bus width for an independent input/output 
   4.262 + GPIO, in bits. Supported values are 1 to 32. The default is 1.</td></tr>
   4.263 +
   4.264 +<tr valign="top" class="whs13">
   4.265 +<td colspan="2" rowspan="1" width="588px" class="whs21">
   4.266 +<p class=Table
   4.267 +	style="font-weight: bold;">IRQ Mode</td>
   4.268 +</tr>
   4.269 +
   4.270 +<tr valign="top" class="whs13">
   4.271 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.272 +<p class=Table>IRQ Mode</td>
   4.273 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.274 +<p class=Table>Provides IRQ signal output when a specified event occurs 
   4.275 + on input ports. This option is deselected by default.</td></tr>
   4.276 +
   4.277 +<tr valign="top" class="whs13">
   4.278 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.279 +<p class=Table>Level</td>
   4.280 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.281 +<p class=Table>Generates an IRQ whenever a specific input is high and interrupts 
   4.282 + have been enabled for that input in the IRQ-MASK register. This option 
   4.283 + is deselected by default.</td></tr>
   4.284 +
   4.285 +<tr valign="top" class="whs13">
   4.286 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.287 +<p class=Table>Edge</td>
   4.288 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.289 +<p class=Table>Generates an IRQ whenever a specific bit in the edge capture 
   4.290 + register is high and interrupts have been enabled for that bit in the 
   4.291 + IRQ-MASK register. This option is selected by default.</td></tr>
   4.292 +
   4.293 +<tr valign="top" class="whs13">
   4.294 +<td colspan="2" rowspan="1" width="588px" class="whs18">
   4.295 +<p class=Table
   4.296 +	style="font-weight: bold;">Edge Response</td>
   4.297 +</tr>
   4.298 +
   4.299 +<tr valign="top" class="whs13">
   4.300 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.301 +<p class=Table>Either Edge</td>
   4.302 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.303 +<p class=Table>Generates an IRQ on either low-to-high or high-to-low transitions. 
   4.304 + This option is deselected by default.</td></tr>
   4.305 +
   4.306 +<tr valign="top" class="whs13">
   4.307 +<td colspan="1" rowspan="1" width="85px" class="whs19">
   4.308 +<p class=Table>Positive Edge</td>
   4.309 +<td colspan="1" rowspan="1" width="503px" class="whs20">
   4.310 +<p class=Table>Generates an IRQ on low-to-high transitions. This option 
   4.311 + is selected by default.</td></tr>
   4.312 +
   4.313 +<tr valign="top" class="whs13">
   4.314 +<td colspan="1" rowspan="1" width="85px" class="whs16">
   4.315 +<p class=Table>Negative Edge</td>
   4.316 +<td colspan="1" rowspan="1" width="503px" class="whs17">
   4.317 +<p class=Table>Generates an IRQ on high-to-low transitions. This option 
   4.318 + is deselected by default.</td></tr>
   4.319 +</table>
   4.320 +
   4.321 +&nbsp; 
   4.322 +
   4.323 +<p><span style="font-weight: bold;"><B>Note</B></span>: If the data sheet fails 
   4.324 + to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs22"> on the Available Components toolbar, and 
   4.325 + then click the note button.</p>
   4.326 +
   4.327 +<script type="text/javascript" language="JavaScript">
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   7.247 +       margin-top:1px;  }
   7.248 +ul ul { 
   7.249 +       margin-top:1px;  }
   7.250 +ul ol { 
   7.251 +       margin-top:1px;  }
     8.1 Binary file document/qm_icon.jpg has changed
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/drivers/device/LCD.c	Fri Aug 13 10:41:29 2010 +0100
     9.3 @@ -0,0 +1,241 @@
     9.4 +/****************************************************************************
     9.5 +**
     9.6 +**  Name: LCD.c
     9.7 +**
     9.8 +**  Description:
     9.9 +**       Implements functions for manipulating a 
    9.10 +**       dot-matrix LCD
    9.11 +**
    9.12 +**  $Revision: $
    9.13 +**
    9.14 +** Disclaimer:
    9.15 +**
    9.16 +**   This source code is intended as a design reference which
    9.17 +**   illustrates how these types of functions can be implemented.  It
    9.18 +**   is the user's responsibility to verify their design for
    9.19 +**   consistency and functionality through the use of formal
    9.20 +**   verification methods.  Lattice Semiconductor provides no warranty
    9.21 +**   regarding the use or functionality of this code.
    9.22 +**
    9.23 +** --------------------------------------------------------------------
    9.24 +**
    9.25 +**                     Lattice Semiconductor Corporation
    9.26 +**                     5555 NE Moore Court
    9.27 +**                     Hillsboro, OR 97214
    9.28 +**                     U.S.A
    9.29 +**
    9.30 +**                     TEL: 1-800-Lattice (USA and Canada)
    9.31 +**                          (503)268-8001 (other locations)
    9.32 +**
    9.33 +**                     web:   http://www.latticesemi.com
    9.34 +**                     email: techsupport@latticesemi.com
    9.35 +**
    9.36 +** --------------------------------------------------------------------------
    9.37 +**
    9.38 +**  Change History (Latest changes on top)
    9.39 +**
    9.40 +**  Ver    Date        Description
    9.41 +** --------------------------------------------------------------------------
    9.42 +**
    9.43 +**  3.0   Mar-25-2008  Added Header
    9.44 +**
    9.45 +**---------------------------------------------------------------------------
    9.46 +*****************************************************************************/
    9.47 +
    9.48 +#include "LCD.h"
    9.49 +#include "MicoUtils.h"
    9.50 +
    9.51 +void LCD_WriteData(volatile unsigned int *pAddress, unsigned int data)
    9.52 +{
    9.53 +	unsigned int iData = data;
    9.54 +
    9.55 +	/* first output the data to write */
    9.56 +	*pAddress = iData;
    9.57 +
    9.58 +	/* strobe enable while maintaining data */
    9.59 +	iData |= 0x400;
    9.60 +	*pAddress = iData;
    9.61 +	
    9.62 +	/* remove strobe while maintaining data */
    9.63 +	iData &= ~0x400;
    9.64 +	*pAddress = iData;
    9.65 +
    9.66 +	/* all done */
    9.67 +	return;
    9.68 +}
    9.69 +
    9.70 +
    9.71 +void LCD_DisplayOnOff(MicoGPIOCtx_t *ctx, unsigned int bOn)
    9.72 +{
    9.73 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
    9.74 +	unsigned int value;
    9.75 +
    9.76 +	if(bOn == 0)	/* turn display off */
    9.77 +		value = 0x8;
    9.78 +	else			/* turn display on */
    9.79 +		value = 0xc;
    9.80 +
    9.81 +	LCD_WriteData(pAddress, value);
    9.82 +	MicoSleepMilliSecs(10);
    9.83 +}
    9.84 +
    9.85 +
    9.86 +void LCD_CursorOnOff(MicoGPIOCtx_t *ctx, unsigned int bOn)
    9.87 +{
    9.88 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
    9.89 +	/* cursor on-off control is valid only if the display is turned on */
    9.90 +	unsigned int iValue;
    9.91 +	
    9.92 +	if(bOn == 0)
    9.93 +		iValue = 0x0c;
    9.94 +	else
    9.95 +		iValue = 0x0e;
    9.96 +
    9.97 +	LCD_WriteData(pAddress, iValue);
    9.98 +	MicoSleepMilliSecs(10);
    9.99 +
   9.100 +}
   9.101 +
   9.102 +
   9.103 +void LCD_BlinkOnOff(MicoGPIOCtx_t *ctx, unsigned int bOn)
   9.104 +{
   9.105 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.106 +	/* character-blink on/off is valid only if the display is turned on */
   9.107 +	unsigned int iValue;
   9.108 +
   9.109 +	if(bOn == 0)
   9.110 +		iValue = 0xc;
   9.111 +	else
   9.112 +		iValue = 0xd;
   9.113 +
   9.114 +	LCD_WriteData(pAddress, iValue);
   9.115 +	MicoSleepMilliSecs(10);
   9.116 +}
   9.117 +
   9.118 +
   9.119 +/* clears LCD display */
   9.120 +void LCD_ClearDisplay(MicoGPIOCtx_t *ctx)
   9.121 +{
   9.122 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.123 +	LCD_WriteData(pAddress, 0x1);
   9.124 +	MicoSleepMilliSecs(10);
   9.125 +}
   9.126 +
   9.127 +
   9.128 +/* sets LCD function (#lines for the display, with 8-bit interface */
   9.129 +void LCD_SetFunction(MicoGPIOCtx_t *ctx, unsigned int iNumLines)
   9.130 +{
   9.131 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.132 +	unsigned int value;
   9.133 +
   9.134 +	/* always sets an 8-bit interface */
   9.135 +	if(iNumLines == 2)
   9.136 +		value = 0x38;
   9.137 +	else
   9.138 +		value = 0x00;
   9.139 +
   9.140 +	LCD_WriteData(pAddress, value);
   9.141 +	MicoSleepMilliSecs(10);
   9.142 +}
   9.143 +
   9.144 +/* sets cursor-move mode */
   9.145 +void LCD_SetCursorMoveMode(MicoGPIOCtx_t *ctx, unsigned int bIncrement)
   9.146 +{
   9.147 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.148 +	unsigned int value;
   9.149 +	if(bIncrement != 0)
   9.150 +		value = 0x6;
   9.151 +	else
   9.152 +		value = 0x4;
   9.153 +	LCD_WriteData(pAddress, value);
   9.154 +	MicoSleepMilliSecs(10);
   9.155 +}
   9.156 +
   9.157 +
   9.158 +/* shifts display to left (!= 0) or right (== 0) */
   9.159 +void LCD_ShiftDisplay(MicoGPIOCtx_t *ctx, unsigned int bLeft)
   9.160 +{
   9.161 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.162 +	unsigned int value;
   9.163 +	if(bLeft == 0)	/* shift to right */
   9.164 +		value = 0x18;
   9.165 +	else 			/* shift to left */
   9.166 +		value = 0x1c;
   9.167 +	LCD_WriteData(pAddress, value);
   9.168 +	MicoSleepMilliSecs(10);
   9.169 +}
   9.170 +
   9.171 +
   9.172 +/* shifts cursor to left (!= 0) or right (== 0) */
   9.173 +void LCD_ShiftCursor(MicoGPIOCtx_t *ctx, unsigned int bLeft)
   9.174 +{
   9.175 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.176 +	unsigned int value;
   9.177 +	if(bLeft == 0)	/* shift to right */
   9.178 +		value = 0x10;
   9.179 +	else			/* shift to left */
   9.180 +		value = 0x14;
   9.181 +	LCD_WriteData(pAddress, value);
   9.182 +	MicoSleepMilliSecs(10);
   9.183 +}
   9.184 +
   9.185 +
   9.186 +void LCD_WriteChar(MicoGPIOCtx_t *ctx, unsigned char character)
   9.187 +{
   9.188 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.189 +	unsigned int value = (unsigned int)character;
   9.190 +	value |= 0x200;
   9.191 +	LCD_WriteData(pAddress, value);
   9.192 +	MicoSleepMilliSecs(10);
   9.193 +}
   9.194 +
   9.195 +
   9.196 +void LCD_SetCursorPos(MicoGPIOCtx_t *ctx, unsigned int iLine, unsigned int iCol)
   9.197 +{
   9.198 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.199 +	unsigned int value;
   9.200 +	if(iLine == 0)	/* first line */
   9.201 +		value = 0x80;
   9.202 +	else			/* second line */
   9.203 +		value = 0xc0;
   9.204 +
   9.205 +	value += iCol;
   9.206 +
   9.207 +	LCD_WriteData(pAddress, value);
   9.208 +	MicoSleepMilliSecs(10);
   9.209 +}
   9.210 +
   9.211 +
   9.212 +void LCD_Init(MicoGPIOCtx_t *ctx, unsigned int iLines)
   9.213 +{
   9.214 +	volatile unsigned int *pAddress = (volatile unsigned int *)(ctx->base);
   9.215 +	/* - wait for power-stabilization */
   9.216 +	MicoSleepMilliSecs(40);
   9.217 +
   9.218 +	*pAddress = 0x0;
   9.219 +
   9.220 +	/* - set data-width (8 bits) and lines in display (2) */
   9.221 +	LCD_SetFunction(ctx, iLines);
   9.222 +	LCD_SetFunction(ctx, iLines);
   9.223 +	LCD_SetFunction(ctx, iLines);
   9.224 +
   9.225 +
   9.226 +	/* turn off the display */
   9.227 +	LCD_DisplayOnOff(ctx, 0);
   9.228 +
   9.229 +	/* - clear display */
   9.230 +	LCD_ClearDisplay(ctx);
   9.231 +			
   9.232 +	/* turn-on the display */
   9.233 +	LCD_DisplayOnOff(ctx, 1);
   9.234 +
   9.235 +	/* turn on the blinking of the cursor-position */
   9.236 +	LCD_BlinkOnOff(ctx, 0);
   9.237 +
   9.238 +	/* set cursor move-mode to increment */
   9.239 +	LCD_SetCursorMoveMode(ctx, 1);
   9.240 +
   9.241 +	/* all done */
   9.242 +	return;
   9.243 +}
   9.244 +
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/drivers/device/LCD.h	Fri Aug 13 10:41:29 2010 +0100
    10.3 @@ -0,0 +1,113 @@
    10.4 +/****************************************************************************
    10.5 +**
    10.6 +**  Name: LCD.h
    10.7 +**
    10.8 +**  Description:
    10.9 +**        Declares user-callable functions for manipulating
   10.10 +**        dot-matrix LCD displays
   10.11 +**
   10.12 +**  $Revision: $
   10.13 +**
   10.14 +** Disclaimer:
   10.15 +**
   10.16 +**   This source code is intended as a design reference which
   10.17 +**   illustrates how these types of functions can be implemented.  It
   10.18 +**   is the user's responsibility to verify their design for
   10.19 +**   consistency and functionality through the use of formal
   10.20 +**   verification methods.  Lattice Semiconductor provides no warranty
   10.21 +**   regarding the use or functionality of this code.
   10.22 +**
   10.23 +** --------------------------------------------------------------------
   10.24 +**
   10.25 +**                     Lattice Semiconductor Corporation
   10.26 +**                     5555 NE Moore Court
   10.27 +**                     Hillsboro, OR 97214
   10.28 +**                     U.S.A
   10.29 +**
   10.30 +**                     TEL: 1-800-Lattice (USA and Canada)
   10.31 +**                          (503)268-8001 (other locations)
   10.32 +**
   10.33 +**                     web:   http://www.latticesemi.com
   10.34 +**                     email: techsupport@latticesemi.com
   10.35 +**
   10.36 +** --------------------------------------------------------------------------
   10.37 +**
   10.38 +**  Change History (Latest changes on top)
   10.39 +**
   10.40 +**  Ver    Date        Description
   10.41 +** --------------------------------------------------------------------------
   10.42 +**
   10.43 +**  3.0   Mar-25-2008  Added Header
   10.44 +**
   10.45 +**---------------------------------------------------------------------------
   10.46 +*****************************************************************************/
   10.47 +
   10.48 +#ifndef LCD_H_
   10.49 +#define LCD_H_
   10.50 +
   10.51 +#include "DDStructs.h"
   10.52 +
   10.53 +#ifdef __cplusplus
   10.54 +extern "C" {
   10.55 +#endif /* __cplusplus */
   10.56 +
   10.57 +
   10.58 +/* for direct read/write to the LCD */
   10.59 +void LCD_WriteData(volatile unsigned int * pAddress, unsigned int data);
   10.60 +
   10.61 +
   10.62 +/* turns display on/off */
   10.63 +void LCD_DisplayOnOff(MicoGPIOCtx_t *pLCD, unsigned int bOn);
   10.64 +
   10.65 +
   10.66 +/* turns cursor on/off */
   10.67 +void LCD_CursorOnOff(MicoGPIOCtx_t *pLCD, unsigned int bOn);
   10.68 +
   10.69 +
   10.70 +/* turns blinking on/off */
   10.71 +void LCD_BlinkOnOff(MicoGPIOCtx_t *pLCD, unsigned int bOn);
   10.72 +
   10.73 +
   10.74 +/* clears display */
   10.75 +void LCD_ClearDisplay(MicoGPIOCtx_t *pLCD);
   10.76 +
   10.77 +
   10.78 +/* sets function */
   10.79 +void LCD_SetFunction(MicoGPIOCtx_t *pLCD, unsigned int iNumLines);
   10.80 +
   10.81 +
   10.82 +/* sets cursor move mode */
   10.83 +void LCD_SetCursorMoveMode(MicoGPIOCtx_t *pLCD, unsigned int bIncrement);
   10.84 +
   10.85 +
   10.86 +/* shifts display left or right by 1 */
   10.87 +void LCD_ShiftDisplay(MicoGPIOCtx_t *pLCD, unsigned int bLeft);
   10.88 +
   10.89 +
   10.90 +/* shifts cursor left or right by 1 */
   10.91 +void LCD_ShiftCursor(MicoGPIOCtx_t *pLCD, unsigned int bLeft);
   10.92 +
   10.93 +
   10.94 +/* writes a character to the display */
   10.95 +void LCD_WriteChar(MicoGPIOCtx_t *pLCD, unsigned char character);
   10.96 +
   10.97 +
   10.98 +/* sets write-position (i.e. cursor position) */
   10.99 +void LCD_SetCursorPos(MicoGPIOCtx_t *pLCD, unsigned int iLine, unsigned int iCol);
  10.100 +
  10.101 +
  10.102 +/* Initializes the LCD */
  10.103 +void LCD_Init(MicoGPIOCtx_t *pLCD, unsigned int iLines);
  10.104 +
  10.105 +
  10.106 +/* writes a line to the LCD at the cursor position */
  10.107 +void LCD_WriteLine(MicoGPIOCtx_t *pLCD, const char *pLine);
  10.108 +
  10.109 +
  10.110 +#ifdef __cplusplus
  10.111 +}
  10.112 +#endif /* __cplusplus */
  10.113 +
  10.114 +
  10.115 +#endif /*LCD_H_*/
  10.116 +
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/drivers/device/MicoGPIO.c	Fri Aug 13 10:41:29 2010 +0100
    11.3 @@ -0,0 +1,67 @@
    11.4 +/****************************************************************************
    11.5 +**
    11.6 +**  Name: MicoGPIO.c
    11.7 +**
    11.8 +**  Description:
    11.9 +**     Implements GPIO functions:
   11.10 +**
   11.11 +**        MicoGPIOInit : GPIO initialization funciton called by LatticeDDInit
   11.12 +**                 (user-callable)
   11.13 +**        
   11.14 +**
   11.15 +**  $Revision: $
   11.16 +**
   11.17 +** Disclaimer:
   11.18 +**
   11.19 +**   This source code is intended as a design reference which
   11.20 +**   illustrates how these types of functions can be implemented.  It
   11.21 +**   is the user's responsibility to verify their design for
   11.22 +**   consistency and functionality through the use of formal
   11.23 +**   verification methods.  Lattice Semiconductor provides no warranty
   11.24 +**   regarding the use or functionality of this code.
   11.25 +**
   11.26 +** --------------------------------------------------------------------
   11.27 +**
   11.28 +**                     Lattice Semiconductor Corporation
   11.29 +**                     5555 NE Moore Court
   11.30 +**                     Hillsboro, OR 97214
   11.31 +**                     U.S.A
   11.32 +**
   11.33 +**                     TEL: 1-800-Lattice (USA and Canada)
   11.34 +**                          (503)268-8001 (other locations)
   11.35 +**
   11.36 +**                     web:   http://www.latticesemi.com
   11.37 +**                     email: techsupport@latticesemi.com
   11.38 +**
   11.39 +** --------------------------------------------------------------------------
   11.40 +**
   11.41 +**  Change History (Latest changes on top)
   11.42 +**
   11.43 +**  Ver    Date        Description
   11.44 +** --------------------------------------------------------------------------
   11.45 +**
   11.46 +**  3.0   Mar-25-2008  Added Header
   11.47 +**
   11.48 +**---------------------------------------------------------------------------
   11.49 +*****************************************************************************/
   11.50 +
   11.51 +#include "MicoGPIO.h"
   11.52 +#include "MicoGPIOService.h"
   11.53 +#include "MicoMacros.h"
   11.54 +#include "LookupServices.h"
   11.55 +
   11.56 +
   11.57 +/******************************************************************************
   11.58 + * Initializes a gpio                                                         *
   11.59 + ******************************************************************************/
   11.60 +void MicoGPIOInit( MicoGPIOCtx_t *ctx )
   11.61 +{
   11.62 +    ctx->lookupReg.name = ctx->name;
   11.63 +    ctx->lookupReg.deviceType = "GPIODevice";
   11.64 +    ctx->lookupReg.priv = ctx;
   11.65 +
   11.66 +    MicoRegisterDevice( &(ctx->lookupReg) );
   11.67 +    /* all done */
   11.68 +    return;
   11.69 +}
   11.70 +
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/drivers/device/MicoGPIO.h	Fri Aug 13 10:41:29 2010 +0100
    12.3 @@ -0,0 +1,161 @@
    12.4 +/****************************************************************************
    12.5 +**
    12.6 +**  Name: MicoGPIO.h 
    12.7 +**
    12.8 +**  Description:
    12.9 +**       Declares GPIO register structure and
   12.10 +**       macros/functions for manipulating GPIO
   12.11 +**
   12.12 +**  $Revision: $
   12.13 +**
   12.14 +** Disclaimer:
   12.15 +**
   12.16 +**   This source code is intended as a design reference which
   12.17 +**   illustrates how these types of functions can be implemented.  It
   12.18 +**   is the user's responsibility to verify their design for
   12.19 +**   consistency and functionality through the use of formal
   12.20 +**   verification methods.  Lattice Semiconductor provides no warranty
   12.21 +**   regarding the use or functionality of this code.
   12.22 +**
   12.23 +** --------------------------------------------------------------------
   12.24 +**
   12.25 +**                     Lattice Semiconductor Corporation
   12.26 +**                     5555 NE Moore Court
   12.27 +**                     Hillsboro, OR 97214
   12.28 +**                     U.S.A
   12.29 +**
   12.30 +**                     TEL: 1-800-Lattice (USA and Canada)
   12.31 +**                          (503)268-8001 (other locations)
   12.32 +**
   12.33 +**                     web:   http://www.latticesemi.com
   12.34 +**                     email: techsupport@latticesemi.com
   12.35 +**
   12.36 +** --------------------------------------------------------------------------
   12.37 +**
   12.38 +**  Change History (Latest changes on top)
   12.39 +**
   12.40 +**  Ver    Date        Description
   12.41 +** --------------------------------------------------------------------------
   12.42 +**
   12.43 +**  3.1   Oct-23-2008  Updated macros to provide for
   12.44 +**                     reading of the interrupt-mask register
   12.45 +**                     and writing to the edge-capture register
   12.46 +**                     Updated comments in the GPIO register
   12.47 +**                     structure definition
   12.48 +**  3.0   Mar-25-2008  Added Header
   12.49 +**
   12.50 +**
   12.51 +**---------------------------------------------------------------------------
   12.52 +*****************************************************************************/
   12.53 +
   12.54 +#ifndef MICO32_MICOGPIO_HEADER_FILE
   12.55 +#define MICO32_MICOGPIO_HEADER_FILE
   12.56 +
   12.57 +#include "MicoTypes.h"
   12.58 +#include "DDStructs.h"
   12.59 +
   12.60 +/****************************************************************************
   12.61 + * Mico-GPIO driver does not provide any specific user-routine other than   *
   12.62 + * linking it to GPIO services for lookup capability.                       *
   12.63 + *--------------------------------------------------------------------------*
   12.64 + * Mico GPIOs must be located in a non-cached region to use this driver     *
   12.65 + ****************************************************************************/
   12.66 +
   12.67 +
   12.68 +#ifdef __cplusplus
   12.69 +extern "C"
   12.70 +{
   12.71 +#endif /* __cplusplus */
   12.72 +
   12.73 +    /*
   12.74 +     *****************************************
   12.75 +     *****************************************
   12.76 +              GPIO REGISTER MAPPING
   12.77 +     *****************************************
   12.78 +     *****************************************
   12.79 +     */
   12.80 +    typedef struct st_MicoGPIO_t{
   12.81 +        volatile unsigned int data;         /* R/W: 
   12.82 +                                                  R for in-only GPIO,
   12.83 +                                                  W for out-only GPIO,
   12.84 +                                                  R/W for tristates  */
   12.85 +        volatile unsigned int tristate;     /* R/W: 
   12.86 +                                                  tristate enable reg for 
   12.87 +                                                  tristate GPIOs */
   12.88 +        volatile unsigned int irqMask;      /* R/W:
   12.89 +                                                  irq mask for interrupt-
   12.90 +                                                  enabled GPIOs */
   12.91 +        volatile unsigned int edgeCapture;  /* R/W:
   12.92 +                                                  applicable to GPIOs with
   12.93 +                                                  edge-capture ability */
   12.94 +    }MicoGPIO_t;
   12.95 +
   12.96 +
   12.97 +
   12.98 +    /*
   12.99 +     ********************************************
  12.100 +     ********************************************
  12.101 +         MACROS FOR ACCESSING GPIO REGISTERS
  12.102 +     ********************************************
  12.103 +     NOTE: FOR THE MACROS, THE FOLLOWING RULES
  12.104 +           APPLY:
  12.105 +           X is pointer to a valid MicoGPIOCtx_t structure
  12.106 +           Y is unsigned int variable
  12.107 +     */
  12.108 +
  12.109 +
  12.110 +    /* reads data register */
  12.111 +    #define MICO_GPIO_READ_DATA(X,Y)    \
  12.112 +        (Y)=((volatile MicoGPIO_t *)((X)->base))->data
  12.113 +
  12.114 +
  12.115 +    /* writes data-register */
  12.116 +    #define MICO_GPIO_WRITE_DATA(X,Y)   \
  12.117 +        ((volatile MicoGPIO_t *)((X)->base))->data=(Y)
  12.118 +
  12.119 +
  12.120 +    /* reads tristate register */
  12.121 +    #define MICO_GPIO_READ_TRISTATE(X,Y)   \
  12.122 +        (Y) = ((volatile MicoGPIO_t *)((X)->base))->tristate
  12.123 +
  12.124 +
  12.125 +    /* writes tristate register */
  12.126 +    #define MICO_GPIO_WRITE_TRISTATE(X,Y)  \
  12.127 +        ((volatile MicoGPIO_t *)((X)->base))->tristate = (Y)
  12.128 +
  12.129 +
  12.130 +    /* reads irq-mask register */
  12.131 +    #define MICO_GPIO_READ_IRQ_MASK(X,Y)  \
  12.132 +        (Y) = ((volatile MicoGPIO_t *)((X)->base))->irqMask
  12.133 +
  12.134 +
  12.135 +    /* writes irq-mask register */
  12.136 +    #define MICO_GPIO_WRITE_IRQ_MASK(X,Y)  \
  12.137 +        ((volatile MicoGPIO_t *)((X)->base))->irqMask = (Y)
  12.138 +
  12.139 +
  12.140 +    /* reads edge-capture register */
  12.141 +    #define MICO_GPIO_READ_EDGE_CAPTURE(X,Y)  \
  12.142 +        (Y) = ((volatile MicoGPIO_t *)((X)->base))->edgeCapture
  12.143 +
  12.144 +
  12.145 +    /* writes edge-capture register */
  12.146 +    #define MICO_GPIO_WRITE_EDGE_CAPTURE(X,Y)  \
  12.147 +        ((volatile MicoGPIO_t *)((X)->base))->edgeCapture = (Y)
  12.148 +
  12.149 +
  12.150 +/******************************************************************************
  12.151 + * functions                                                                  *
  12.152 + ******************************************************************************/
  12.153 +
  12.154 +/* initializes Mico32 GPIO peripheral */
  12.155 +void MicoGPIOInit( MicoGPIOCtx_t *ctx );
  12.156 +
  12.157 +
  12.158 +#ifdef __cplusplus
  12.159 +};
  12.160 +#endif /* __cplusplus */
  12.161 +
  12.162 +
  12.163 +#endif /*MICO32_MICOGPIO_HEADER_FILE */
  12.164 +
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/drivers/peripheral.mk	Fri Aug 13 10:41:29 2010 +0100
    13.3 @@ -0,0 +1,10 @@
    13.4 +#---------------------------------------------------------
    13.5 +# Identify source-paths for this device's driver-sources,
    13.6 +# compiled when building the library
    13.7 +#---------------------------------------------------------
    13.8 +LIBRARY_C_SRCS	+=			MicoGPIO.c		\
    13.9 +					MicoGPIOService.c	\
   13.10 +					LCD.c
   13.11 +
   13.12 +LIBRARY_ASM_SRCS += 
   13.13 +
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/drivers/service/MicoGPIOService.c	Fri Aug 13 10:41:29 2010 +0100
    14.3 @@ -0,0 +1,2 @@
    14.4 +/* NO IMPLEMENTATION, BY DESIGN */
    14.5 +
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/drivers/service/MicoGPIOService.h	Fri Aug 13 10:41:29 2010 +0100
    15.3 @@ -0,0 +1,17 @@
    15.4 +#ifndef MICO32_GPIOSERVICE_HEADER_FILE
    15.5 +#define MICO32_GPIOSERVICE_HEADER_FILE
    15.6 +
    15.7 +
    15.8 +#ifdef __cplusplus
    15.9 +extern "C"
   15.10 +{
   15.11 +#endif /* __cplusplus */
   15.12 +
   15.13 +
   15.14 +
   15.15 +#ifdef __cplusplus
   15.16 +};
   15.17 +#endif /* __cplusplus */
   15.18 +
   15.19 +
   15.20 +#endif /* MICO32_GPIOSERVICE_HEADER_FILE */
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/gpio.xml	Fri Aug 13 10:41:29 2010 +0100
    16.3 @@ -0,0 +1,83 @@
    16.4 +<?xml version="1.0" encoding="UTF-8"?>
    16.5 +<Component Name="gpio" Text="GPIO" Type="IO" Ver="3.1" Help="gpio\document\gpio.htm">
    16.6 +	<MasterSlavePorts>
    16.7 +		<SlavePort Prefix="GPIO" Name="GP I/O Port" Type="DATA,DMAR,DMAW"/>
    16.8 +	</MasterSlavePorts>
    16.9 +	<ClockPort Name="CLK_I" Description="Clock     one"/>
   16.10 +        <ResetPort Name="RST_I" Description="Reset"/>
   16.11 +	<Interrupt Name="IRQ_O" Active="high" IRQ=""/>
   16.12 +	<ExternalPorts>
   16.13 +		<ExternalPort Name="PIO_IN" Type="input" Width="DATA_WIDTH" Condition="INPUT_PORTS_ONLY" />
   16.14 +		<ExternalPort Name="PIO_BOTH_IN" Type="input" Width="INPUT_WIDTH" Condition="BOTH_INPUT_AND_OUTPUT" />
   16.15 +		<ExternalPort Name="PIO_OUT" Type="output" Width="DATA_WIDTH" Condition="OUTPUT_PORTS_ONLY" />
   16.16 +		<ExternalPort Name="PIO_BOTH_OUT" Type="output" Width="OUTPUT_WIDTH" Condition="BOTH_INPUT_AND_OUTPUT" />
   16.17 +		<ExternalPort Name="PIO_IO" Type="inout" Width="DATA_WIDTH" Condition="TRISTATE_PORTS" />
   16.18 +	</ExternalPorts>
   16.19 +        <DeviceDriver InitRoutine="MicoGPIOInit" StructName="MicoGPIOCtx_t">
   16.20 +                <DDInclude Include = "LookupServices.h"/>
   16.21 +                <DDstruct>			
   16.22 +			<DDSElem MemberName = "name" MemberType = "const char*" Type = "Parm" Value = "InstanceName" Format="string"/>
   16.23 +			<DDSElem MemberName = "base" MemberType = "unsigned int" Type = "Parm" Value = "BASE_ADDRESS" />
   16.24 +                        <DDSElem MemberName = "lookupReg" MemberType = "DeviceReg_t" Type="uninitialized" Value=""/>
   16.25 +                        <DDSElem MemberName = "intrLevel" MemberType = "unsigned int" Type = "Interrupt" Value = "IRQ_LEVEL" />
   16.26 +                        <DDSElem MemberName = "output_only" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_PORTS_ONLY" />
   16.27 +                        <DDSElem MemberName = "input_only" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_PORTS_ONLY" />
   16.28 +                        <DDSElem MemberName = "in_and_out" MemberType = "unsigned int" Type = "Parm" Value = "BOTH_INPUT_AND_OUTPUT" />
   16.29 +                        <DDSElem MemberName = "tristate" MemberType = "unsigned int" Type = "Parm" Value = "TRISTATE_PORTS"	/>
   16.30 +                        <DDSElem MemberName = "data_width" MemberType = "unsigned int" Type = "Parm" Value = "DATA_WIDTH" />
   16.31 +                        <DDSElem MemberName = "input_width" MemberType = "unsigned int" Type = "Parm" Value = "INPUT_WIDTH" />
   16.32 +                        <DDSElem MemberName = "output_width" MemberType = "unsigned int" Type = "Parm" Value = "OUTPUT_WIDTH" />
   16.33 +                        <DDSElem MemberName = "intr_enable" MemberType = "unsigned int" Type = "Parm" Value = "IRQ_MODE" />
   16.34 +                        <DDSElem MemberName = "prev" MemberType = "void *" Type = "uninitialized" Value = "" />
   16.35 +                        <DDSElem MemberName = "next" MemberType = "void *" Type = "uninitialized" Value = "" />
   16.36 +                </DDstruct>
   16.37 +        </DeviceDriver>
   16.38 +      <Files>
   16.39 +	    <File Name="../components/gpio/rtl/verilog/gpio.v" />
   16.40 +	    <File Name="../components/gpio/rtl/verilog/tpio.v" />
   16.41 +      </Files>
   16.42 +	<Parms>
   16.43 +		<Parm Name="InstanceName"    Value="gpio"     Type="string" isiname="true" Text="Instance Name"/>
   16.44 +		<Parm Name="BASE_ADDRESS"    Value="0x80000000" Type="Integer" isba="true" Text="Base Address"/>
   16.45 +		<Parm Name="SIZE"            Value="128"    Type="Integer" issize="true" Text="Size" Enable="false"/>
   16.46 +                <Parm Name="ADDRESS_LOCK" Type="Define" Value="undef" Text="Lock Address"/>
   16.47 +		<Parm Name="DISABLE" Type="Define" Value="undef" isuse="true" Text="Disable Component"/>
   16.48 +		<Parm Name="OUTPUT_PORTS_ONLY" Type="define" Value="def" GROUP="XFER_MODE" Text="Output Ports Only" isparm="true" />
   16.49 +		<Parm Name="INPUT_PORTS_ONLY" Type="define" Value="undef" GROUP="XFER_MODE" Text="Input Ports Only" isparm="true"/>
   16.50 +		<Parm Name="TRISTATE_PORTS" Type="define" Value="undef" GROUP="XFER_MODE" Text="Tristate Ports" isparm="true"/>
   16.51 +		<Parm Name="BOTH_INPUT_AND_OUTPUT" Type="define" Value="undef" GROUP="XFER_MODE" Text="Both Input and Output" isparm="true"/>
   16.52 +		<Parm Name="DATA_WIDTH" Type="Integer" ValueRange="1-32" Value="1" NotCondition="BOTH_INPUT_AND_OUTPUT" Text="Data Width" isparm="true"/>
   16.53 +		<Parm Name="INPUT_WIDTH" Type="Integer" ValueRange="1-32" Value="1" Condition="BOTH_INPUT_AND_OUTPUT" Text="Input Width" isparm="true"/>
   16.54 +		<Parm Name="OUTPUT_WIDTH" Type="Integer" ValueRange="1-32" Value="1" Condition="BOTH_INPUT_AND_OUTPUT" Text="Output Width" isparm="true"/>
   16.55 +		<Parm Name="IRQ_MODE" Type="define" Value="undef" Text="IRQ Mode" isparm="true"/>
   16.56 +		<Parm Name="LEVEL" Type="define" Value="undef" GROUP="IMODE" Condition="IRQ_MODE" Text="Level" isparm="true"/>
   16.57 +		<Parm Name="EDGE" Type="define" Value="def" GROUP="IMODE" Condition="IRQ_MODE" Text="Edge" isparm="true"/>
   16.58 +		<Parm Name="EITHER_EDGE_IRQ" Type="define" Value="undef" Group="EMODE" Condition="EDGE" Text="Either Edge" isparm="true"/>
   16.59 +		<Parm Name="POSE_EDGE_IRQ" Type="define" Value="def" Group="EMODE" Condition="EDGE" Text="Postive Edge" isparm="true"/>
   16.60 +		<Parm Name="NEGE_EDGE_IRQ" Type="define" Value="undef" Group="EMODE" Condition="EDGE" Text="Negative Edge" isparm="true"/>
   16.61 +	</Parms>
   16.62 +      <GUIS Columns="2" Help="component_help\lm32.htm" Name="GPIO">
   16.63 +            <GUI Widget="Text" Span="1" Name="InstanceName" Width="40"/>
   16.64 +            <GUI Widget="Text" Span="1" Name="BASE_ADDRESS"/>
   16.65 +            <GUI Widget="Group" Span="1" Name="XFER_MODE" Text="Port Types" Columns="1"/>
   16.66 +            <GUI Widget="Radio" Span="1" Name="OUTPUT_PORTS_ONLY"/>
   16.67 +            <GUI Widget="Radio" Span="1" Name="INPUT_PORTS_ONLY"/>
   16.68 +            <GUI Widget="Radio" Span="1" Name="TRISTATE_PORTS"/>
   16.69 +            <GUI Widget="Radio" Span="1" Name="BOTH_INPUT_AND_OUTPUT"/>
   16.70 +
   16.71 +            <GUI Widget="Group" Span="1" Text="Port Width" Columns="2"/>
   16.72 +            <GUI Widget="Spinner" Span="1" Name="DATA_WIDTH"/>
   16.73 +            <GUI Widget="Spinner" Span="1" Name="INPUT_WIDTH"/>
   16.74 +            <GUI Widget="Spinner" Span="1" Name="OUTPUT_WIDTH"/>
   16.75 +
   16.76 +            <GUI Widget="Group" Span="1" Name="IRQ_MODE" Text="IRQ Mode" Columns="1"/>
   16.77 +            <GUI Widget="Check" Span="1" Name="IRQ_MODE"/>
   16.78 +            <GUI Widget="Radio" Span="1" Name="LEVEL"/>
   16.79 +            <GUI Widget="Radio" Span="1" Name="EDGE"/>
   16.80 +
   16.81 +            <GUI Widget="Group" Span="1" Text="Edge Response" Columns="1"/>
   16.82 +            <GUI Widget="Radio" Span="1" Name="EITHER_EDGE_IRQ"/>
   16.83 +            <GUI Widget="Radio" Span="1" Name="POSE_EDGE_IRQ"/>
   16.84 +            <GUI Widget="Radio" Span="1" Name="NEGE_EDGE_IRQ"/>
   16.85 +     </GUIS>
   16.86 +</Component>
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/rtl/verilog/gpio.v	Fri Aug 13 10:41:29 2010 +0100
    17.3 @@ -0,0 +1,379 @@
    17.4 +// =============================================================================
    17.5 +//                           COPYRIGHT NOTICE
    17.6 +// Copyright 2004 (c) Lattice Semiconductor Corporation
    17.7 +// ALL RIGHTS RESERVED
    17.8 +// This confidential and proprietary software may be used only as authorised by
    17.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   17.10 +// The entire notice above must be reproduced on all authorized copies and
   17.11 +// copies may only be made to the extent permitted by a licensing agreement from
   17.12 +// Lattice Semiconductor Corporation.
   17.13 +//
   17.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   17.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   17.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   17.17 +// U.S.A                                   email: techsupport@latticesemi.com
   17.18 +// =============================================================================/
   17.19 +//                         FILE DETAILS
   17.20 +// Project          : GPIO for LM32
   17.21 +// File             : gpio.v
   17.22 +// Title            : General Purpose IO Component 
   17.23 +// Dependencies     : system_conf.v
   17.24 +// Description      : Implements the logic to interface general purpuse IO with 
   17.25 +//                    Wishbone bus.
   17.26 +// =============================================================================
   17.27 +//                        REVISION HISTORY
   17.28 +// Version          : 7.0
   17.29 +// Mod. Date        : Jun 27, 2005
   17.30 +// Changes Made     : Initial Creation
   17.31 +//
   17.32 +// Version          : 7.0SP2, 3.0
   17.33 +// Mod. Date        : 20 Nov. 2007
   17.34 +// Changes Made     : Code clean up.
   17.35 +//
   17.36 +// Version          : 3.1
   17.37 +// Mod. Date        : 11 Oct. 2008
   17.38 +// Changes Made     : Update the Edge Capture Register clean method
   17.39 +//                    Make IRQ Mask register readable
   17.40 +// =============================================================================
   17.41 +`ifndef GPIO_V
   17.42 +`define GPIO_V
   17.43 +`timescale 1ns/100 ps
   17.44 +`include "system_conf.v"
   17.45 +module gpio #(parameter DATA_WIDTH = 16,
   17.46 +              parameter INPUT_WIDTH = 16,
   17.47 +              parameter OUTPUT_WIDTH = 16,
   17.48 +              parameter IRQ_MODE = 0,
   17.49 +              parameter LEVEL = 0,
   17.50 +              parameter EDGE = 0,
   17.51 +              parameter POSE_EDGE_IRQ = 0,
   17.52 +              parameter NEGE_EDGE_IRQ = 0,
   17.53 +              parameter EITHER_EDGE_IRQ = 0,
   17.54 +              parameter INPUT_PORTS_ONLY = 1,
   17.55 +              parameter OUTPUT_PORTS_ONLY = 0,
   17.56 +              parameter BOTH_INPUT_AND_OUTPUT = 0,
   17.57 +              parameter TRISTATE_PORTS = 0)
   17.58 +     (
   17.59 +     //system clock and reset
   17.60 +     CLK_I,
   17.61 +     RST_I,
   17.62 +     //wishbone interface signals
   17.63 +     GPIO_ADR_I,
   17.64 +     GPIO_CYC_I,
   17.65 +     GPIO_DAT_I,
   17.66 +     GPIO_SEL_I,
   17.67 +     GPIO_STB_I,
   17.68 +     GPIO_WE_I,
   17.69 +     GPIO_LOCK_I,
   17.70 +     GPIO_CTI_I,
   17.71 +     GPIO_BTE_I,
   17.72 +     GPIO_ACK_O,
   17.73 +     GPIO_RTY_O,
   17.74 +     GPIO_DAT_O,
   17.75 +     GPIO_ERR_O,
   17.76 +     IRQ_O, //bit_or of all IRQs
   17.77 +     //PIO side
   17.78 +     PIO_IN,
   17.79 +     PIO_OUT,
   17.80 +     PIO_IO,
   17.81 +     PIO_BOTH_IN,
   17.82 +     PIO_BOTH_OUT
   17.83 +     );
   17.84 +
   17.85 +//---------------------------------------------------------------------
   17.86 +// inputs
   17.87 +   //
   17.88 +   input                   CLK_I;
   17.89 +   input                   RST_I;
   17.90 +   input [31:0]            GPIO_ADR_I;
   17.91 +   input                   GPIO_CYC_I;
   17.92 +   input [31:0]            GPIO_DAT_I;
   17.93 +   input [3:0]             GPIO_SEL_I;
   17.94 +   input                   GPIO_STB_I;
   17.95 +   input                   GPIO_WE_I;
   17.96 +   input                   GPIO_LOCK_I;
   17.97 +   input [2:0]             GPIO_CTI_I;
   17.98 +   input [1:0]             GPIO_BTE_I;   
   17.99 +   input [DATA_WIDTH-1:0]  PIO_IN;
  17.100 +   input [INPUT_WIDTH-1:0] PIO_BOTH_IN;
  17.101 +//---------------------------------------------------------------------
  17.102 +// outputs
  17.103 +//
  17.104 +   output                    GPIO_ACK_O;
  17.105 +   output                    GPIO_RTY_O;
  17.106 +   output [31:0]             GPIO_DAT_O;
  17.107 +   output                    GPIO_ERR_O;
  17.108 +   output                    IRQ_O;
  17.109 +   output [DATA_WIDTH-1:0]   PIO_OUT;
  17.110 +   output [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT;
  17.111 +//----------------
  17.112 +//inout mode
  17.113 +   inout [DATA_WIDTH-1:0]    PIO_IO;
  17.114 +//----------------
  17.115 +//process
  17.116 +   
  17.117 +   parameter    UDLY     = 1;
  17.118 +   
  17.119 +   wire         ADR_0;
  17.120 +   wire         ADR_4;
  17.121 +   wire         ADR_8;
  17.122 +   wire         ADR_C;
  17.123 +   wire         read_addr_0;   
  17.124 +   wire         read_addr_4;   
  17.125 +   wire         read_addr_8;   
  17.126 +   wire         read_addr_C;   
  17.127 +   wire         GPIO_RTY_O;
  17.128 +   wire         GPIO_ERR_O;
  17.129 +   wire [31:0]  GPIO_DAT_O;
  17.130 +   wire         IRQ_O;
  17.131 +   wire [DATA_WIDTH-1:0]   PIO_OUT;
  17.132 +   wire [OUTPUT_WIDTH-1:0] PIO_BOTH_OUT;
  17.133 +   wire [DATA_WIDTH-1:0]   tpio_out;
  17.134 +   wire                    PIO_DATA_WR_EN;
  17.135 +   wire                    PIO_TRI_WR_EN;
  17.136 +   wire                    IRQ_MASK_WR_EN;
  17.137 +   wire                    EDGE_CAP_WR_EN;
  17.138 +   wire                    PIO_DATA_RE_EN;
  17.139 +   wire                    PIO_TRI_RE_EN;
  17.140 +   wire                    IRQ_MASK_RE_EN;
  17.141 +   wire [DATA_WIDTH-1:0]   IRQ_TRI_TEMP;
  17.142 +   reg [DATA_WIDTH-1:0]    PIO_DATA;
  17.143 +   reg [DATA_WIDTH-1:0]    IRQ_MASK;
  17.144 +   reg [INPUT_WIDTH-1:0]   IRQ_MASK_BOTH;
  17.145 +   reg [DATA_WIDTH-1:0]    IRQ_TEMP;
  17.146 +   reg [INPUT_WIDTH-1:0]   IRQ_TEMP_BOTH;
  17.147 +   reg [DATA_WIDTH-1:0]    EDGE_CAPTURE;
  17.148 +   reg [INPUT_WIDTH-1:0]   EDGE_CAPTURE_BOTH;
  17.149 +   reg [DATA_WIDTH-1:0]    PIO_DATA_DLY;
  17.150 +   reg [INPUT_WIDTH-1:0]   PIO_DATA_DLY_BOTH;
  17.151 +   reg [OUTPUT_WIDTH-1:0]  PIO_DATAO; 
  17.152 +   reg [INPUT_WIDTH-1 :0]  PIO_DATAI;
  17.153 +   reg                     GPIO_ACK_O;
  17.154 +
  17.155 +   assign GPIO_RTY_O = 1'b0;
  17.156 +   assign GPIO_ERR_O = 1'b0;
  17.157 +   assign ADR_0 = (GPIO_ADR_I[3:0] == 4'b0000 ? 1'b1 : 0); // IO Data           
  17.158 +   assign ADR_4 = (GPIO_ADR_I[3:0] == 4'b0100 ? 1'b1 : 0); // Tri-state Control 
  17.159 +   assign ADR_8 = (GPIO_ADR_I[3:0] == 4'b1000 ? 1'b1 : 0); // IRQ Mask          
  17.160 +   assign ADR_C = (GPIO_ADR_I[3:0] == 4'b1100 ? 1'b1 : 0); // Edge Capture      
  17.161 +   assign read_addr_0 =                   (ADR_0 & GPIO_STB_I & ~GPIO_WE_I) ;   
  17.162 +   assign read_addr_4 =                   (ADR_4 & GPIO_STB_I & ~GPIO_WE_I) ;   
  17.163 +   assign read_addr_8 = (IRQ_MODE == 1 && (ADR_8 & GPIO_STB_I & ~GPIO_WE_I));   
  17.164 +   assign read_addr_C = (IRQ_MODE == 1 && (ADR_C & GPIO_STB_I & ~GPIO_WE_I));   
  17.165 +
  17.166 +   always @(posedge CLK_I or posedge RST_I)
  17.167 +     if(RST_I)
  17.168 +       GPIO_ACK_O       <= #UDLY 1'b0;
  17.169 +     else if( GPIO_STB_I && !GPIO_ACK_O)
  17.170 +       GPIO_ACK_O       <= #UDLY 1'b1;
  17.171 +     else
  17.172 +       GPIO_ACK_O       <= #UDLY 1'b0;   
  17.173 +
  17.174 +   generate
  17.175 +      if (INPUT_PORTS_ONLY == 1) begin   
  17.176 +         always @(posedge CLK_I or posedge RST_I)
  17.177 +           if (RST_I)
  17.178 +             PIO_DATA <= #UDLY 0;
  17.179 +           else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111)       
  17.180 +             PIO_DATA <= #UDLY PIO_IN;
  17.181 +         end
  17.182 +   endgenerate
  17.183 + 
  17.184 +   generate   
  17.185 +      if (OUTPUT_PORTS_ONLY == 1) begin
  17.186 +        always @(posedge CLK_I or posedge RST_I)
  17.187 +          if (RST_I)
  17.188 +            PIO_DATA <= #UDLY 0;
  17.189 +          else if (GPIO_STB_I && !GPIO_ACK_O && GPIO_WE_I && ADR_0 == 1'b1 && GPIO_SEL_I == 4'b1111)
  17.190 +            PIO_DATA <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0];   
  17.191 +            
  17.192 +        assign  PIO_OUT = PIO_DATA;
  17.193 +        end
  17.194 +   endgenerate
  17.195 +   
  17.196 +   generate
  17.197 +      if (BOTH_INPUT_AND_OUTPUT == 1) begin   
  17.198 +        always @(posedge CLK_I or posedge RST_I)
  17.199 +          if (RST_I) begin
  17.200 +            PIO_DATAI <= #UDLY 0;
  17.201 +            PIO_DATAO <= #UDLY 0;
  17.202 +          end else if (GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111)
  17.203 +            PIO_DATAI <= #UDLY PIO_BOTH_IN;
  17.204 +          else if (GPIO_STB_I && GPIO_ACK_O && GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111)
  17.205 +            PIO_DATAO <= #UDLY GPIO_DAT_I[OUTPUT_WIDTH-1:0];
  17.206 +               
  17.207 +        assign  PIO_BOTH_OUT = PIO_DATAO[OUTPUT_WIDTH-1:0];
  17.208 +        end
  17.209 +   endgenerate
  17.210 +   
  17.211 +   assign  PIO_DATA_RE_EN = GPIO_STB_I && !GPIO_ACK_O && !GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.212 +   assign  PIO_TRI_RE_EN  = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.213 +   assign  IRQ_MASK_RE_EN = GPIO_STB_I &&  GPIO_ACK_O && !GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.214 +   assign  PIO_DATA_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_0 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.215 +   assign  PIO_TRI_WR_EN  = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_4 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.216 +   assign  IRQ_MASK_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_8 == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.217 +   assign  EDGE_CAP_WR_EN = GPIO_STB_I &&  GPIO_ACK_O &&  GPIO_WE_I && (ADR_C == 1'b1) && GPIO_SEL_I == 4'b1111;
  17.218 +   
  17.219 +   generate
  17.220 +      genvar     ti;
  17.221 +      for (ti = 0 ; ti < DATA_WIDTH; ti = ti + 1)
  17.222 +         begin : tio_inst
  17.223 +            TRI_PIO #(.DATA_WIDTH(DATA_WIDTH),
  17.224 +               .IRQ_MODE(IRQ_MODE),
  17.225 +               .LEVEL(LEVEL),
  17.226 +               .EDGE(EDGE),
  17.227 +               .POSE_EDGE_IRQ(POSE_EDGE_IRQ),
  17.228 +               .NEGE_EDGE_IRQ(NEGE_EDGE_IRQ),
  17.229 +               .EITHER_EDGE_IRQ(EITHER_EDGE_IRQ))
  17.230 +            TP (.CLK_I(CLK_I),
  17.231 +           .RST_I(RST_I),
  17.232 +           .DAT_I(GPIO_DAT_I[ti]),
  17.233 +           .DAT_O(tpio_out[ti]),
  17.234 +           .PIO_IO(PIO_IO[ti]),
  17.235 +           .IRQ_O(IRQ_TRI_TEMP[ti]),
  17.236 +           .PIO_TRI_WR_EN(PIO_TRI_WR_EN),
  17.237 +           .PIO_TRI_RE_EN(PIO_TRI_RE_EN),
  17.238 +           .PIO_DATA_WR_EN(PIO_DATA_WR_EN),
  17.239 +           .PIO_DATA_RE_EN(PIO_DATA_RE_EN),
  17.240 +           .IRQ_MASK_WR_EN(IRQ_MASK_WR_EN),
  17.241 +           .IRQ_MASK_RE_EN(IRQ_MASK_RE_EN),
  17.242 +           .EDGE_CAP_WR_EN(EDGE_CAP_WR_EN));
  17.243 +         end
  17.244 +   endgenerate
  17.245 +
  17.246 +   generate      
  17.247 +     if (INPUT_PORTS_ONLY == 1)
  17.248 +       assign GPIO_DAT_O = read_addr_0 ? PIO_DATA : 
  17.249 +                           read_addr_8 ? IRQ_MASK :
  17.250 +                           read_addr_C ? EDGE_CAPTURE :
  17.251 +                           0;
  17.252 +     else if (BOTH_INPUT_AND_OUTPUT == 1)
  17.253 +       assign GPIO_DAT_O = read_addr_0 ? PIO_DATAI : 
  17.254 +                           read_addr_8 ? IRQ_MASK_BOTH :
  17.255 +                           read_addr_C ? EDGE_CAPTURE_BOTH :
  17.256 +                           0;
  17.257 +     else if (TRISTATE_PORTS == 1)
  17.258 +       assign GPIO_DAT_O = read_addr_0 ? tpio_out : 
  17.259 +                           read_addr_4 ? tpio_out : 
  17.260 +                           read_addr_8 ? tpio_out :
  17.261 +                           read_addr_C ? IRQ_TRI_TEMP :
  17.262 +                           0;
  17.263 +     else
  17.264 +       assign GPIO_DAT_O = 0;
  17.265 +   endgenerate
  17.266 +   
  17.267 +//-----------------------------------------------------------------------------
  17.268 +//-------------------------------IRQ Generation--------------------------------
  17.269 +//-----------------------------------------------------------------------------
  17.270 +   generate
  17.271 +      if (IRQ_MODE == 1) begin
  17.272 +        always @(posedge CLK_I or posedge RST_I)
  17.273 +          if (RST_I) begin
  17.274 +            IRQ_MASK      <= #UDLY 0;
  17.275 +            IRQ_MASK_BOTH <= #UDLY 0;
  17.276 +          end else if (IRQ_MASK_WR_EN) begin
  17.277 +            IRQ_MASK      <= #UDLY GPIO_DAT_I[DATA_WIDTH-1:0];   
  17.278 +            IRQ_MASK_BOTH <= #UDLY GPIO_DAT_I[INPUT_WIDTH-1:0];   
  17.279 +          end
  17.280 +        end
  17.281 +   endgenerate
  17.282 +
  17.283 +   generate 
  17.284 +      //--------------------------------
  17.285 +      //--INPUT_PORTS_ONLY MODE IRQ
  17.286 +      //--------------------------------
  17.287 +      if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && LEVEL == 1) begin   
  17.288 +         //level mode IRQ
  17.289 +         always @(posedge CLK_I or posedge RST_I)
  17.290 +           if (RST_I)
  17.291 +             IRQ_TEMP <= #UDLY 0;
  17.292 +           else if (IRQ_MASK_WR_EN)
  17.293 +             IRQ_TEMP <= #UDLY IRQ_TEMP & GPIO_DAT_I[DATA_WIDTH-1:0];
  17.294 +              else
  17.295 +             IRQ_TEMP <= #UDLY PIO_IN & IRQ_MASK;//bit-and   
  17.296 +         assign   IRQ_O = |IRQ_TEMP;
  17.297 +      end else if (IRQ_MODE == 1 && INPUT_PORTS_ONLY == 1 && EDGE == 1) begin   
  17.298 +         always @(posedge CLK_I or posedge RST_I)
  17.299 +           if (RST_I)
  17.300 +             PIO_DATA_DLY <= #UDLY 0;
  17.301 +           else
  17.302 +             PIO_DATA_DLY <= PIO_IN;
  17.303 +
  17.304 +         // edge-capture register bits are treated as individual bits.
  17.305 +         genvar i;
  17.306 +         for( i = 0; i < DATA_WIDTH; i = i + 1)
  17.307 +         begin
  17.308 +             always @(posedge CLK_I or posedge RST_I)
  17.309 +                 if (RST_I)
  17.310 +                   EDGE_CAPTURE[i] <= #UDLY 0;
  17.311 +                 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (POSE_EDGE_IRQ == 1))
  17.312 +                   EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  17.313 +                 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (NEGE_EDGE_IRQ == 1))
  17.314 +                   EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  17.315 +                 else if (|(PIO_IN[i] & ~PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  17.316 +                   EDGE_CAPTURE[i] <= #UDLY PIO_IN[i] & ~PIO_DATA_DLY[i];
  17.317 +                 else if (|(~PIO_IN[i] & PIO_DATA_DLY[i]) && (EITHER_EDGE_IRQ == 1))
  17.318 +                   EDGE_CAPTURE[i] <= #UDLY ~PIO_IN[i] & PIO_DATA_DLY[i];
  17.319 +                 else if ( (~IRQ_MASK[i]) & GPIO_DAT_I[i] & IRQ_MASK_WR_EN )
  17.320 +                   // interrupt mask is being set, so clear edge-capture
  17.321 +                   EDGE_CAPTURE[i] <= #UDLY 0;
  17.322 +                 else if (EDGE_CAP_WR_EN)
  17.323 +                   // user's writing to the edge register, so update edge capture
  17.324 +                   // register
  17.325 +                   EDGE_CAPTURE[i] <= #UDLY EDGE_CAPTURE[i] & GPIO_DAT_I[i];
  17.326 +         end
  17.327 +         assign  IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
  17.328 +
  17.329 +     //----------------------------------
  17.330 +     //--BOTH_INPUT_AND_OUTPUT MODE IRQ
  17.331 +     //----------------------------------
  17.332 +     end else if  (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && LEVEL == 1) begin
  17.333 +         always @(posedge CLK_I or posedge RST_I)
  17.334 +            if (RST_I)
  17.335 +              IRQ_TEMP_BOTH <= #UDLY 0;
  17.336 +            else if (IRQ_MASK_WR_EN)
  17.337 +              IRQ_TEMP_BOTH <= #UDLY IRQ_TEMP_BOTH & GPIO_DAT_I[INPUT_WIDTH-1:0];   
  17.338 +            else 
  17.339 +              IRQ_TEMP_BOTH <= #UDLY PIO_BOTH_IN & IRQ_MASK_BOTH;   
  17.340 +         assign   IRQ_O = |IRQ_TEMP_BOTH;
  17.341 +
  17.342 +     //edge mode IRQ
  17.343 +     end else if  (IRQ_MODE == 1 && BOTH_INPUT_AND_OUTPUT == 1 && EDGE == 1) begin   
  17.344 +         always @(posedge CLK_I or posedge RST_I)
  17.345 +           if (RST_I)
  17.346 +             PIO_DATA_DLY_BOTH <= #UDLY 0;
  17.347 +           else
  17.348 +             PIO_DATA_DLY_BOTH <= PIO_BOTH_IN;
  17.349 +
  17.350 +         // edge-capture register bits are treated as individual bits.
  17.351 +         genvar i_both;
  17.352 +         for( i_both = 0; i_both < INPUT_WIDTH; i_both = i_both + 1)
  17.353 +         begin
  17.354 +         always @(posedge CLK_I or posedge RST_I)
  17.355 +           if (RST_I)
  17.356 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  17.357 +           else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && POSE_EDGE_IRQ == 1)
  17.358 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  17.359 +           else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) &&  NEGE_EDGE_IRQ == 1)
  17.360 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  17.361 +           else if (|(PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  17.362 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY PIO_BOTH_IN[i_both] & ~PIO_DATA_DLY_BOTH[i_both];
  17.363 +           else if (|(~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both]) && EITHER_EDGE_IRQ == 1)
  17.364 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY ~PIO_BOTH_IN[i_both] & PIO_DATA_DLY_BOTH[i_both];
  17.365 +           else if ( (~IRQ_MASK_BOTH[i_both]) & GPIO_DAT_I[i_both] & IRQ_MASK_WR_EN )
  17.366 +             // interrupt mask is being set, so clear edge-capture
  17.367 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY 0;
  17.368 +           else if (EDGE_CAP_WR_EN)
  17.369 +             // user's writing to the edge register, so update edge capture
  17.370 +             // register
  17.371 +             EDGE_CAPTURE_BOTH[i_both] <= #UDLY EDGE_CAPTURE_BOTH[i_both] & GPIO_DAT_I[i_both];
  17.372 +         end
  17.373 +         assign   IRQ_O = |(EDGE_CAPTURE_BOTH & IRQ_MASK_BOTH);
  17.374 +
  17.375 +     end else if (IRQ_MODE == 1 && TRISTATE_PORTS == 1) begin
  17.376 +         assign  IRQ_O = |IRQ_TRI_TEMP; 
  17.377 +     end else
  17.378 +         assign  IRQ_O = 1'b0;
  17.379 +   endgenerate   
  17.380 +
  17.381 +endmodule
  17.382 +`endif // GPIO_V
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/rtl/verilog/tpio.v	Fri Aug 13 10:41:29 2010 +0100
    18.3 @@ -0,0 +1,168 @@
    18.4 +// =============================================================================
    18.5 +//                           COPYRIGHT NOTICE
    18.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
    18.7 +// ALL RIGHTS RESERVED
    18.8 +// This confidential and proprietary software may be used only as authorised by
    18.9 +// a licensing agreement from Lattice Semiconductor Corporation.
   18.10 +// The entire notice above must be reproduced on all authorized copies and
   18.11 +// copies may only be made to the extent permitted by a licensing agreement from
   18.12 +// Lattice Semiconductor Corporation.
   18.13 +//
   18.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
   18.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
   18.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
   18.17 +// U.S.A                                   email: techsupport@latticesemi.com
   18.18 +// ============================================================================/
   18.19 +//                         FILE DETAILS
   18.20 +//                         FILE DETAILS
   18.21 +// Project          : GPIO for LM32
   18.22 +// File             : tpio.v
   18.23 +// Title            : Tri State IO control 
   18.24 +// Dependencies     : system_conf.v
   18.25 +// Description      : Implements the logic to interface tri-state IO with 
   18.26 +//                    Wishbone bus.
   18.27 +// =============================================================================
   18.28 +//                        REVISION HISTORY
   18.29 +// Version          : 7.0
   18.30 +// Mod. Date        : Jun 27, 2005
   18.31 +// Changes Made     : Initial Creation
   18.32 +//
   18.33 +// Version          : 7.0SP2, 3.0
   18.34 +// Mod. Date        : 20 Nov. 2007
   18.35 +// Changes Made     : Code clean up and add the BB for the inout port.
   18.36 +//
   18.37 +// Version          : 3.1
   18.38 +// Mod. Date        : 11 Oct. 2008
   18.39 +// Changes Made     : Update the Edge Capture Register clean method
   18.40 +//                    Make IRQ Mask register readable
   18.41 +// =============================================================================
   18.42 +`ifndef TPIO_V
   18.43 +`define TPIO_V
   18.44 +`timescale 1ns/100 ps
   18.45 +`include "system_conf.v"
   18.46 +module TRI_PIO #(parameter DATA_WIDTH = 16,
   18.47 +                 parameter IRQ_MODE = 1,
   18.48 +		 parameter LEVEL = 0,
   18.49 +                 parameter EDGE = 1,
   18.50 +                 parameter POSE_EDGE_IRQ = 1,
   18.51 +		 parameter NEGE_EDGE_IRQ = 0,
   18.52 +		 parameter EITHER_EDGE_IRQ = 0)
   18.53 +      (RST_I,
   18.54 +       CLK_I,
   18.55 +       DAT_I,
   18.56 +       DAT_O,
   18.57 +       PIO_IO,
   18.58 +       IRQ_O,
   18.59 +       PIO_TRI_WR_EN,
   18.60 +       PIO_TRI_RE_EN,
   18.61 +       PIO_DATA_RE_EN,
   18.62 +       PIO_DATA_WR_EN,
   18.63 +       IRQ_MASK_RE_EN,
   18.64 +       IRQ_MASK_WR_EN,
   18.65 +       EDGE_CAP_WR_EN);
   18.66 +
   18.67 +   parameter UDLY = 1;//user delay
   18.68 +
   18.69 +   input  RST_I;
   18.70 +   input  CLK_I;
   18.71 +   input  DAT_I;
   18.72 +   input  PIO_TRI_RE_EN;
   18.73 +   input  PIO_TRI_WR_EN;
   18.74 +   input  PIO_DATA_RE_EN;
   18.75 +   input  PIO_DATA_WR_EN;
   18.76 +   output DAT_O;
   18.77 +   input  IRQ_MASK_RE_EN;
   18.78 +   input  IRQ_MASK_WR_EN;
   18.79 +   input  EDGE_CAP_WR_EN;
   18.80 +   output IRQ_O;
   18.81 +   inout  PIO_IO;
   18.82 +
   18.83 +   wire  PIO_IO_I;
   18.84 +   wire  DAT_O;
   18.85 +   wire  IRQ_O;
   18.86 +   reg   PIO_DATA_O;
   18.87 +   reg   PIO_DATA_I;
   18.88 +   reg   PIO_TRI;
   18.89 +   reg   IRQ_MASK;
   18.90 +   reg   IRQ_TEMP;
   18.91 +   reg   EDGE_CAPTURE;
   18.92 +   reg   PIO_DATA_DLY;
   18.93 +
   18.94 +   always @(posedge CLK_I or posedge RST_I)
   18.95 +     if (RST_I)
   18.96 +       PIO_TRI <= #UDLY 0;
   18.97 +     else if (PIO_TRI_WR_EN)
   18.98 +       PIO_TRI <= #UDLY DAT_I;
   18.99 +   
  18.100 +   always @(posedge CLK_I or posedge RST_I)
  18.101 +     if (RST_I)
  18.102 +       PIO_DATA_O <= #UDLY 0;
  18.103 +     else if (PIO_DATA_WR_EN)
  18.104 +       PIO_DATA_O <= #UDLY DAT_I;
  18.105 +
  18.106 +   always @(posedge CLK_I or posedge RST_I)
  18.107 +     if (RST_I)
  18.108 +       PIO_DATA_I <= #UDLY 0;
  18.109 +     else if (PIO_DATA_RE_EN)
  18.110 +       PIO_DATA_I <= #UDLY PIO_IO_I;
  18.111 +   
  18.112 +   BB tpio_inst(.I(PIO_DATA_O), .T(~PIO_TRI), .O(PIO_IO_I), .B(PIO_IO));
  18.113 +   assign  DAT_O =  PIO_TRI_RE_EN ? PIO_TRI  : 
  18.114 +                   IRQ_MASK_RE_EN ? IRQ_MASK : PIO_DATA_I;
  18.115 +
  18.116 +   //IRQ_MODE
  18.117 +
  18.118 +   generate
  18.119 +     if (IRQ_MODE == 1) begin
  18.120 +       //CONFIG THE IRQ_MASK REG.  
  18.121 +       always @(posedge CLK_I or posedge RST_I)
  18.122 +         if (RST_I)
  18.123 +           IRQ_MASK <= #UDLY 0;
  18.124 +         else if (IRQ_MASK_WR_EN)
  18.125 +           IRQ_MASK <= #UDLY DAT_I;
  18.126 +       end
  18.127 +   endgenerate   
  18.128 +
  18.129 +   generate
  18.130 +      if (IRQ_MODE == 1 && LEVEL == 1) begin
  18.131 +          always @(posedge CLK_I or posedge RST_I)
  18.132 +            if (RST_I)
  18.133 +              IRQ_TEMP <= #UDLY 0;
  18.134 +            else
  18.135 +              IRQ_TEMP <= #UDLY PIO_IO_I & IRQ_MASK & ~PIO_TRI;//bit-and
  18.136 +          assign    IRQ_O = IRQ_TEMP;
  18.137 +          end
  18.138 +      else if (IRQ_MODE == 1 &&  EDGE == 1) begin   
  18.139 +          always @(posedge CLK_I or posedge RST_I)
  18.140 +            if (RST_I)
  18.141 +              PIO_DATA_DLY <= #UDLY 0;
  18.142 +            else
  18.143 +              PIO_DATA_DLY <= PIO_IO_I;
  18.144 +
  18.145 +             always @(posedge CLK_I or posedge RST_I)
  18.146 +               if (RST_I)
  18.147 +                 EDGE_CAPTURE <= #UDLY 0;
  18.148 +               else  if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && POSE_EDGE_IRQ == 1)
  18.149 +                 EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
  18.150 +               else  if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && NEGE_EDGE_IRQ == 1)
  18.151 +                 EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
  18.152 +               else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI)  && EITHER_EDGE_IRQ == 1)
  18.153 +                 EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
  18.154 +               else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI)  && EITHER_EDGE_IRQ == 1)
  18.155 +                 EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
  18.156 +               else if ( (~IRQ_MASK) & DAT_I & IRQ_MASK_WR_EN )
  18.157 +                 // interrupt mask's being set, so clear edge-capture
  18.158 +                 EDGE_CAPTURE <= #UDLY 0;
  18.159 +               else if ( EDGE_CAP_WR_EN )
  18.160 +                 // user's writing to the edge-register, so update edge-capture
  18.161 +                 // register
  18.162 +                 EDGE_CAPTURE <= #UDLY EDGE_CAPTURE & DAT_I;
  18.163 +
  18.164 +         assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
  18.165 +       end  
  18.166 +     else // IRQ_MODE ==0
  18.167 +         assign IRQ_O = 0;      
  18.168 +   endgenerate
  18.169 +endmodule
  18.170 +`endif // TPIO_V
  18.171 +