wb_sdram.v

Tue, 10 Aug 2010 22:11:51 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 22:11:51 +0100
changeset 10
2e7c2bcdac0e
parent 9
413ec22a27cd
child 11
efeebc7c7498
permissions
-rw-r--r--

[wb_sdram] parameterise timing and CAS latency

philpem@0 1 /****************************************************************************
philpem@0 2 *
philpem@0 3 *
philpem@0 4 ****************************************************************************/
philpem@0 5
philpem@0 6 module wb_sdram (
philpem@0 7 // Clocks and resets
philpem@0 8 input wb_clk_i, // WISHBONE clock
philpem@0 9 input wb_rst_i, // WISHBONE reset
philpem@0 10
philpem@0 11 // WISHBONE bus
philpem@0 12 input [31:0] wb_adr_i, // WISHBONE address
philpem@0 13 input [31:0] wb_dat_i, // WISHBONE data in
philpem@0 14 output reg [31:0] wb_dat_o, // WISHBONE data out
philpem@0 15 input [3:0] wb_sel_i, // WISHBONE byte select
philpem@0 16 input wb_we_i, // WISHBONE write enable (R/#W)
philpem@0 17 input wb_cyc_i, // WISHBONE cycle
philpem@0 18 input wb_stb_i, // WISHBONE strobe
philpem@7 19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
philpem@0 20 output wb_err_o, // WISHBONE bus error
philpem@0 21 output wb_rty_o, // WISHBONE retry-later
philpem@0 22
philpem@0 23 // SDRAM
philpem@0 24 output reg sdram_cke, // SDRAM clock enable
philpem@0 25 output sdram_cs_n, // SDRAM chip select (active low)
philpem@0 26 output sdram_ras_n, // SDRAM row address strobe (active low)
philpem@0 27 output sdram_cas_n, // SDRAM column address strobe (active low)
philpem@0 28 output sdram_we_n, // SDRAM write enable (active low)
philpem@0 29 output [11:0] sdram_a, // SDRAM address
philpem@0 30 output reg [1:0] sdram_ba, // SDRAM bank address
philpem@0 31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
philpem@0 32 inout [31:0] sdram_dq, // SDRAM data bus
philpem@0 33
philpem@0 34 // Debugging
philpem@3 35 output /*reg*/ [2:0] debug // debug bits
philpem@0 36 );
philpem@0 37
philpem@0 38
philpem@0 39 /****
philpem@10 40 * Timer values
philpem@10 41 ****/
philpem@10 42 // CAS latency -- either 2 or 3
philpem@10 43 parameter CAS_LATENCY = 3'd2;
philpem@10 44 // T_rp ==> 20ns
philpem@10 45 parameter TIME_Trp = 32'd1;
philpem@10 46 // T_rcd ==> 20ns
philpem@10 47 parameter TIME_Trcd = 32'd1;
philpem@10 48 // T_rfc (a.k.a. T_rc) ==> 70ns
philpem@10 49 parameter TIME_Trfc = 32'd2;
philpem@10 50 // T_mrd ==> 2 clock cycles
philpem@10 51 parameter TIME_Tmrd = 32'd2;
philpem@10 52
philpem@10 53
philpem@10 54 /****
philpem@8 55 * WISHBONE status pins
philpem@8 56 ****/
philpem@8 57 // Can't raise bus errors
philpem@8 58 assign wb_err_o = 1'b0;
philpem@8 59 // Can't request retries
philpem@8 60 assign wb_rty_o = 1'b0;
philpem@8 61
philpem@8 62
philpem@8 63 /****
philpem@0 64 * SDRAM data output buffer
philpem@0 65 ****/
philpem@0 66 // OE=1 for output mode, 0 for input
philpem@0 67 reg sdram_dq_oe;
philpem@0 68 // SDRAM output register
philpem@0 69 reg [31:0] sdram_dq_r;
philpem@0 70 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
philpem@0 71
philpem@0 72
philpem@0 73
philpem@0 74 /****
philpem@0 75 * State timer
philpem@0 76 * This is used to ensure that the state machine abides by RAM timing
philpem@0 77 * restrictions.
philpem@0 78 ****/
philpem@0 79 reg [31:0] timer;
philpem@0 80
philpem@0 81
philpem@0 82 /****
philpem@0 83 * MODE logic
philpem@0 84 ****/
philpem@0 85 reg [5:0] sdram_mode;
philpem@0 86 reg [11:0] sdram_addr;
philpem@0 87 assign sdram_cs_n = sdram_mode[3];
philpem@0 88 assign sdram_ras_n = sdram_mode[2];
philpem@0 89 assign sdram_cas_n = sdram_mode[1];
philpem@0 90 assign sdram_we_n = sdram_mode[0];
philpem@0 91 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
philpem@0 92
philpem@0 93 // SDRAM chip instructions
philpem@0 94 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
philpem@0 95 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
philpem@0 96 localparam M_BankActivate = 6'b0X0011;
philpem@0 97 localparam M_PrechargeBank = 6'b100010;
philpem@0 98 localparam M_PrechargeAll = 6'b110010;
philpem@0 99 localparam M_Write = 6'b100100;
philpem@0 100 localparam M_WritePrecharge = 6'b110100;
philpem@0 101 localparam M_Read = 6'b100101;
philpem@0 102 localparam M_ReadPrecharge = 6'b110101;
philpem@2 103 localparam M_LoadModeRegister = 6'b0X0000;
philpem@0 104 localparam M_Nop = 6'b0X0111;
philpem@0 105 localparam M_BurstStop = 6'b0X0110;
philpem@0 106 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
philpem@0 107 localparam M_AutoRefresh = 6'b0X0001;
philpem@0 108
philpem@0 109
philpem@0 110 /****
philpem@3 111 * Refresh Timer
philpem@3 112 ****/
philpem@3 113 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
philpem@3 114 reg [31:0] refresh_timer;
philpem@3 115 reg refresh_req, refresh_ack, refresh_timer_en;
philpem@3 116 always @(posedge wb_clk_i) begin
philpem@3 117 if (wb_rst_i | !refresh_timer_en) begin
philpem@3 118 // Reset; clear timer, unset REFRESH REQUEST
philpem@3 119 refresh_req <= 1'b0;
philpem@3 120 refresh_timer <= REFRESH_INTERVAL;
philpem@3 121 end else if (refresh_ack) begin
philpem@3 122 // Refresh Ack, clear Refresh Request.
philpem@3 123 refresh_req <= 1'b0;
philpem@3 124 end else if (refresh_timer == 0) begin
philpem@3 125 // Refresh timer timed out, make a Refresh Request and reload the timer
philpem@3 126 refresh_req <= 1'b1;
philpem@3 127 refresh_timer <= REFRESH_INTERVAL;
philpem@3 128 end else begin
philpem@3 129 // Otherwise just decrement the timer
philpem@3 130 refresh_timer <= refresh_timer - 32'd1;
philpem@3 131 end
philpem@3 132 end
philpem@3 133
philpem@3 134 assign debug = { 1'b0, refresh_req, refresh_ack };
philpem@3 135
philpem@4 136
philpem@4 137 /****
philpem@4 138 * Address decoder
philpem@4 139 ****/
philpem@4 140 wire [8:0] column_addr;
philpem@4 141 wire [11:0] row_addr;
philpem@4 142 wire [1:0] bank_addr;
philpem@4 143
philpem@7 144 // Convert a 23-bit linear address into an SDRAM address
philpem@4 145 assign column_addr = wb_adr_i[8:0];
philpem@4 146 assign bank_addr = wb_adr_i[10:9];
philpem@7 147 assign row_addr = wb_adr_i[22:11];
philpem@4 148
philpem@4 149
philpem@3 150 /****
philpem@0 151 * Finite State Machine
philpem@0 152 ****/
philpem@2 153 localparam ST_INIT1 = 32'd0;
philpem@2 154 localparam ST_INIT2 = 32'd1;
philpem@2 155 localparam ST_NOP1 = 32'd2;
philpem@2 156 localparam ST_PrechargeAll = 32'd3;
philpem@2 157 localparam ST_PrechargeAll_Wait = 32'd4;
philpem@2 158 localparam ST_AutoRefresh1 = 32'd5;
philpem@2 159 localparam ST_AutoRefresh1_Wait = 32'd6;
philpem@2 160 localparam ST_AutoRefresh2 = 32'd7;
philpem@2 161 localparam ST_AutoRefresh2_Wait = 32'd8;
philpem@2 162 localparam ST_LoadModeRegister = 32'd9;
philpem@2 163 localparam ST_LoadModeRegister_Wait = 32'd10;
philpem@3 164 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
philpem@3 165 localparam ST_Refresh = 32'd12;
philpem@3 166 localparam ST_Refresh_Wait = 32'd13;
philpem@7 167 localparam ST_Activate = 32'd30;
philpem@7 168 localparam ST_Activate_Wait = 32'd31;
philpem@7 169 localparam ST_Write = 32'd32;
philpem@7 170 localparam ST_Read = 32'd33;
philpem@7 171 localparam ST_Read_Wait = 32'd34;
philpem@7 172 localparam ST_Wait_Trp = 32'd35;
philpem@7 173 localparam ST_Ack = 32'd36;
philpem@7 174
philpem@0 175
philpem@0 176 reg [31:0] state;
philpem@0 177 always @(posedge wb_clk_i) begin
philpem@0 178 if (wb_rst_i) begin
philpem@0 179 // Initialise state machine and timer
philpem@0 180 state <= ST_INIT1;
philpem@3 181 // debug <= 3'd0;
philpem@0 182 timer <= 32'd0;
philpem@3 183
philpem@3 184 // Clear REFRESH ACK flag and disable refresh timer
philpem@3 185 refresh_ack <= 1'b0;
philpem@3 186 refresh_timer_en <= 1'b0;
philpem@0 187
philpem@0 188 // Initialisation state for SDRAM
philpem@0 189 sdram_cke <= 1'b0;
philpem@0 190 sdram_mode <= M_Inhibit;
philpem@0 191 sdram_addr <= 12'h000;
philpem@0 192 sdram_ba <= 2'b00;
philpem@0 193 sdram_dqm <= 4'b0000;
philpem@0 194 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 195 sdram_dq_r <= 32'd0;
philpem@0 196 end else begin
philpem@0 197 // timer logic
philpem@0 198 if (timer > 32'd0) begin
philpem@0 199 timer <= timer - 32'd1;
philpem@0 200 end
philpem@0 201
philpem@0 202 // state machine logic
philpem@0 203 case (state)
philpem@0 204 ST_INIT1: begin
philpem@0 205 // INIT1: Set up for initial power-up wait
philpem@0 206 state <= ST_INIT2;
philpem@0 207 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
philpem@0 208
philpem@0 209 // SDRAM state
philpem@0 210 sdram_cke <= 1'b0; // clock disabled
philpem@0 211 sdram_mode <= M_Inhibit;
philpem@0 212 sdram_addr <= 12'h000;
philpem@0 213 sdram_ba <= 2'b00;
philpem@0 214 sdram_dqm <= 4'b1111;
philpem@0 215 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 216 sdram_dq_r <= 32'd0;
philpem@0 217 end
philpem@0 218
philpem@0 219 ST_INIT2: begin
philpem@0 220 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
philpem@0 221 // the end of the power-up wait, then bring CKE high.
philpem@0 222 if (timer == 32'd0) begin
philpem@0 223 // Timer hit zero. Send a NOP.
philpem@2 224 state <= ST_NOP1;
philpem@1 225 end else if (timer < 32'd50) begin
philpem@0 226 // Timer value is more than zero but less than 50; CKE is on, but
philpem@0 227 // keep waiting for the timer to actually expire.
philpem@0 228 sdram_cke <= 1'b1;
philpem@0 229 state <= ST_INIT2;
philpem@3 230 // debug <= 3'd1;
philpem@0 231 end
philpem@0 232 sdram_mode <= M_Inhibit;
philpem@0 233 end
philpem@0 234
philpem@2 235 ST_NOP1: begin
philpem@2 236 // Apply one or more NOP commands to the SDRAM
philpem@2 237 sdram_mode <= M_Nop;
philpem@2 238 state <= ST_PrechargeAll;
philpem@2 239 end
philpem@2 240
philpem@2 241 ST_PrechargeAll: begin
philpem@2 242 // Precharge All, then wait T_rp (20ns)
philpem@2 243 sdram_mode <= M_PrechargeAll;
philpem@10 244 timer <= TIME_Trp - 32'd1;
philpem@2 245 state <= ST_PrechargeAll_Wait;
philpem@2 246 end
philpem@2 247
philpem@2 248 ST_PrechargeAll_Wait: begin
philpem@2 249 // Wait for T_rp after Precharge All
philpem@2 250 sdram_mode <= M_Nop;
philpem@2 251 if (timer == 32'd0) begin
philpem@2 252 // Timer hit zero. Continue
philpem@2 253 state <= ST_AutoRefresh1;
philpem@2 254 end
philpem@2 255 end
philpem@2 256
philpem@2 257 ST_AutoRefresh1: begin
philpem@2 258 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
philpem@2 259 sdram_mode <= M_AutoRefresh;
philpem@10 260 timer <= TIME_Trfc - 32'd1;
philpem@2 261 state <= ST_AutoRefresh1_Wait;
philpem@2 262 end
philpem@2 263
philpem@2 264 ST_AutoRefresh1_Wait: begin
philpem@2 265 // Wait for T_rfc
philpem@1 266 sdram_mode <= M_Nop;
philpem@2 267 if (timer == 32'd0) begin
philpem@2 268 // Timer hit zero. Continue
philpem@2 269 state <= ST_AutoRefresh2;
philpem@2 270 end
philpem@2 271 end
philpem@2 272
philpem@2 273 ST_AutoRefresh2: begin
philpem@2 274 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
philpem@2 275 sdram_mode <= M_AutoRefresh;
philpem@10 276 timer <= TIME_Trfc - 32'd1;
philpem@2 277 state <= ST_AutoRefresh2_Wait;
philpem@2 278 end
philpem@2 279
philpem@2 280 ST_AutoRefresh2_Wait: begin
philpem@2 281 // Wait for T_rfc
philpem@2 282 sdram_mode <= M_Nop;
philpem@2 283 if (timer == 32'd0) begin
philpem@2 284 // Timer hit zero. Continue
philpem@2 285 state <= ST_LoadModeRegister;
philpem@2 286 end
philpem@2 287 end
philpem@2 288
philpem@2 289 ST_LoadModeRegister: begin
philpem@2 290 // Load Mode Register
philpem@2 291 /**
philpem@2 292 * Mode register:
philpem@2 293 * - BS0,1 = 00 [RFU]
philpem@2 294 * - A11,10 = 00 [RFU]
philpem@2 295 * - A9 = 0 [WBL -- write burst length same as read burst length]
philpem@2 296 * - A8,7 = 00 [Test Mode off]
philpem@10 297 * - A6..4 = 010 [CAS Latency = 2 or 3 clocks, set above]
philpem@2 298 * - A3 = 0 [Burst type = sequential]
philpem@2 299 * - A2..0 = 000 [Burst length = 1 word]
philpem@2 300 */
philpem@2 301 sdram_ba <= 2'b00;
philpem@10 302 sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
philpem@2 303 sdram_mode <= M_LoadModeRegister;
philpem@2 304
philpem@2 305 // Wait T_mrd (2 clock cycles)
philpem@10 306 timer <= TIME_Tmrd - 32'd1;
philpem@2 307 state <= ST_LoadModeRegister_Wait;
philpem@2 308 end
philpem@2 309
philpem@2 310 ST_LoadModeRegister_Wait: begin
philpem@2 311 // Wait for LMR to complete
philpem@2 312 sdram_mode <= M_Nop;
philpem@2 313 sdram_ba <= 2'd0;
philpem@2 314 sdram_addr <= 12'd0;
philpem@2 315 if (timer == 32'd0) begin
philpem@2 316 // Timer hit zero. Continue
philpem@2 317 state <= ST_Spin;
philpem@2 318 end
philpem@2 319 end
philpem@2 320
philpem@2 321 ST_Spin: begin
philpem@3 322 // Enable refresh timer
philpem@3 323 refresh_timer_en <= 1'b1;
philpem@3 324
philpem@7 325 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
philpem@2 326 sdram_mode <= M_Inhibit;
philpem@3 327
philpem@9 328 // Check if a refresh is due (these have highest priority)
philpem@3 329 if (refresh_req) begin
philpem@3 330 // Refresh request received. Ack it and do a refresh.
philpem@3 331 refresh_ack <= 1'b1;
philpem@3 332 state <= ST_Refresh;
philpem@3 333 end else begin
philpem@7 334 if (wb_cyc_i & wb_stb_i) begin
philpem@7 335 // CYC and STB high. A Wishbone cycle just started.
philpem@7 336 state <= ST_Activate;
philpem@7 337 end
philpem@3 338 end
philpem@3 339 end
philpem@7 340
philpem@7 341 /////
philpem@7 342 // Refresh logic
philpem@7 343 /////
philpem@3 344
philpem@3 345 ST_Refresh: begin
philpem@3 346 // Refresh timer timed out; do a refresh run
philpem@3 347 // Start by clearing the ACK flag (which was set by the Spin state)
philpem@3 348 refresh_ack <= 1'b0;
philpem@3 349 // Tell the SDRAM to do a Refresh
philpem@3 350 sdram_mode <= M_AutoRefresh;
philpem@3 351 // Wait for T_rfc
philpem@10 352 timer <= TIME_Trfc;
philpem@3 353 state <= ST_Refresh_Wait;
philpem@3 354 end
philpem@3 355
philpem@3 356 ST_Refresh_Wait: begin
philpem@3 357 // Wait for T_rfc
philpem@3 358 sdram_mode <= M_Nop;
philpem@3 359 if (timer == 32'd0) begin
philpem@3 360 // Timer hit zero. Go back to spin state.
philpem@3 361 state <= ST_Spin;
philpem@3 362 end
philpem@0 363 end
philpem@7 364
philpem@7 365 //////
philpem@7 366 // R/W logic
philpem@7 367 //////
philpem@7 368 ST_Activate: begin
philpem@7 369 // Activate the required bank
philpem@4 370 sdram_mode <= M_BankActivate;
philpem@4 371 sdram_addr <= row_addr;
philpem@7 372 sdram_ba <= bank_addr;
philpem@10 373 timer <= TIME_Trcd - 32'd1;
philpem@7 374 state <= ST_Activate_Wait;
philpem@4 375 end
philpem@4 376
philpem@7 377 ST_Activate_Wait: begin
philpem@7 378 // Wait for T_rcd
philpem@4 379 sdram_mode <= M_Nop;
philpem@4 380 if (timer == 32'd0) begin
philpem@7 381 if (wb_we_i) begin
philpem@7 382 // Write cycle.
philpem@7 383 state <= ST_Write;
philpem@7 384 end else begin
philpem@7 385 // Read cycle
philpem@7 386 state <= ST_Read;
philpem@7 387 end
philpem@4 388 end
philpem@4 389 end
philpem@4 390
philpem@7 391 ST_Write: begin
philpem@7 392 // Write cycle handler
philpem@7 393 sdram_mode <= M_WritePrecharge;
philpem@7 394 sdram_addr <= column_addr;
philpem@7 395 sdram_dq_r <= wb_dat_i;
philpem@7 396 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
philpem@9 397 sdram_dqm <= ~wb_sel_i;
philpem@7 398
philpem@7 399 // Wait T_rp (20ns)
philpem@10 400 timer <= TIME_Trp - 32'd1;
philpem@7 401 state <= ST_Wait_Trp;
philpem@7 402 end
philpem@7 403
philpem@7 404 ST_Read: begin
philpem@7 405 // Read cycle handler
philpem@7 406 sdram_mode <= M_ReadPrecharge;
philpem@7 407 sdram_addr <= column_addr;
philpem@7 408 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 409 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
philpem@10 410 timer <= CAS_LATENCY - 32'd1; // CAS# Latency
philpem@7 411 state <= ST_Read_Wait;
philpem@4 412 end
philpem@4 413
philpem@7 414 ST_Read_Wait: begin
philpem@7 415 // Wait for CAS# latency
philpem@7 416 sdram_mode <= M_Nop;
philpem@7 417 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
philpem@4 418 if (timer == 32'd0) begin
philpem@7 419 // Latch data
philpem@7 420 wb_dat_o <= sdram_dq;
philpem@7 421 // Wait T_rp (20ns)
philpem@10 422 timer <= TIME_Trp - 32'd1;
philpem@7 423 state <= ST_Wait_Trp;
philpem@4 424 end
philpem@4 425 end
philpem@5 426
philpem@7 427 ST_Wait_Trp: begin
philpem@7 428 // Wait for T_rp, then ack
philpem@7 429 if (timer == 32'd0) begin
philpem@7 430 state <= ST_Ack;
philpem@7 431 end
philpem@4 432 end
philpem@4 433
philpem@7 434 ST_Ack: begin
philpem@7 435 // Ack the transfer to the WISHBONE host
philpem@7 436 sdram_mode <= M_Nop;
philpem@7 437 sdram_addr <= 32'd0;
philpem@7 438 sdram_dq_r <= 32'd0;
philpem@7 439 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 440 sdram_dqm <= 4'b1111; // mask off DQM
philpem@7 441 if (wb_cyc_i & wb_stb_i) begin
philpem@7 442 // CYC and STB high, ack the transfer
philpem@7 443 wb_ack_o <= 1'b1;
philpem@7 444 state <= ST_Ack;
philpem@7 445 end else begin
philpem@9 446 // CYC and STB low, go back and wait for another transaction
philpem@9 447 wb_ack_o <= 1'b0;
philpem@7 448 state <= ST_Spin;
philpem@4 449 end
philpem@4 450 end
philpem@0 451 endcase
philpem@0 452 end
philpem@0 453 end
philpem@0 454
philpem@0 455 endmodule