IPCores/wb_sdram: wb_sdram.v@49f3a5bd860e (annotated)

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wb_sdram.v@49f3a5bd860e (annotated)

wb_sdram.v

Wed, 11 Aug 2010 01:19:03 +0100

author: Philip Pemberton <philpem@philpem.me.uk>
date: Wed, 11 Aug 2010 01:19:03 +0100
changeset 16: 49f3a5bd860e
parent 15: da71a5efdf98
child 17: ac979332d5fd
permissions: -rw-r--r--

[wb_sdram] add nice comments to explain sdram timings

 	/****************************************************************************
  *
  *
  ****************************************************************************/
 module wb_sdram (
 	// Clocks and resets
 	input						wb_clk_i,			// WISHBONE clock
 	input						wb_rst_i,			// WISHBONE reset
 	// WISHBONE bus
 	input			[31:0]	wb_adr_i,			// WISHBONE address
 	input			[31:0]	wb_dat_i,			// WISHBONE data in
 	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
 	input			[3:0]		wb_sel_i,			// WISHBONE byte select
 	input						wb_we_i,				// WISHBONE write enable (R/#W)
 	input						wb_cyc_i,			// WISHBONE cycle
 	input						wb_stb_i,			// WISHBONE strobe
 	output reg				wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
 	output					wb_err_o,			// WISHBONE bus error
 	output					wb_rty_o,			// WISHBONE retry-later
 	// SDRAM
 	output reg				sdram_cke,			// SDRAM clock enable
 	output					sdram_cs_n,			// SDRAM chip select (active low)
 	output					sdram_ras_n,		// SDRAM row address strobe (active low)
 	output					sdram_cas_n,		// SDRAM column address strobe (active low)
 	output					sdram_we_n,			// SDRAM write enable (active low)
 	output		[11:0]	sdram_a,				// SDRAM address
 	output reg	[1:0]		sdram_ba,			// SDRAM bank address
 	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
 	inout			[31:0]	sdram_dq,			// SDRAM data bus
 	// Debugging
 	output /*reg*/	[2:0]		debug					// debug bits
 );
 /****
  * Timer values
  ****/
 // CAS latency -- either 2 or 3   [2010-08-10: tested with CL=3, worked fine]
 parameter	CAS_LATENCY		= 3'd2;
 // System clock frequency
 parameter	CLOCK_RATE		= 25_000_000;
 // SDRAM timings in nanoseconds
 // Precharge to refresh/row activate command (same bank) -- Trp
 parameter	TIME_Trp			= 20;
 // RAS# to CAS# delay -- Trcd
 parameter	TIME_Trcd		= 20;
 // Row cycle time -- Trfc, also known as Trc
 parameter	TIME_Trfc		= 70;
 // Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
 parameter	TIME_Refresh	= 15_625;
 // 2ms power-up init period
 parameter	TIME_InitDelay	= 2_000_000;
 // 2us before the end of the init period, raise CKE
 parameter	TIME_InitFinal	= 2_000;
 // Calculate clock period in nanoseconds
 localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;
 // T_rp  ==> 20ns
 localparam	TCY_Trp			= (TIME_Trp+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 // T_rcd ==> 20ns
 localparam	TCY_Trcd			= (TIME_Trcd+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 // T_rfc (a.k.a. T_rc) ==> 70ns
 localparam	TCY_Trfc			= (TIME_Trfc+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 // T_mrd ==> 2 clock cycles
 localparam	TCY_Tmrd			= 32'd2;
 // Maximum allowed time between two refresh cycles
 localparam	TCY_Refresh		= (TIME_Refresh+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 localparam	TCY_InitDelay	= (TIME_InitDelay+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 localparam	TCY_InitFinal	= (TIME_InitFinal+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
 /****
  * WISHBONE status pins
  ****/
 // Can't raise bus errors
 assign wb_err_o = 1'b0;
 // Can't request retries
 assign wb_rty_o = 1'b0;
 // Lock DEBUG pins low
 assign debug = 3'd0;
 /****
  * SDRAM data output buffer
  ****/
 // OE=1 for output mode, 0 for input
 reg sdram_dq_oe;
 // SDRAM output register
 reg [31:0] sdram_dq_r;
 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
 /****
  * State timer
  * This is used to ensure that the state machine abides by RAM timing
  * restrictions.
  ****/
 reg [31:0] timer;
 /****
  * MODE logic
  ****/
 reg  [5:0]  sdram_mode;
 reg  [11:0]	sdram_addr;
 assign sdram_cs_n		= sdram_mode[3];
 assign sdram_ras_n	= sdram_mode[2];
 assign sdram_cas_n	= sdram_mode[1];
 assign sdram_we_n		= sdram_mode[0];
 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
 // SDRAM chip instructions
 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
 localparam M_BankActivate		= 6'b0X0011;
 localparam M_PrechargeBank		= 6'b100010;
 localparam M_PrechargeAll		= 6'b110010;
 localparam M_Write				= 6'b100100;
 localparam M_WritePrecharge	= 6'b110100;
 localparam M_Read					= 6'b100101;
 localparam M_ReadPrecharge		= 6'b110101;
 localparam M_LoadModeRegister	= 6'b0X0000;
 localparam M_Nop					= 6'b0X0111;
 localparam M_BurstStop			= 6'b0X0110;
 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
 localparam M_AutoRefresh		= 6'b0X0001;
 /****
  * Refresh Timer
  ****/
 reg [31:0] refresh_timer;
 reg refresh_req, refresh_ack, refresh_timer_en;
 always @(posedge wb_clk_i) begin
 	if (wb_rst_i | !refresh_timer_en) begin
 		// Reset; clear timer, unset REFRESH REQUEST
 		refresh_req <= 1'b0;
 		refresh_timer <= TCY_Refresh - 32'd1;
 	end else if (refresh_ack) begin
 		// Refresh Ack, clear Refresh Request.
 		refresh_req <= 1'b0;
 	end else if (refresh_timer == 0) begin
 		// Refresh timer timed out, make a Refresh Request and reload the timer
 		refresh_req <= 1'b1;
 		refresh_timer <= TCY_Refresh - 32'd1;
 	end else begin
 		// Otherwise just decrement the timer
 		refresh_timer <= refresh_timer - 32'd1;
 	end
 end
 /****
  * Address decoder
  ****/
 wire [8:0] column_addr;
 wire [11:0] row_addr;
 wire [1:0] bank_addr;
 // Convert a 23-bit linear address into an SDRAM address
 assign column_addr	= wb_adr_i[8:0];
 assign bank_addr		= wb_adr_i[10:9];
 assign row_addr		= wb_adr_i[22:11];
 /****
  * Finite State Machine
  ****/
 localparam	ST_INIT1							= 32'd0;
 localparam	ST_INIT2							= 32'd1;
 localparam	ST_NOP1							= 32'd2;
 localparam	ST_PrechargeAll				= 32'd3;
 localparam	ST_PrechargeAll_Wait			= 32'd4;
 localparam	ST_AutoRefresh1				= 32'd5;
 localparam	ST_AutoRefresh1_Wait			= 32'd6;
 localparam	ST_AutoRefresh2				= 32'd7;
 localparam	ST_AutoRefresh2_Wait			= 32'd8;
 localparam	ST_LoadModeRegister			= 32'd9;
 localparam	ST_LoadModeRegister_Wait	= 32'd10;
 localparam	ST_Spin							= 32'd11;		// <<== main 'spin' / 'idle' state
 localparam	ST_Refresh						= 32'd12;
 localparam	ST_Refresh_Wait				= 32'd13;
 localparam	ST_Activate						= 32'd30;
 localparam	ST_Activate_Wait				= 32'd31;
 localparam	ST_Write							= 32'd32;
 localparam	ST_Read							= 32'd33;
 localparam	ST_Read_Wait					= 32'd34;
 localparam	ST_Wait_Trp						= 32'd35;
 localparam	ST_Ack							= 32'd36;
 reg [31:0] state;
 always @(posedge wb_clk_i) begin
 	if (wb_rst_i) begin
 		// Initialise state machine and timer
 		state <= ST_INIT1;
 		timer <= 32'd0;
 		// Clear REFRESH ACK flag and disable refresh timer
 		refresh_ack <= 1'b0;
 		refresh_timer_en <= 1'b0;
 		// Initialisation state for SDRAM
 		sdram_cke	<= 1'b0;
 		sdram_mode	<= M_Inhibit;
 		sdram_addr	<= 12'h000;
 		sdram_ba		<= 2'b00;
 		sdram_dqm	<= 4'b0000;
 		sdram_dq_oe	<= 1'b0;			// data output disabled
 		sdram_dq_r	<= 32'd0;
 	end else begin
 		// timer logic
 		if (timer > 32'd0) begin
 			timer <= timer - 32'd1;
 		end
 		// state machine logic
 		case (state)
 			ST_INIT1: begin
 					// INIT1: Set up for initial power-up wait
 					state <= ST_INIT2;
 					timer <= TCY_InitDelay;		// Needs to be >= 100us
 					// SDRAM state
 					sdram_cke	<= 1'b0;			// clock disabled
 					sdram_mode	<= M_Inhibit;
 					sdram_addr	<= 12'h000;
 					sdram_ba		<= 2'b00;
 					sdram_dqm	<= 4'b1111;
 					sdram_dq_oe	<= 1'b0;			// data output disabled
 					sdram_dq_r	<= 32'd0;
 				end
 			ST_INIT2: begin
 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
 					// the end of the power-up wait, then bring CKE high.
 					if (timer == 32'd0) begin
 						// Timer hit zero. Send a NOP.
 						state <= ST_NOP1;
 					end else if (timer < TCY_InitFinal) begin
 						// Timer value is more than zero but less than 50; CKE is on, but
 						// keep waiting for the timer to actually expire.
 						sdram_cke	<= 1'b1;
 						state			<= ST_INIT2;
 					end
 					sdram_mode <= M_Inhibit;
 				end
 			ST_NOP1: begin
 					// Apply one or more NOP commands to the SDRAM
 					sdram_mode <= M_Nop;
 					state <= ST_PrechargeAll;
 				end
 			ST_PrechargeAll: begin
 					// Precharge All, then wait T_rp (20ns)
 					sdram_mode <= M_PrechargeAll;
 					timer <= TCY_Trp - 32'd1;
 					state <= ST_PrechargeAll_Wait;
 				end
 			ST_PrechargeAll_Wait: begin
 					// Wait for T_rp after Precharge All
 					sdram_mode <= M_Nop;
 					if (timer == 32'd0) begin
 						// Timer hit zero. Continue
 						state <= ST_AutoRefresh1;
 					end
 				end
 			ST_AutoRefresh1: begin
 					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
 					sdram_mode <= M_AutoRefresh;
 					timer <= TCY_Trfc - 32'd1;
 					state <= ST_AutoRefresh1_Wait;
 				end
 			ST_AutoRefresh1_Wait: begin
 					// Wait for T_rfc
 					sdram_mode <= M_Nop;
 					if (timer == 32'd0) begin
 						// Timer hit zero. Continue
 						state <= ST_AutoRefresh2;
 					end
 				end
 			ST_AutoRefresh2: begin
 					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
 					sdram_mode <= M_AutoRefresh;
 					timer <= TCY_Trfc - 32'd1;
 					state <= ST_AutoRefresh2_Wait;
 				end
 			ST_AutoRefresh2_Wait: begin
 					// Wait for T_rfc
 					sdram_mode <= M_Nop;
 					if (timer == 32'd0) begin
 						// Timer hit zero. Continue
 						state <= ST_LoadModeRegister;
 					end
 				end
 			ST_LoadModeRegister: begin
 					// Load Mode Register
 					/**
 					 * Mode register:
 					 *   - BS0,1  = 00  [RFU]
 					 *   - A11,10 = 00  [RFU]
 					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
 					 *   - A8,7   = 00  [Test Mode off]
 					 *   - A6..4  = 010 [CAS Latency = 2 or 3 clocks, set above]
 					 *   - A3     = 0   [Burst type = sequential]
 					 *   - A2..0  = 000 [Burst length = 1 word]
 					 */
 					sdram_ba <= 2'b00;
 					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
 					sdram_mode <= M_LoadModeRegister;
 					// Wait T_mrd (2 clock cycles)
 					timer <= TCY_Tmrd - 32'd1;
 					state <= ST_LoadModeRegister_Wait;
 				end
 			ST_LoadModeRegister_Wait: begin
 					// Wait for LMR to complete
 					sdram_mode <= M_Nop;
 					sdram_ba <= 2'd0;
 					sdram_addr <= 12'd0;
 					if (timer == 32'd0) begin
 						// Timer hit zero. Continue
 						state <= ST_Spin;
 					end
 				end
 			ST_Spin: begin
 					// Enable refresh timer
 					refresh_timer_en <= 1'b1;
 					// Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
 					sdram_mode <= M_Inhibit;
 					// Check if a refresh is due (these have highest priority)
 					if (refresh_req) begin
 						// Refresh request received. Ack it and do a refresh.
 						refresh_ack <= 1'b1;
 						state <= ST_Refresh;
 					end else begin
 						if (wb_cyc_i & wb_stb_i) begin
 							// CYC and STB high. A Wishbone cycle just started.
 							state <= ST_Activate;
 						end
 					end
 				end
 /////
 // Refresh logic
 /////
 			ST_Refresh: begin
 					// Refresh timer timed out; do a refresh run
 					// Start by clearing the ACK flag (which was set by the Spin state)
 					refresh_ack <= 1'b0;
 					// Tell the SDRAM to do a Refresh
 					sdram_mode <= M_AutoRefresh;
 					// Wait for T_rfc
 					timer <= TCY_Trfc;
 					state <= ST_Refresh_Wait;
 				end
 			ST_Refresh_Wait: begin
 					// Wait for T_rfc
 					sdram_mode <= M_Nop;
 					if (timer == 32'd0) begin
 						// Timer hit zero. Go back to spin state.
 						state <= ST_Spin;
 					end
 				end
 //////
 // R/W logic
 //////
 			ST_Activate: begin
 					// Activate the required bank
 					sdram_mode <= M_BankActivate;
 					sdram_addr <= row_addr;
 					sdram_ba   <= bank_addr;
 					timer <= TCY_Trcd - 32'd1;
 					state <= ST_Activate_Wait;
 				end
 			ST_Activate_Wait: begin
 					// Wait for T_rcd
 					sdram_mode <= M_Nop;
 					if (timer == 32'd0) begin
 						if (wb_we_i) begin
 							// Write cycle.
 							state <= ST_Write;
 						end else begin
 							// Read cycle
 							state <= ST_Read;
 						end
 					end
 				end
 			ST_Write: begin
 					// Write cycle handler
 					sdram_mode	<= M_WritePrecharge;
 					sdram_addr	<= column_addr;
 					sdram_dq_r	<= wb_dat_i;
 					sdram_dq_oe	<= 1'b1;		// FPGA drives the DQ bus
 					sdram_dqm	<= ~wb_sel_i;
 					// Wait T_rp (20ns)
 					timer <= TCY_Trp - 32'd1;
 					state <= ST_Wait_Trp;
 				end
 			ST_Read: begin
 					// Read cycle handler
 					sdram_mode	<= M_ReadPrecharge;
 					sdram_addr	<= column_addr;
 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
 					sdram_dqm	<= 4'b0000;	// Grab all the data (it's just easier that way...)
 					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
 					state <= ST_Read_Wait;
 				end
 			ST_Read_Wait: begin
 					// Wait for CAS# latency
 					sdram_mode	<= M_Nop;
 					sdram_dqm	<= 4'b1111;	// Make SDRAM DQ bus float
 					if (timer == 32'd0) begin
 						// Latch data
 						wb_dat_o <= sdram_dq;
 						// Wait T_rp (20ns)
 						timer <= TCY_Trp - 32'd1;
 						state <=	ST_Wait_Trp;
 					end
 				end
 			ST_Wait_Trp: begin
 					// Wait for T_rp, then ack
 					if (timer == 32'd0) begin
 						state <= ST_Ack;
 					end
 				end
 			ST_Ack: begin
 					// Ack the transfer to the WISHBONE host
 					sdram_mode	<= M_Nop;
 					sdram_addr	<= 32'd0;
 					sdram_dq_r	<= 32'd0;
 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
 					sdram_dqm	<= 4'b1111;	// mask off DQM
 					if (wb_cyc_i & wb_stb_i) begin
 						// CYC and STB high, ack the transfer
 						wb_ack_o		<= 1'b1;
 						state			<= ST_Ack;
 					end else begin
 						// CYC and STB low, go back and wait for another transaction
 						wb_ack_o		<= 1'b0;
 						state			<= ST_Spin;
 					end
 				end
 		endcase
 	end
 end
 endmodule

IPCores/wb_sdram / annotate

wb_sdram.v@49f3a5bd860e (annotated)

wb_sdram.v