wb_sdram.v

Tue, 10 Aug 2010 22:49:21 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 22:49:21 +0100
changeset 12
81ec01103af1
parent 11
efeebc7c7498
child 13
07b3fd53e7a5
permissions
-rw-r--r--

[wb_sdram] tidy up refresh time parameterisation

philpem@11 1 /****************************************************************************
philpem@0 2 *
philpem@0 3 *
philpem@0 4 ****************************************************************************/
philpem@0 5
philpem@0 6 module wb_sdram (
philpem@0 7 // Clocks and resets
philpem@0 8 input wb_clk_i, // WISHBONE clock
philpem@0 9 input wb_rst_i, // WISHBONE reset
philpem@0 10
philpem@0 11 // WISHBONE bus
philpem@0 12 input [31:0] wb_adr_i, // WISHBONE address
philpem@0 13 input [31:0] wb_dat_i, // WISHBONE data in
philpem@0 14 output reg [31:0] wb_dat_o, // WISHBONE data out
philpem@0 15 input [3:0] wb_sel_i, // WISHBONE byte select
philpem@0 16 input wb_we_i, // WISHBONE write enable (R/#W)
philpem@0 17 input wb_cyc_i, // WISHBONE cycle
philpem@0 18 input wb_stb_i, // WISHBONE strobe
philpem@7 19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
philpem@0 20 output wb_err_o, // WISHBONE bus error
philpem@0 21 output wb_rty_o, // WISHBONE retry-later
philpem@0 22
philpem@0 23 // SDRAM
philpem@0 24 output reg sdram_cke, // SDRAM clock enable
philpem@0 25 output sdram_cs_n, // SDRAM chip select (active low)
philpem@0 26 output sdram_ras_n, // SDRAM row address strobe (active low)
philpem@0 27 output sdram_cas_n, // SDRAM column address strobe (active low)
philpem@0 28 output sdram_we_n, // SDRAM write enable (active low)
philpem@0 29 output [11:0] sdram_a, // SDRAM address
philpem@0 30 output reg [1:0] sdram_ba, // SDRAM bank address
philpem@0 31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
philpem@0 32 inout [31:0] sdram_dq, // SDRAM data bus
philpem@0 33
philpem@0 34 // Debugging
philpem@3 35 output /*reg*/ [2:0] debug // debug bits
philpem@0 36 );
philpem@0 37
philpem@0 38
philpem@0 39 /****
philpem@10 40 * Timer values
philpem@10 41 ****/
philpem@10 42 // CAS latency -- either 2 or 3
philpem@12 43 parameter CAS_LATENCY = 3'd2;
philpem@10 44 // T_rp ==> 20ns
philpem@12 45 parameter TIME_Trp = 32'd1;
philpem@10 46 // T_rcd ==> 20ns
philpem@12 47 parameter TIME_Trcd = 32'd1;
philpem@10 48 // T_rfc (a.k.a. T_rc) ==> 70ns
philpem@12 49 parameter TIME_Trfc = 32'd2;
philpem@10 50 // T_mrd ==> 2 clock cycles
philpem@12 51 parameter TIME_Tmrd = 32'd2;
philpem@12 52 // Maximum allowed time between two refresh cycles
philpem@12 53 parameter TIME_REFRESH = 32'd390;
philpem@10 54
philpem@10 55
philpem@10 56 /****
philpem@8 57 * WISHBONE status pins
philpem@8 58 ****/
philpem@8 59 // Can't raise bus errors
philpem@8 60 assign wb_err_o = 1'b0;
philpem@8 61 // Can't request retries
philpem@8 62 assign wb_rty_o = 1'b0;
philpem@11 63 // Lock DEBUG pins low
philpem@11 64 assign debug = 3'd0;
philpem@8 65
philpem@8 66 /****
philpem@0 67 * SDRAM data output buffer
philpem@0 68 ****/
philpem@0 69 // OE=1 for output mode, 0 for input
philpem@0 70 reg sdram_dq_oe;
philpem@0 71 // SDRAM output register
philpem@0 72 reg [31:0] sdram_dq_r;
philpem@0 73 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
philpem@0 74
philpem@0 75
philpem@0 76
philpem@0 77 /****
philpem@0 78 * State timer
philpem@0 79 * This is used to ensure that the state machine abides by RAM timing
philpem@0 80 * restrictions.
philpem@0 81 ****/
philpem@0 82 reg [31:0] timer;
philpem@0 83
philpem@0 84
philpem@0 85 /****
philpem@0 86 * MODE logic
philpem@0 87 ****/
philpem@0 88 reg [5:0] sdram_mode;
philpem@0 89 reg [11:0] sdram_addr;
philpem@0 90 assign sdram_cs_n = sdram_mode[3];
philpem@0 91 assign sdram_ras_n = sdram_mode[2];
philpem@0 92 assign sdram_cas_n = sdram_mode[1];
philpem@0 93 assign sdram_we_n = sdram_mode[0];
philpem@0 94 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
philpem@0 95
philpem@0 96 // SDRAM chip instructions
philpem@0 97 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
philpem@0 98 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
philpem@0 99 localparam M_BankActivate = 6'b0X0011;
philpem@0 100 localparam M_PrechargeBank = 6'b100010;
philpem@0 101 localparam M_PrechargeAll = 6'b110010;
philpem@0 102 localparam M_Write = 6'b100100;
philpem@0 103 localparam M_WritePrecharge = 6'b110100;
philpem@0 104 localparam M_Read = 6'b100101;
philpem@0 105 localparam M_ReadPrecharge = 6'b110101;
philpem@2 106 localparam M_LoadModeRegister = 6'b0X0000;
philpem@0 107 localparam M_Nop = 6'b0X0111;
philpem@0 108 localparam M_BurstStop = 6'b0X0110;
philpem@0 109 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
philpem@0 110 localparam M_AutoRefresh = 6'b0X0001;
philpem@0 111
philpem@0 112
philpem@0 113 /****
philpem@3 114 * Refresh Timer
philpem@3 115 ****/
philpem@3 116 reg [31:0] refresh_timer;
philpem@3 117 reg refresh_req, refresh_ack, refresh_timer_en;
philpem@3 118 always @(posedge wb_clk_i) begin
philpem@3 119 if (wb_rst_i | !refresh_timer_en) begin
philpem@3 120 // Reset; clear timer, unset REFRESH REQUEST
philpem@3 121 refresh_req <= 1'b0;
philpem@12 122 refresh_timer <= TIME_REFRESH - 32'd1;
philpem@3 123 end else if (refresh_ack) begin
philpem@3 124 // Refresh Ack, clear Refresh Request.
philpem@3 125 refresh_req <= 1'b0;
philpem@3 126 end else if (refresh_timer == 0) begin
philpem@3 127 // Refresh timer timed out, make a Refresh Request and reload the timer
philpem@3 128 refresh_req <= 1'b1;
philpem@12 129 refresh_timer <= TIME_REFRESH - 32'd1;
philpem@3 130 end else begin
philpem@3 131 // Otherwise just decrement the timer
philpem@3 132 refresh_timer <= refresh_timer - 32'd1;
philpem@3 133 end
philpem@3 134 end
philpem@3 135
philpem@4 136
philpem@4 137 /****
philpem@4 138 * Address decoder
philpem@4 139 ****/
philpem@4 140 wire [8:0] column_addr;
philpem@4 141 wire [11:0] row_addr;
philpem@4 142 wire [1:0] bank_addr;
philpem@4 143
philpem@7 144 // Convert a 23-bit linear address into an SDRAM address
philpem@4 145 assign column_addr = wb_adr_i[8:0];
philpem@4 146 assign bank_addr = wb_adr_i[10:9];
philpem@7 147 assign row_addr = wb_adr_i[22:11];
philpem@4 148
philpem@4 149
philpem@3 150 /****
philpem@0 151 * Finite State Machine
philpem@0 152 ****/
philpem@2 153 localparam ST_INIT1 = 32'd0;
philpem@2 154 localparam ST_INIT2 = 32'd1;
philpem@2 155 localparam ST_NOP1 = 32'd2;
philpem@2 156 localparam ST_PrechargeAll = 32'd3;
philpem@2 157 localparam ST_PrechargeAll_Wait = 32'd4;
philpem@2 158 localparam ST_AutoRefresh1 = 32'd5;
philpem@2 159 localparam ST_AutoRefresh1_Wait = 32'd6;
philpem@2 160 localparam ST_AutoRefresh2 = 32'd7;
philpem@2 161 localparam ST_AutoRefresh2_Wait = 32'd8;
philpem@2 162 localparam ST_LoadModeRegister = 32'd9;
philpem@2 163 localparam ST_LoadModeRegister_Wait = 32'd10;
philpem@3 164 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
philpem@3 165 localparam ST_Refresh = 32'd12;
philpem@3 166 localparam ST_Refresh_Wait = 32'd13;
philpem@7 167 localparam ST_Activate = 32'd30;
philpem@7 168 localparam ST_Activate_Wait = 32'd31;
philpem@7 169 localparam ST_Write = 32'd32;
philpem@7 170 localparam ST_Read = 32'd33;
philpem@7 171 localparam ST_Read_Wait = 32'd34;
philpem@7 172 localparam ST_Wait_Trp = 32'd35;
philpem@7 173 localparam ST_Ack = 32'd36;
philpem@7 174
philpem@0 175
philpem@0 176 reg [31:0] state;
philpem@0 177 always @(posedge wb_clk_i) begin
philpem@0 178 if (wb_rst_i) begin
philpem@0 179 // Initialise state machine and timer
philpem@0 180 state <= ST_INIT1;
philpem@0 181 timer <= 32'd0;
philpem@3 182
philpem@3 183 // Clear REFRESH ACK flag and disable refresh timer
philpem@3 184 refresh_ack <= 1'b0;
philpem@3 185 refresh_timer_en <= 1'b0;
philpem@0 186
philpem@0 187 // Initialisation state for SDRAM
philpem@0 188 sdram_cke <= 1'b0;
philpem@0 189 sdram_mode <= M_Inhibit;
philpem@0 190 sdram_addr <= 12'h000;
philpem@0 191 sdram_ba <= 2'b00;
philpem@0 192 sdram_dqm <= 4'b0000;
philpem@0 193 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 194 sdram_dq_r <= 32'd0;
philpem@0 195 end else begin
philpem@0 196 // timer logic
philpem@0 197 if (timer > 32'd0) begin
philpem@0 198 timer <= timer - 32'd1;
philpem@0 199 end
philpem@0 200
philpem@0 201 // state machine logic
philpem@0 202 case (state)
philpem@0 203 ST_INIT1: begin
philpem@0 204 // INIT1: Set up for initial power-up wait
philpem@0 205 state <= ST_INIT2;
philpem@0 206 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
philpem@0 207
philpem@0 208 // SDRAM state
philpem@0 209 sdram_cke <= 1'b0; // clock disabled
philpem@0 210 sdram_mode <= M_Inhibit;
philpem@0 211 sdram_addr <= 12'h000;
philpem@0 212 sdram_ba <= 2'b00;
philpem@0 213 sdram_dqm <= 4'b1111;
philpem@0 214 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 215 sdram_dq_r <= 32'd0;
philpem@0 216 end
philpem@0 217
philpem@0 218 ST_INIT2: begin
philpem@0 219 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
philpem@0 220 // the end of the power-up wait, then bring CKE high.
philpem@0 221 if (timer == 32'd0) begin
philpem@0 222 // Timer hit zero. Send a NOP.
philpem@2 223 state <= ST_NOP1;
philpem@1 224 end else if (timer < 32'd50) begin
philpem@0 225 // Timer value is more than zero but less than 50; CKE is on, but
philpem@0 226 // keep waiting for the timer to actually expire.
philpem@0 227 sdram_cke <= 1'b1;
philpem@0 228 state <= ST_INIT2;
philpem@0 229 end
philpem@0 230 sdram_mode <= M_Inhibit;
philpem@0 231 end
philpem@0 232
philpem@2 233 ST_NOP1: begin
philpem@2 234 // Apply one or more NOP commands to the SDRAM
philpem@2 235 sdram_mode <= M_Nop;
philpem@2 236 state <= ST_PrechargeAll;
philpem@2 237 end
philpem@2 238
philpem@2 239 ST_PrechargeAll: begin
philpem@2 240 // Precharge All, then wait T_rp (20ns)
philpem@2 241 sdram_mode <= M_PrechargeAll;
philpem@10 242 timer <= TIME_Trp - 32'd1;
philpem@2 243 state <= ST_PrechargeAll_Wait;
philpem@2 244 end
philpem@2 245
philpem@2 246 ST_PrechargeAll_Wait: begin
philpem@2 247 // Wait for T_rp after Precharge All
philpem@2 248 sdram_mode <= M_Nop;
philpem@2 249 if (timer == 32'd0) begin
philpem@2 250 // Timer hit zero. Continue
philpem@2 251 state <= ST_AutoRefresh1;
philpem@2 252 end
philpem@2 253 end
philpem@2 254
philpem@2 255 ST_AutoRefresh1: begin
philpem@2 256 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
philpem@2 257 sdram_mode <= M_AutoRefresh;
philpem@10 258 timer <= TIME_Trfc - 32'd1;
philpem@2 259 state <= ST_AutoRefresh1_Wait;
philpem@2 260 end
philpem@2 261
philpem@2 262 ST_AutoRefresh1_Wait: begin
philpem@2 263 // Wait for T_rfc
philpem@1 264 sdram_mode <= M_Nop;
philpem@2 265 if (timer == 32'd0) begin
philpem@2 266 // Timer hit zero. Continue
philpem@2 267 state <= ST_AutoRefresh2;
philpem@2 268 end
philpem@2 269 end
philpem@2 270
philpem@2 271 ST_AutoRefresh2: begin
philpem@2 272 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
philpem@2 273 sdram_mode <= M_AutoRefresh;
philpem@10 274 timer <= TIME_Trfc - 32'd1;
philpem@2 275 state <= ST_AutoRefresh2_Wait;
philpem@2 276 end
philpem@2 277
philpem@2 278 ST_AutoRefresh2_Wait: begin
philpem@2 279 // Wait for T_rfc
philpem@2 280 sdram_mode <= M_Nop;
philpem@2 281 if (timer == 32'd0) begin
philpem@2 282 // Timer hit zero. Continue
philpem@2 283 state <= ST_LoadModeRegister;
philpem@2 284 end
philpem@2 285 end
philpem@2 286
philpem@2 287 ST_LoadModeRegister: begin
philpem@2 288 // Load Mode Register
philpem@2 289 /**
philpem@2 290 * Mode register:
philpem@2 291 * - BS0,1 = 00 [RFU]
philpem@2 292 * - A11,10 = 00 [RFU]
philpem@2 293 * - A9 = 0 [WBL -- write burst length same as read burst length]
philpem@2 294 * - A8,7 = 00 [Test Mode off]
philpem@10 295 * - A6..4 = 010 [CAS Latency = 2 or 3 clocks, set above]
philpem@2 296 * - A3 = 0 [Burst type = sequential]
philpem@2 297 * - A2..0 = 000 [Burst length = 1 word]
philpem@2 298 */
philpem@2 299 sdram_ba <= 2'b00;
philpem@10 300 sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
philpem@2 301 sdram_mode <= M_LoadModeRegister;
philpem@2 302
philpem@2 303 // Wait T_mrd (2 clock cycles)
philpem@10 304 timer <= TIME_Tmrd - 32'd1;
philpem@2 305 state <= ST_LoadModeRegister_Wait;
philpem@2 306 end
philpem@2 307
philpem@2 308 ST_LoadModeRegister_Wait: begin
philpem@2 309 // Wait for LMR to complete
philpem@2 310 sdram_mode <= M_Nop;
philpem@2 311 sdram_ba <= 2'd0;
philpem@2 312 sdram_addr <= 12'd0;
philpem@2 313 if (timer == 32'd0) begin
philpem@2 314 // Timer hit zero. Continue
philpem@2 315 state <= ST_Spin;
philpem@2 316 end
philpem@2 317 end
philpem@2 318
philpem@2 319 ST_Spin: begin
philpem@3 320 // Enable refresh timer
philpem@3 321 refresh_timer_en <= 1'b1;
philpem@3 322
philpem@7 323 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
philpem@2 324 sdram_mode <= M_Inhibit;
philpem@3 325
philpem@9 326 // Check if a refresh is due (these have highest priority)
philpem@3 327 if (refresh_req) begin
philpem@3 328 // Refresh request received. Ack it and do a refresh.
philpem@3 329 refresh_ack <= 1'b1;
philpem@3 330 state <= ST_Refresh;
philpem@3 331 end else begin
philpem@7 332 if (wb_cyc_i & wb_stb_i) begin
philpem@7 333 // CYC and STB high. A Wishbone cycle just started.
philpem@7 334 state <= ST_Activate;
philpem@7 335 end
philpem@3 336 end
philpem@3 337 end
philpem@7 338
philpem@7 339 /////
philpem@7 340 // Refresh logic
philpem@7 341 /////
philpem@3 342
philpem@3 343 ST_Refresh: begin
philpem@3 344 // Refresh timer timed out; do a refresh run
philpem@3 345 // Start by clearing the ACK flag (which was set by the Spin state)
philpem@3 346 refresh_ack <= 1'b0;
philpem@3 347 // Tell the SDRAM to do a Refresh
philpem@3 348 sdram_mode <= M_AutoRefresh;
philpem@3 349 // Wait for T_rfc
philpem@10 350 timer <= TIME_Trfc;
philpem@3 351 state <= ST_Refresh_Wait;
philpem@3 352 end
philpem@3 353
philpem@3 354 ST_Refresh_Wait: begin
philpem@3 355 // Wait for T_rfc
philpem@3 356 sdram_mode <= M_Nop;
philpem@3 357 if (timer == 32'd0) begin
philpem@3 358 // Timer hit zero. Go back to spin state.
philpem@3 359 state <= ST_Spin;
philpem@3 360 end
philpem@0 361 end
philpem@7 362
philpem@7 363 //////
philpem@7 364 // R/W logic
philpem@7 365 //////
philpem@7 366 ST_Activate: begin
philpem@7 367 // Activate the required bank
philpem@4 368 sdram_mode <= M_BankActivate;
philpem@4 369 sdram_addr <= row_addr;
philpem@7 370 sdram_ba <= bank_addr;
philpem@10 371 timer <= TIME_Trcd - 32'd1;
philpem@7 372 state <= ST_Activate_Wait;
philpem@4 373 end
philpem@4 374
philpem@7 375 ST_Activate_Wait: begin
philpem@7 376 // Wait for T_rcd
philpem@4 377 sdram_mode <= M_Nop;
philpem@4 378 if (timer == 32'd0) begin
philpem@7 379 if (wb_we_i) begin
philpem@7 380 // Write cycle.
philpem@7 381 state <= ST_Write;
philpem@7 382 end else begin
philpem@7 383 // Read cycle
philpem@7 384 state <= ST_Read;
philpem@7 385 end
philpem@4 386 end
philpem@4 387 end
philpem@4 388
philpem@7 389 ST_Write: begin
philpem@7 390 // Write cycle handler
philpem@7 391 sdram_mode <= M_WritePrecharge;
philpem@7 392 sdram_addr <= column_addr;
philpem@7 393 sdram_dq_r <= wb_dat_i;
philpem@7 394 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
philpem@9 395 sdram_dqm <= ~wb_sel_i;
philpem@7 396
philpem@7 397 // Wait T_rp (20ns)
philpem@10 398 timer <= TIME_Trp - 32'd1;
philpem@7 399 state <= ST_Wait_Trp;
philpem@7 400 end
philpem@7 401
philpem@7 402 ST_Read: begin
philpem@7 403 // Read cycle handler
philpem@7 404 sdram_mode <= M_ReadPrecharge;
philpem@7 405 sdram_addr <= column_addr;
philpem@7 406 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 407 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
philpem@10 408 timer <= CAS_LATENCY - 32'd1; // CAS# Latency
philpem@7 409 state <= ST_Read_Wait;
philpem@4 410 end
philpem@4 411
philpem@7 412 ST_Read_Wait: begin
philpem@7 413 // Wait for CAS# latency
philpem@7 414 sdram_mode <= M_Nop;
philpem@7 415 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
philpem@4 416 if (timer == 32'd0) begin
philpem@7 417 // Latch data
philpem@7 418 wb_dat_o <= sdram_dq;
philpem@7 419 // Wait T_rp (20ns)
philpem@10 420 timer <= TIME_Trp - 32'd1;
philpem@7 421 state <= ST_Wait_Trp;
philpem@4 422 end
philpem@4 423 end
philpem@5 424
philpem@7 425 ST_Wait_Trp: begin
philpem@7 426 // Wait for T_rp, then ack
philpem@7 427 if (timer == 32'd0) begin
philpem@7 428 state <= ST_Ack;
philpem@7 429 end
philpem@4 430 end
philpem@4 431
philpem@7 432 ST_Ack: begin
philpem@7 433 // Ack the transfer to the WISHBONE host
philpem@7 434 sdram_mode <= M_Nop;
philpem@7 435 sdram_addr <= 32'd0;
philpem@7 436 sdram_dq_r <= 32'd0;
philpem@7 437 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 438 sdram_dqm <= 4'b1111; // mask off DQM
philpem@7 439 if (wb_cyc_i & wb_stb_i) begin
philpem@7 440 // CYC and STB high, ack the transfer
philpem@7 441 wb_ack_o <= 1'b1;
philpem@7 442 state <= ST_Ack;
philpem@7 443 end else begin
philpem@9 444 // CYC and STB low, go back and wait for another transaction
philpem@9 445 wb_ack_o <= 1'b0;
philpem@7 446 state <= ST_Spin;
philpem@4 447 end
philpem@4 448 end
philpem@0 449 endcase
philpem@0 450 end
philpem@0 451 end
philpem@0 452
philpem@0 453 endmodule