wb_sdram.v

Tue, 10 Aug 2010 18:35:50 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 18:35:50 +0100
changeset 8
b00018dfe8e5
parent 7
001f5282bff0
child 9
413ec22a27cd
permissions
-rw-r--r--

[wb_sdram] add drivers for unused WISHBONE i/os

philpem@0 1 /****************************************************************************
philpem@0 2 *
philpem@0 3 *
philpem@0 4 ****************************************************************************/
philpem@0 5
philpem@0 6 module wb_sdram (
philpem@0 7 // Clocks and resets
philpem@0 8 input wb_clk_i, // WISHBONE clock
philpem@0 9 input wb_rst_i, // WISHBONE reset
philpem@0 10
philpem@0 11 // WISHBONE bus
philpem@0 12 input [31:0] wb_adr_i, // WISHBONE address
philpem@0 13 input [31:0] wb_dat_i, // WISHBONE data in
philpem@0 14 output reg [31:0] wb_dat_o, // WISHBONE data out
philpem@0 15 input [3:0] wb_sel_i, // WISHBONE byte select
philpem@0 16 input wb_we_i, // WISHBONE write enable (R/#W)
philpem@0 17 input wb_cyc_i, // WISHBONE cycle
philpem@0 18 input wb_stb_i, // WISHBONE strobe
philpem@7 19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
philpem@0 20 output wb_err_o, // WISHBONE bus error
philpem@0 21 output wb_rty_o, // WISHBONE retry-later
philpem@0 22
philpem@0 23 // SDRAM
philpem@0 24 output reg sdram_cke, // SDRAM clock enable
philpem@0 25 output sdram_cs_n, // SDRAM chip select (active low)
philpem@0 26 output sdram_ras_n, // SDRAM row address strobe (active low)
philpem@0 27 output sdram_cas_n, // SDRAM column address strobe (active low)
philpem@0 28 output sdram_we_n, // SDRAM write enable (active low)
philpem@0 29 output [11:0] sdram_a, // SDRAM address
philpem@0 30 output reg [1:0] sdram_ba, // SDRAM bank address
philpem@0 31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
philpem@0 32 inout [31:0] sdram_dq, // SDRAM data bus
philpem@0 33
philpem@0 34 // Debugging
philpem@3 35 output /*reg*/ [2:0] debug // debug bits
philpem@0 36 );
philpem@0 37
philpem@0 38
philpem@0 39 /****
philpem@8 40 * WISHBONE status pins
philpem@8 41 ****/
philpem@8 42 // Can't raise bus errors
philpem@8 43 assign wb_err_o = 1'b0;
philpem@8 44 // Can't request retries
philpem@8 45 assign wb_rty_o = 1'b0;
philpem@8 46
philpem@8 47
philpem@8 48 /****
philpem@0 49 * SDRAM data output buffer
philpem@0 50 ****/
philpem@0 51 // OE=1 for output mode, 0 for input
philpem@0 52 reg sdram_dq_oe;
philpem@0 53 // SDRAM output register
philpem@0 54 reg [31:0] sdram_dq_r;
philpem@0 55 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
philpem@0 56
philpem@0 57
philpem@0 58
philpem@0 59 /****
philpem@0 60 * State timer
philpem@0 61 * This is used to ensure that the state machine abides by RAM timing
philpem@0 62 * restrictions.
philpem@0 63 ****/
philpem@0 64 reg [31:0] timer;
philpem@0 65
philpem@0 66
philpem@0 67 /****
philpem@0 68 * MODE logic
philpem@0 69 ****/
philpem@0 70 reg [5:0] sdram_mode;
philpem@0 71 reg [11:0] sdram_addr;
philpem@0 72 assign sdram_cs_n = sdram_mode[3];
philpem@0 73 assign sdram_ras_n = sdram_mode[2];
philpem@0 74 assign sdram_cas_n = sdram_mode[1];
philpem@0 75 assign sdram_we_n = sdram_mode[0];
philpem@0 76 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
philpem@0 77
philpem@0 78 // SDRAM chip instructions
philpem@0 79 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
philpem@0 80 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
philpem@0 81 localparam M_BankActivate = 6'b0X0011;
philpem@0 82 localparam M_PrechargeBank = 6'b100010;
philpem@0 83 localparam M_PrechargeAll = 6'b110010;
philpem@0 84 localparam M_Write = 6'b100100;
philpem@0 85 localparam M_WritePrecharge = 6'b110100;
philpem@0 86 localparam M_Read = 6'b100101;
philpem@0 87 localparam M_ReadPrecharge = 6'b110101;
philpem@2 88 localparam M_LoadModeRegister = 6'b0X0000;
philpem@0 89 localparam M_Nop = 6'b0X0111;
philpem@0 90 localparam M_BurstStop = 6'b0X0110;
philpem@0 91 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
philpem@0 92 localparam M_AutoRefresh = 6'b0X0001;
philpem@0 93
philpem@0 94
philpem@0 95 /****
philpem@3 96 * Refresh Timer
philpem@3 97 ****/
philpem@3 98 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
philpem@3 99 reg [31:0] refresh_timer;
philpem@3 100 reg refresh_req, refresh_ack, refresh_timer_en;
philpem@3 101 always @(posedge wb_clk_i) begin
philpem@3 102 if (wb_rst_i | !refresh_timer_en) begin
philpem@3 103 // Reset; clear timer, unset REFRESH REQUEST
philpem@3 104 refresh_req <= 1'b0;
philpem@3 105 refresh_timer <= REFRESH_INTERVAL;
philpem@3 106 end else if (refresh_ack) begin
philpem@3 107 // Refresh Ack, clear Refresh Request.
philpem@3 108 refresh_req <= 1'b0;
philpem@3 109 end else if (refresh_timer == 0) begin
philpem@3 110 // Refresh timer timed out, make a Refresh Request and reload the timer
philpem@3 111 refresh_req <= 1'b1;
philpem@3 112 refresh_timer <= REFRESH_INTERVAL;
philpem@3 113 end else begin
philpem@3 114 // Otherwise just decrement the timer
philpem@3 115 refresh_timer <= refresh_timer - 32'd1;
philpem@3 116 end
philpem@3 117 end
philpem@3 118
philpem@3 119 assign debug = { 1'b0, refresh_req, refresh_ack };
philpem@3 120
philpem@4 121
philpem@4 122 /****
philpem@4 123 * Address decoder
philpem@4 124 ****/
philpem@4 125 wire [8:0] column_addr;
philpem@4 126 wire [11:0] row_addr;
philpem@4 127 wire [1:0] bank_addr;
philpem@4 128
philpem@7 129 // Convert a 23-bit linear address into an SDRAM address
philpem@4 130 assign column_addr = wb_adr_i[8:0];
philpem@4 131 assign bank_addr = wb_adr_i[10:9];
philpem@7 132 assign row_addr = wb_adr_i[22:11];
philpem@4 133
philpem@4 134
philpem@3 135 /****
philpem@0 136 * Finite State Machine
philpem@0 137 ****/
philpem@2 138 localparam ST_INIT1 = 32'd0;
philpem@2 139 localparam ST_INIT2 = 32'd1;
philpem@2 140 localparam ST_NOP1 = 32'd2;
philpem@2 141 localparam ST_PrechargeAll = 32'd3;
philpem@2 142 localparam ST_PrechargeAll_Wait = 32'd4;
philpem@2 143 localparam ST_AutoRefresh1 = 32'd5;
philpem@2 144 localparam ST_AutoRefresh1_Wait = 32'd6;
philpem@2 145 localparam ST_AutoRefresh2 = 32'd7;
philpem@2 146 localparam ST_AutoRefresh2_Wait = 32'd8;
philpem@2 147 localparam ST_LoadModeRegister = 32'd9;
philpem@2 148 localparam ST_LoadModeRegister_Wait = 32'd10;
philpem@3 149 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
philpem@3 150 localparam ST_Refresh = 32'd12;
philpem@3 151 localparam ST_Refresh_Wait = 32'd13;
philpem@7 152 localparam ST_Activate = 32'd30;
philpem@7 153 localparam ST_Activate_Wait = 32'd31;
philpem@7 154 localparam ST_Write = 32'd32;
philpem@7 155 localparam ST_Read = 32'd33;
philpem@7 156 localparam ST_Read_Wait = 32'd34;
philpem@7 157 localparam ST_Wait_Trp = 32'd35;
philpem@7 158 localparam ST_Ack = 32'd36;
philpem@7 159
philpem@0 160
philpem@0 161 reg [31:0] state;
philpem@0 162 always @(posedge wb_clk_i) begin
philpem@0 163 if (wb_rst_i) begin
philpem@0 164 // Initialise state machine and timer
philpem@0 165 state <= ST_INIT1;
philpem@3 166 // debug <= 3'd0;
philpem@0 167 timer <= 32'd0;
philpem@3 168
philpem@3 169 // Clear REFRESH ACK flag and disable refresh timer
philpem@3 170 refresh_ack <= 1'b0;
philpem@3 171 refresh_timer_en <= 1'b0;
philpem@0 172
philpem@0 173 // Initialisation state for SDRAM
philpem@0 174 sdram_cke <= 1'b0;
philpem@0 175 sdram_mode <= M_Inhibit;
philpem@0 176 sdram_addr <= 12'h000;
philpem@0 177 sdram_ba <= 2'b00;
philpem@0 178 sdram_dqm <= 4'b0000;
philpem@0 179 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 180 sdram_dq_r <= 32'd0;
philpem@0 181 end else begin
philpem@0 182 // timer logic
philpem@0 183 if (timer > 32'd0) begin
philpem@0 184 timer <= timer - 32'd1;
philpem@0 185 end
philpem@0 186
philpem@0 187 // state machine logic
philpem@0 188 case (state)
philpem@0 189 ST_INIT1: begin
philpem@0 190 // INIT1: Set up for initial power-up wait
philpem@0 191 state <= ST_INIT2;
philpem@0 192 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
philpem@0 193
philpem@0 194 // SDRAM state
philpem@0 195 sdram_cke <= 1'b0; // clock disabled
philpem@0 196 sdram_mode <= M_Inhibit;
philpem@0 197 sdram_addr <= 12'h000;
philpem@0 198 sdram_ba <= 2'b00;
philpem@0 199 sdram_dqm <= 4'b1111;
philpem@0 200 sdram_dq_oe <= 1'b0; // data output disabled
philpem@0 201 sdram_dq_r <= 32'd0;
philpem@0 202 end
philpem@0 203
philpem@0 204 ST_INIT2: begin
philpem@0 205 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
philpem@0 206 // the end of the power-up wait, then bring CKE high.
philpem@0 207 if (timer == 32'd0) begin
philpem@0 208 // Timer hit zero. Send a NOP.
philpem@2 209 state <= ST_NOP1;
philpem@1 210 end else if (timer < 32'd50) begin
philpem@0 211 // Timer value is more than zero but less than 50; CKE is on, but
philpem@0 212 // keep waiting for the timer to actually expire.
philpem@0 213 sdram_cke <= 1'b1;
philpem@0 214 state <= ST_INIT2;
philpem@3 215 // debug <= 3'd1;
philpem@0 216 end
philpem@0 217 sdram_mode <= M_Inhibit;
philpem@0 218 end
philpem@0 219
philpem@2 220 ST_NOP1: begin
philpem@2 221 // Apply one or more NOP commands to the SDRAM
philpem@2 222 sdram_mode <= M_Nop;
philpem@2 223 state <= ST_PrechargeAll;
philpem@2 224 end
philpem@2 225
philpem@2 226 ST_PrechargeAll: begin
philpem@2 227 // Precharge All, then wait T_rp (20ns)
philpem@2 228 sdram_mode <= M_PrechargeAll;
philpem@2 229 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
philpem@2 230 state <= ST_PrechargeAll_Wait;
philpem@2 231 end
philpem@2 232
philpem@2 233 ST_PrechargeAll_Wait: begin
philpem@2 234 // Wait for T_rp after Precharge All
philpem@2 235 sdram_mode <= M_Nop;
philpem@2 236 if (timer == 32'd0) begin
philpem@2 237 // Timer hit zero. Continue
philpem@2 238 state <= ST_AutoRefresh1;
philpem@2 239 end
philpem@2 240 end
philpem@2 241
philpem@2 242 ST_AutoRefresh1: begin
philpem@2 243 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
philpem@2 244 sdram_mode <= M_AutoRefresh;
philpem@2 245 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
philpem@2 246 state <= ST_AutoRefresh1_Wait;
philpem@2 247 end
philpem@2 248
philpem@2 249 ST_AutoRefresh1_Wait: begin
philpem@2 250 // Wait for T_rfc
philpem@1 251 sdram_mode <= M_Nop;
philpem@2 252 if (timer == 32'd0) begin
philpem@2 253 // Timer hit zero. Continue
philpem@2 254 state <= ST_AutoRefresh2;
philpem@2 255 end
philpem@2 256 end
philpem@2 257
philpem@2 258 ST_AutoRefresh2: begin
philpem@2 259 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
philpem@2 260 sdram_mode <= M_AutoRefresh;
philpem@2 261 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
philpem@2 262 state <= ST_AutoRefresh2_Wait;
philpem@2 263 end
philpem@2 264
philpem@2 265 ST_AutoRefresh2_Wait: begin
philpem@2 266 // Wait for T_rfc
philpem@2 267 sdram_mode <= M_Nop;
philpem@2 268 if (timer == 32'd0) begin
philpem@2 269 // Timer hit zero. Continue
philpem@2 270 state <= ST_LoadModeRegister;
philpem@2 271 end
philpem@2 272 end
philpem@2 273
philpem@2 274 ST_LoadModeRegister: begin
philpem@2 275 // Load Mode Register
philpem@2 276 /**
philpem@2 277 * Mode register:
philpem@2 278 * - BS0,1 = 00 [RFU]
philpem@2 279 * - A11,10 = 00 [RFU]
philpem@2 280 * - A9 = 0 [WBL -- write burst length same as read burst length]
philpem@2 281 * - A8,7 = 00 [Test Mode off]
philpem@2 282 * - A6..4 = 010 [CAS Latency = 2 clocks]
philpem@2 283 * - A3 = 0 [Burst type = sequential]
philpem@2 284 * - A2..0 = 000 [Burst length = 1 word]
philpem@2 285 */
philpem@2 286 sdram_ba <= 2'b00;
philpem@2 287 sdram_addr <= 12'b00_0_00_010_000;
philpem@2 288 sdram_mode <= M_LoadModeRegister;
philpem@2 289
philpem@2 290 // Wait T_mrd (2 clock cycles)
philpem@2 291 timer <= 32'd1; // (2cy)-1 ---> TIMER HERE
philpem@2 292 state <= ST_LoadModeRegister_Wait;
philpem@2 293 end
philpem@2 294
philpem@2 295 ST_LoadModeRegister_Wait: begin
philpem@2 296 // Wait for LMR to complete
philpem@2 297 sdram_mode <= M_Nop;
philpem@2 298 sdram_ba <= 2'd0;
philpem@2 299 sdram_addr <= 12'd0;
philpem@2 300 if (timer == 32'd0) begin
philpem@2 301 // Timer hit zero. Continue
philpem@2 302 state <= ST_Spin;
philpem@2 303 end
philpem@2 304 end
philpem@2 305
philpem@2 306 ST_Spin: begin
philpem@3 307 // Enable refresh timer
philpem@3 308 refresh_timer_en <= 1'b1;
philpem@3 309
philpem@7 310 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
philpem@2 311 sdram_mode <= M_Inhibit;
philpem@7 312
philpem@7 313 // Clear the WISHBONE Ack flag -- NOTE: is this required?
philpem@7 314 wb_ack_o <= 1'b0;
philpem@3 315
philpem@3 316 if (refresh_req) begin
philpem@3 317 // Refresh request received. Ack it and do a refresh.
philpem@3 318 refresh_ack <= 1'b1;
philpem@3 319 state <= ST_Refresh;
philpem@3 320 end else begin
philpem@4 321 //state <= ST_Spin; // NOTE: turned off to run a ram test...
philpem@7 322 //state <= ST_Test_Activate;
philpem@7 323 if (wb_cyc_i & wb_stb_i) begin
philpem@7 324 // CYC and STB high. A Wishbone cycle just started.
philpem@7 325 state <= ST_Activate;
philpem@7 326 end
philpem@3 327 end
philpem@3 328 end
philpem@7 329
philpem@7 330 /////
philpem@7 331 // Refresh logic
philpem@7 332 /////
philpem@3 333
philpem@3 334 ST_Refresh: begin
philpem@3 335 // Refresh timer timed out; do a refresh run
philpem@3 336 // Start by clearing the ACK flag (which was set by the Spin state)
philpem@3 337 refresh_ack <= 1'b0;
philpem@3 338 // Tell the SDRAM to do a Refresh
philpem@3 339 sdram_mode <= M_AutoRefresh;
philpem@3 340 // Wait for T_rfc
philpem@3 341 timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE
philpem@3 342 state <= ST_Refresh_Wait;
philpem@3 343 end
philpem@3 344
philpem@3 345 ST_Refresh_Wait: begin
philpem@3 346 // Wait for T_rfc
philpem@3 347 sdram_mode <= M_Nop;
philpem@3 348 if (timer == 32'd0) begin
philpem@3 349 // Timer hit zero. Go back to spin state.
philpem@3 350 state <= ST_Spin;
philpem@3 351 end
philpem@0 352 end
philpem@7 353
philpem@7 354 //////
philpem@7 355 // R/W logic
philpem@7 356 //////
philpem@7 357 ST_Activate: begin
philpem@7 358 // Activate the required bank
philpem@4 359 sdram_mode <= M_BankActivate;
philpem@4 360 sdram_addr <= row_addr;
philpem@7 361 sdram_ba <= bank_addr;
philpem@7 362 timer <= 32'd0; // Wait T_rcd (20ns ideally, here 40ns) ---> TIMER HERE
philpem@7 363 state <= ST_Activate_Wait;
philpem@4 364 end
philpem@4 365
philpem@7 366 ST_Activate_Wait: begin
philpem@7 367 // Wait for T_rcd
philpem@4 368 sdram_mode <= M_Nop;
philpem@4 369 if (timer == 32'd0) begin
philpem@7 370 if (wb_we_i) begin
philpem@7 371 // Write cycle.
philpem@7 372 state <= ST_Write;
philpem@7 373 end else begin
philpem@7 374 // Read cycle
philpem@7 375 state <= ST_Read;
philpem@7 376 end
philpem@4 377 end
philpem@4 378 end
philpem@4 379
philpem@7 380 ST_Write: begin
philpem@7 381 // Write cycle handler
philpem@7 382 sdram_mode <= M_WritePrecharge;
philpem@7 383 sdram_addr <= column_addr;
philpem@7 384 sdram_dq_r <= wb_dat_i;
philpem@7 385 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
philpem@7 386 sdram_dqm <= 4'b0000; // TODO: use WB_SEL_I to set these
philpem@7 387
philpem@7 388 // Wait T_rp (20ns)
philpem@7 389 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
philpem@7 390 state <= ST_Wait_Trp;
philpem@7 391 end
philpem@7 392
philpem@7 393 ST_Read: begin
philpem@7 394 // Read cycle handler
philpem@7 395 sdram_mode <= M_ReadPrecharge;
philpem@7 396 sdram_addr <= column_addr;
philpem@7 397 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 398 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
philpem@7 399 timer <= 32'd2 - 32'd1; // CAS# Latency ---> TIMER HERE
philpem@7 400 state <= ST_Read_Wait;
philpem@4 401 end
philpem@4 402
philpem@7 403 ST_Read_Wait: begin
philpem@7 404 // Wait for CAS# latency
philpem@7 405 sdram_mode <= M_Nop;
philpem@7 406 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
philpem@4 407 if (timer == 32'd0) begin
philpem@7 408 // Latch data
philpem@7 409 wb_dat_o <= sdram_dq;
philpem@7 410 // Wait T_rp (20ns)
philpem@7 411 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
philpem@7 412 state <= ST_Wait_Trp;
philpem@4 413 end
philpem@4 414 end
philpem@5 415
philpem@7 416 ST_Wait_Trp: begin
philpem@7 417 // Wait for T_rp, then ack
philpem@7 418 if (timer == 32'd0) begin
philpem@7 419 state <= ST_Ack;
philpem@7 420 end
philpem@4 421 end
philpem@4 422
philpem@7 423 ST_Ack: begin
philpem@7 424 // Ack the transfer to the WISHBONE host
philpem@7 425 sdram_mode <= M_Nop;
philpem@7 426 sdram_addr <= 32'd0;
philpem@7 427 sdram_dq_r <= 32'd0;
philpem@7 428 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
philpem@7 429 sdram_dqm <= 4'b1111; // mask off DQM
philpem@7 430 if (wb_cyc_i & wb_stb_i) begin
philpem@7 431 // CYC and STB high, ack the transfer
philpem@7 432 wb_ack_o <= 1'b1;
philpem@7 433 state <= ST_Ack;
philpem@7 434 end else begin
philpem@7 435 // CYC and STB low, back to the start again...
philpem@7 436 state <= ST_Spin;
philpem@4 437 end
philpem@4 438 end
philpem@0 439 endcase
philpem@0 440 end
philpem@0 441 end
philpem@0 442
philpem@0 443 endmodule