wb_sdram.v

changeset 17
ac979332d5fd
parent 16
49f3a5bd860e
child 18
275105a6a36b
     1.1 --- a/wb_sdram.v	Wed Aug 11 01:19:03 2010 +0100
     1.2 +++ b/wb_sdram.v	Wed Aug 18 14:10:48 2010 +0100
     1.3 @@ -1,38 +1,40 @@
     1.4 -	/****************************************************************************
     1.5 +/****************************************************************************
     1.6   *
     1.7   *
     1.8   ****************************************************************************/
     1.9   
    1.10 -module wb_sdram (
    1.11 +module wb_sdram #(
    1.12 +	parameter	DATA_BITS				= 32,				// Width of SDRAM data bus
    1.13 +	parameter	COLADDR_BITS			= 9,				// Number of SDRAM Column Address bits
    1.14 +	parameter	BANKADDR_BITS			= 2,				// Number of SDRAM Bank Address bits
    1.15 +	parameter	ROWADDR_BITS			= 12				// Number of SDRAM Row Address bits
    1.16 +) (
    1.17  	// Clocks and resets
    1.18 -	input						wb_clk_i,			// WISHBONE clock
    1.19 -	input						wb_rst_i,			// WISHBONE reset
    1.20 +	input										wb_clk_i,		// WISHBONE clock
    1.21 +	input										wb_rst_i,		// WISHBONE reset
    1.22  
    1.23  	// WISHBONE bus
    1.24 -	input			[31:0]	wb_adr_i,			// WISHBONE address
    1.25 -	input			[31:0]	wb_dat_i,			// WISHBONE data in
    1.26 -	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
    1.27 -	input			[3:0]		wb_sel_i,			// WISHBONE byte select
    1.28 -	input						wb_we_i,				// WISHBONE write enable (R/#W)
    1.29 -	input						wb_cyc_i,			// WISHBONE cycle
    1.30 -	input						wb_stb_i,			// WISHBONE strobe
    1.31 -	output reg				wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
    1.32 -	output					wb_err_o,			// WISHBONE bus error
    1.33 -	output					wb_rty_o,			// WISHBONE retry-later
    1.34 +	input			[31:0]					wb_adr_i,		// WISHBONE address
    1.35 +	input			[DATA_BITS-1:0]		wb_dat_i,		// WISHBONE data in
    1.36 +	output reg	[DATA_BITS-1:0]		wb_dat_o,		// WISHBONE data out
    1.37 +	input			[(DATA_BITS/4)-1:0]	wb_sel_i,		// WISHBONE byte select
    1.38 +	input										wb_we_i,			// WISHBONE write enable (R/#W)
    1.39 +	input										wb_cyc_i,		// WISHBONE cycle
    1.40 +	input										wb_stb_i,		// WISHBONE strobe
    1.41 +	output reg								wb_ack_o,		// WISHBONE cycle acknowledge (data available, DTACK)
    1.42 +	output									wb_err_o,		// WISHBONE bus error
    1.43 +	output									wb_rty_o,		// WISHBONE retry-later
    1.44  	
    1.45  	// SDRAM
    1.46 -	output reg				sdram_cke,			// SDRAM clock enable
    1.47 -	output					sdram_cs_n,			// SDRAM chip select (active low)
    1.48 -	output					sdram_ras_n,		// SDRAM row address strobe (active low)
    1.49 -	output					sdram_cas_n,		// SDRAM column address strobe (active low)
    1.50 -	output					sdram_we_n,			// SDRAM write enable (active low)
    1.51 -	output		[11:0]	sdram_a,				// SDRAM address
    1.52 -	output reg	[1:0]		sdram_ba,			// SDRAM bank address
    1.53 -	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
    1.54 -	inout			[31:0]	sdram_dq,			// SDRAM data bus
    1.55 -
    1.56 -	// Debugging
    1.57 -	output /*reg*/	[2:0]		debug					// debug bits
    1.58 +	output reg								sdram_cke,		// SDRAM clock enable
    1.59 +	output									sdram_cs_n,		// SDRAM chip select (active low)
    1.60 +	output									sdram_ras_n,	// SDRAM row address strobe (active low)
    1.61 +	output									sdram_cas_n,	// SDRAM column address strobe (active low)
    1.62 +	output									sdram_we_n,		// SDRAM write enable (active low)
    1.63 +	output		[ROWADDR_BITS-1:0]	sdram_a,			// SDRAM address
    1.64 +	output reg	[BANKADDR_BITS-1:0]	sdram_ba,		// SDRAM bank address
    1.65 +	output reg	[(DATA_BITS/4)-1:0]	sdram_dqm,		// SDRAM data mask (OE#; 0=active, 1=disabled)
    1.66 +	inout			[DATA_BITS-1:0]		sdram_dq			// SDRAM data bus
    1.67  );
    1.68  
    1.69  
    1.70 @@ -83,8 +85,6 @@
    1.71  assign wb_err_o = 1'b0;
    1.72  // Can't request retries
    1.73  assign wb_rty_o = 1'b0;
    1.74 -// Lock DEBUG pins low
    1.75 -assign debug = 3'd0;
    1.76  
    1.77  
    1.78  /****
    1.79 @@ -93,8 +93,8 @@
    1.80  // OE=1 for output mode, 0 for input
    1.81  reg sdram_dq_oe;
    1.82  // SDRAM output register
    1.83 -reg [31:0] sdram_dq_r;
    1.84 -assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    1.85 +reg [DATA_BITS-1:0] sdram_dq_r;
    1.86 +assign sdram_dq = sdram_dq_oe ? sdram_dq_r : {DATA_BITS{1'bZ}};
    1.87  
    1.88  
    1.89  /****
    1.90 @@ -160,14 +160,14 @@
    1.91  /****
    1.92   * Address decoder
    1.93   ****/
    1.94 -wire [8:0] column_addr;
    1.95 -wire [11:0] row_addr;
    1.96 -wire [1:0] bank_addr;
    1.97 +wire [COLADDR_BITS-1:0] column_addr;
    1.98 +wire [ROWADDR_BITS-1:0] row_addr;
    1.99 +wire [BANKADDR_BITS-1:0] bank_addr;
   1.100  
   1.101  // Convert a 23-bit linear address into an SDRAM address
   1.102 -assign column_addr	= wb_adr_i[8:0];
   1.103 -assign bank_addr		= wb_adr_i[10:9];
   1.104 -assign row_addr		= wb_adr_i[22:11];
   1.105 +assign column_addr	= wb_adr_i[COLADDR_BITS-1:0];
   1.106 +assign bank_addr		= wb_adr_i[COLADDR_BITS+BANKADDR_BITS-1:COLADDR_BITS];
   1.107 +assign row_addr		= wb_adr_i[COLADDR_BITS+BANKADDR_BITS+ROWADDR_BITS-1:COLADDR_BITS+BANKADDR_BITS];
   1.108  
   1.109  
   1.110  /****
   1.111 @@ -210,11 +210,11 @@
   1.112  		// Initialisation state for SDRAM
   1.113  		sdram_cke	<= 1'b0;
   1.114  		sdram_mode	<= M_Inhibit;
   1.115 -		sdram_addr	<= 12'h000;
   1.116 -		sdram_ba		<= 2'b00;
   1.117 -		sdram_dqm	<= 4'b0000;
   1.118 -		sdram_dq_oe	<= 1'b0;			// data output disabled
   1.119 -		sdram_dq_r	<= 32'd0;
   1.120 +		sdram_addr	<= 0;
   1.121 +		sdram_ba		<= 0;
   1.122 +		sdram_dqm	<= 0;
   1.123 +		sdram_dq_oe	<= 0;				// data output disabled
   1.124 +		sdram_dq_r	<= 0;
   1.125  	end else begin
   1.126  		// timer logic
   1.127  		if (timer > 32'd0) begin
   1.128 @@ -231,11 +231,11 @@
   1.129  					// SDRAM state
   1.130  					sdram_cke	<= 1'b0;			// clock disabled
   1.131  					sdram_mode	<= M_Inhibit;
   1.132 -					sdram_addr	<= 12'h000;
   1.133 -					sdram_ba		<= 2'b00;
   1.134 -					sdram_dqm	<= 4'b1111;
   1.135 -					sdram_dq_oe	<= 1'b0;			// data output disabled
   1.136 -					sdram_dq_r	<= 32'd0;
   1.137 +					sdram_addr	<= 0;
   1.138 +					sdram_ba		<= 0;
   1.139 +					sdram_dqm	<= {(DATA_BITS/4){1'b1}};
   1.140 +					sdram_dq_oe	<= 0;				// data output disabled
   1.141 +					sdram_dq_r	<= 0;
   1.142  				end
   1.143  				
   1.144  			ST_INIT2: begin
   1.145 @@ -319,7 +319,7 @@
   1.146  					 *   - A3     = 0   [Burst type = sequential]
   1.147  					 *   - A2..0  = 000 [Burst length = 1 word]
   1.148  					 */
   1.149 -					sdram_ba <= 2'b00;
   1.150 +					sdram_ba <= 0;
   1.151  					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
   1.152  					sdram_mode <= M_LoadModeRegister;
   1.153  
   1.154 @@ -331,8 +331,8 @@
   1.155  			ST_LoadModeRegister_Wait: begin
   1.156  					// Wait for LMR to complete
   1.157  					sdram_mode <= M_Nop;
   1.158 -					sdram_ba <= 2'd0;
   1.159 -					sdram_addr <= 12'd0;
   1.160 +					sdram_ba <= 0;
   1.161 +					sdram_addr <= 0;
   1.162  					if (timer == 32'd0) begin
   1.163  						// Timer hit zero. Continue
   1.164  						state <= ST_Spin;
   1.165 @@ -413,8 +413,8 @@
   1.166  					// Write cycle handler
   1.167  					sdram_mode	<= M_WritePrecharge;
   1.168  					sdram_addr	<= column_addr;
   1.169 -					sdram_dq_r	<= wb_dat_i;
   1.170 -					sdram_dq_oe	<= 1'b1;		// FPGA drives the DQ bus
   1.171 +					sdram_dq_r	<= 0;
   1.172 +					sdram_dq_oe	<= 1;			// FPGA drives the DQ bus
   1.173  					sdram_dqm	<= ~wb_sel_i;
   1.174  					
   1.175  					// Wait T_rp (20ns)
   1.176 @@ -426,8 +426,8 @@
   1.177  					// Read cycle handler
   1.178  					sdram_mode	<= M_ReadPrecharge;
   1.179  					sdram_addr	<= column_addr;
   1.180 -					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   1.181 -					sdram_dqm	<= 4'b0000;	// Grab all the data (it's just easier that way...)
   1.182 +					sdram_dq_oe	<= 0;			// SDRAM drives the DQ bus
   1.183 +					sdram_dqm	<= 0;			// Grab all the data (easier than playing with WB_SEL...)
   1.184  					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
   1.185  					state <= ST_Read_Wait;
   1.186  				end
   1.187 @@ -435,7 +435,7 @@
   1.188  			ST_Read_Wait: begin
   1.189  					// Wait for CAS# latency
   1.190  					sdram_mode	<= M_Nop;
   1.191 -					sdram_dqm	<= 4'b1111;	// Make SDRAM DQ bus float
   1.192 +					sdram_dqm	<= {(DATA_BITS/4){1'b1}};	// Make SDRAM DQ bus float
   1.193  					if (timer == 32'd0) begin
   1.194  						// Latch data
   1.195  						wb_dat_o <= sdram_dq;
   1.196 @@ -455,10 +455,10 @@
   1.197  			ST_Ack: begin
   1.198  					// Ack the transfer to the WISHBONE host
   1.199  					sdram_mode	<= M_Nop;
   1.200 -					sdram_addr	<= 32'd0;
   1.201 -					sdram_dq_r	<= 32'd0;
   1.202 -					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   1.203 -					sdram_dqm	<= 4'b1111;	// mask off DQM
   1.204 +					sdram_addr	<= 0;
   1.205 +					sdram_dq_r	<= 0;
   1.206 +					sdram_dq_oe	<= 0;			// SDRAM drives the DQ bus
   1.207 +					sdram_dqm	<= {(DATA_BITS/4){1'b1}};	// mask off DQM
   1.208  					if (wb_cyc_i & wb_stb_i) begin
   1.209  						// CYC and STB high, ack the transfer
   1.210  						wb_ack_o		<= 1'b1;