wb_sdram.v

changeset 8
b00018dfe8e5
parent 7
001f5282bff0
child 9
413ec22a27cd
     1.1 --- a/wb_sdram.v	Tue Aug 10 18:33:25 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 18:35:50 2010 +0100
     1.3 @@ -37,6 +37,15 @@
     1.4  
     1.5  
     1.6  /****
     1.7 + * WISHBONE status pins
     1.8 + ****/
     1.9 +// Can't raise bus errors
    1.10 +assign wb_err_o = 1'b0;
    1.11 +// Can't request retries
    1.12 +assign wb_rty_o = 1'b0;
    1.13 +
    1.14 +
    1.15 +/****
    1.16   * SDRAM data output buffer
    1.17   ****/
    1.18  // OE=1 for output mode, 0 for input