wb_sdram.v

Tue, 10 Aug 2010 12:58:34 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 12:58:34 +0100
changeset 1
05af11892ed8
parent 0
f797831bb66d
child 2
ceaa61ebf8a2
permissions
-rw-r--r--

make spinstate more noticeable on LA, fix CKE init timer

cke init timer was running 1cy longer than it should have

     1 /****************************************************************************
     2  *
     3  *
     4  ****************************************************************************/
     6 module wb_sdram (
     7 	// Clocks and resets
     8 	input						wb_clk_i,			// WISHBONE clock
     9 	input						wb_rst_i,			// WISHBONE reset
    11 	// WISHBONE bus
    12 	input			[31:0]	wb_adr_i,			// WISHBONE address
    13 	input			[31:0]	wb_dat_i,			// WISHBONE data in
    14 	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
    15 	input			[3:0]		wb_sel_i,			// WISHBONE byte select
    16 	input						wb_we_i,				// WISHBONE write enable (R/#W)
    17 	input						wb_cyc_i,			// WISHBONE cycle
    18 	input						wb_stb_i,			// WISHBONE strobe
    19 	output					wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
    20 	output					wb_err_o,			// WISHBONE bus error
    21 	output					wb_rty_o,			// WISHBONE retry-later
    23 	// SDRAM
    24 	output reg				sdram_cke,			// SDRAM clock enable
    25 	output					sdram_cs_n,			// SDRAM chip select (active low)
    26 	output					sdram_ras_n,		// SDRAM row address strobe (active low)
    27 	output					sdram_cas_n,		// SDRAM column address strobe (active low)
    28 	output					sdram_we_n,			// SDRAM write enable (active low)
    29 	output		[11:0]	sdram_a,				// SDRAM address
    30 	output reg	[1:0]		sdram_ba,			// SDRAM bank address
    31 	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
    32 	inout			[31:0]	sdram_dq,			// SDRAM data bus
    34 	// Debugging
    35 	output reg	[2:0]		debug					// debug bits
    36 );
    39 /****
    40  * SDRAM data output buffer
    41  ****/
    42 // OE=1 for output mode, 0 for input
    43 reg sdram_dq_oe;
    44 // SDRAM output register
    45 reg [31:0] sdram_dq_r;
    46 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    50 /****
    51  * State timer
    52  * This is used to ensure that the state machine abides by RAM timing
    53  * restrictions.
    54  ****/
    55 reg [31:0] timer;
    58 /****
    59  * MODE logic
    60  ****/
    61 reg  [5:0]  sdram_mode;
    62 reg  [11:0]	sdram_addr;
    63 assign sdram_cs_n		= sdram_mode[3];
    64 assign sdram_ras_n	= sdram_mode[2];
    65 assign sdram_cas_n	= sdram_mode[1];
    66 assign sdram_we_n		= sdram_mode[0];
    67 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
    69 // SDRAM chip instructions
    70 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
    71 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
    72 localparam M_BankActivate		= 6'b0X0011;
    73 localparam M_PrechargeBank		= 6'b100010;
    74 localparam M_PrechargeAll		= 6'b110010;
    75 localparam M_Write				= 6'b100100;
    76 localparam M_WritePrecharge	= 6'b110100;
    77 localparam M_Read					= 6'b100101;
    78 localparam M_ReadPrecharge		= 6'b110101;
    79 localparam M_ModeRegister		= 6'b0X0000;
    80 localparam M_Nop					= 6'b0X0111;
    81 localparam M_BurstStop			= 6'b0X0110;
    82 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
    83 localparam M_AutoRefresh		= 6'b0X0001;
    86 /****
    87  * Finite State Machine
    88  ****/
    89 localparam	ST_INIT1			= 32'd0;
    90 localparam	ST_INIT2			= 32'd1;
    91 localparam	ST_NOP			= 32'd999;
    93 reg [31:0] state;
    94 always @(posedge wb_clk_i) begin
    95 	if (wb_rst_i) begin
    96 		// Initialise state machine and timer
    97 		state <= ST_INIT1;
    98 		debug <= 3'd0;
    99 		timer <= 32'd0;
   101 		// Initialisation state for SDRAM
   102 		sdram_cke	<= 1'b0;
   103 		sdram_mode	<= M_Inhibit;
   104 		sdram_addr	<= 12'h000;
   105 		sdram_ba		<= 2'b00;
   106 		sdram_dqm	<= 4'b0000;
   107 		sdram_dq_oe	<= 1'b0;			// data output disabled
   108 		sdram_dq_r	<= 32'd0;
   109 	end else begin
   110 		// timer logic
   111 		if (timer > 32'd0) begin
   112 			timer <= timer - 32'd1;
   113 		end
   115 		// state machine logic
   116 		case (state)
   117 			ST_INIT1: begin
   118 					// INIT1: Set up for initial power-up wait
   119 					state <= ST_INIT2;
   120 					timer <= 32'd50_000;		// TODO: dependent on core clock rate. Needs to be >= 100us
   122 					// SDRAM state
   123 					sdram_cke	<= 1'b0;			// clock disabled
   124 					sdram_mode	<= M_Inhibit;
   125 					sdram_addr	<= 12'h000;
   126 					sdram_ba		<= 2'b00;
   127 					sdram_dqm	<= 4'b1111;
   128 					sdram_dq_oe	<= 1'b0;			// data output disabled
   129 					sdram_dq_r	<= 32'd0;
   130 				end
   132 			ST_INIT2: begin
   133 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
   134 					// the end of the power-up wait, then bring CKE high.
   135 					if (timer == 32'd0) begin
   136 						// Timer hit zero. Send a NOP.
   137 						state <= ST_NOP;
   138 					end else if (timer < 32'd50) begin
   139 						// Timer value is more than zero but less than 50; CKE is on, but
   140 						// keep waiting for the timer to actually expire.
   141 						sdram_cke	<= 1'b1;
   142 						state			<= ST_INIT2;
   143 						debug <= 3'd1;
   144 					end
   145 					sdram_mode <= M_Inhibit;
   146 				end
   148 			ST_NOP: begin
   149 					// Spinstate. Hold SDRAM in NOP.
   150 					debug <= 3'd7;
   151 					sdram_mode <= M_Nop;
   152 					state <= ST_NOP;
   153 				end
   154 		endcase
   155 	end
   156 end
   158 endmodule