Tue, 10 Aug 2010 22:11:51 +0100
[wb_sdram] parameterise timing and CAS latency
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * Timer values
41 ****/
42 // CAS latency -- either 2 or 3
43 parameter CAS_LATENCY = 3'd2;
44 // T_rp ==> 20ns
45 parameter TIME_Trp = 32'd1;
46 // T_rcd ==> 20ns
47 parameter TIME_Trcd = 32'd1;
48 // T_rfc (a.k.a. T_rc) ==> 70ns
49 parameter TIME_Trfc = 32'd2;
50 // T_mrd ==> 2 clock cycles
51 parameter TIME_Tmrd = 32'd2;
54 /****
55 * WISHBONE status pins
56 ****/
57 // Can't raise bus errors
58 assign wb_err_o = 1'b0;
59 // Can't request retries
60 assign wb_rty_o = 1'b0;
63 /****
64 * SDRAM data output buffer
65 ****/
66 // OE=1 for output mode, 0 for input
67 reg sdram_dq_oe;
68 // SDRAM output register
69 reg [31:0] sdram_dq_r;
70 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
74 /****
75 * State timer
76 * This is used to ensure that the state machine abides by RAM timing
77 * restrictions.
78 ****/
79 reg [31:0] timer;
82 /****
83 * MODE logic
84 ****/
85 reg [5:0] sdram_mode;
86 reg [11:0] sdram_addr;
87 assign sdram_cs_n = sdram_mode[3];
88 assign sdram_ras_n = sdram_mode[2];
89 assign sdram_cas_n = sdram_mode[1];
90 assign sdram_we_n = sdram_mode[0];
91 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
93 // SDRAM chip instructions
94 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
95 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
96 localparam M_BankActivate = 6'b0X0011;
97 localparam M_PrechargeBank = 6'b100010;
98 localparam M_PrechargeAll = 6'b110010;
99 localparam M_Write = 6'b100100;
100 localparam M_WritePrecharge = 6'b110100;
101 localparam M_Read = 6'b100101;
102 localparam M_ReadPrecharge = 6'b110101;
103 localparam M_LoadModeRegister = 6'b0X0000;
104 localparam M_Nop = 6'b0X0111;
105 localparam M_BurstStop = 6'b0X0110;
106 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
107 localparam M_AutoRefresh = 6'b0X0001;
110 /****
111 * Refresh Timer
112 ****/
113 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
114 reg [31:0] refresh_timer;
115 reg refresh_req, refresh_ack, refresh_timer_en;
116 always @(posedge wb_clk_i) begin
117 if (wb_rst_i | !refresh_timer_en) begin
118 // Reset; clear timer, unset REFRESH REQUEST
119 refresh_req <= 1'b0;
120 refresh_timer <= REFRESH_INTERVAL;
121 end else if (refresh_ack) begin
122 // Refresh Ack, clear Refresh Request.
123 refresh_req <= 1'b0;
124 end else if (refresh_timer == 0) begin
125 // Refresh timer timed out, make a Refresh Request and reload the timer
126 refresh_req <= 1'b1;
127 refresh_timer <= REFRESH_INTERVAL;
128 end else begin
129 // Otherwise just decrement the timer
130 refresh_timer <= refresh_timer - 32'd1;
131 end
132 end
134 assign debug = { 1'b0, refresh_req, refresh_ack };
137 /****
138 * Address decoder
139 ****/
140 wire [8:0] column_addr;
141 wire [11:0] row_addr;
142 wire [1:0] bank_addr;
144 // Convert a 23-bit linear address into an SDRAM address
145 assign column_addr = wb_adr_i[8:0];
146 assign bank_addr = wb_adr_i[10:9];
147 assign row_addr = wb_adr_i[22:11];
150 /****
151 * Finite State Machine
152 ****/
153 localparam ST_INIT1 = 32'd0;
154 localparam ST_INIT2 = 32'd1;
155 localparam ST_NOP1 = 32'd2;
156 localparam ST_PrechargeAll = 32'd3;
157 localparam ST_PrechargeAll_Wait = 32'd4;
158 localparam ST_AutoRefresh1 = 32'd5;
159 localparam ST_AutoRefresh1_Wait = 32'd6;
160 localparam ST_AutoRefresh2 = 32'd7;
161 localparam ST_AutoRefresh2_Wait = 32'd8;
162 localparam ST_LoadModeRegister = 32'd9;
163 localparam ST_LoadModeRegister_Wait = 32'd10;
164 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
165 localparam ST_Refresh = 32'd12;
166 localparam ST_Refresh_Wait = 32'd13;
167 localparam ST_Activate = 32'd30;
168 localparam ST_Activate_Wait = 32'd31;
169 localparam ST_Write = 32'd32;
170 localparam ST_Read = 32'd33;
171 localparam ST_Read_Wait = 32'd34;
172 localparam ST_Wait_Trp = 32'd35;
173 localparam ST_Ack = 32'd36;
176 reg [31:0] state;
177 always @(posedge wb_clk_i) begin
178 if (wb_rst_i) begin
179 // Initialise state machine and timer
180 state <= ST_INIT1;
181 // debug <= 3'd0;
182 timer <= 32'd0;
184 // Clear REFRESH ACK flag and disable refresh timer
185 refresh_ack <= 1'b0;
186 refresh_timer_en <= 1'b0;
188 // Initialisation state for SDRAM
189 sdram_cke <= 1'b0;
190 sdram_mode <= M_Inhibit;
191 sdram_addr <= 12'h000;
192 sdram_ba <= 2'b00;
193 sdram_dqm <= 4'b0000;
194 sdram_dq_oe <= 1'b0; // data output disabled
195 sdram_dq_r <= 32'd0;
196 end else begin
197 // timer logic
198 if (timer > 32'd0) begin
199 timer <= timer - 32'd1;
200 end
202 // state machine logic
203 case (state)
204 ST_INIT1: begin
205 // INIT1: Set up for initial power-up wait
206 state <= ST_INIT2;
207 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
209 // SDRAM state
210 sdram_cke <= 1'b0; // clock disabled
211 sdram_mode <= M_Inhibit;
212 sdram_addr <= 12'h000;
213 sdram_ba <= 2'b00;
214 sdram_dqm <= 4'b1111;
215 sdram_dq_oe <= 1'b0; // data output disabled
216 sdram_dq_r <= 32'd0;
217 end
219 ST_INIT2: begin
220 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
221 // the end of the power-up wait, then bring CKE high.
222 if (timer == 32'd0) begin
223 // Timer hit zero. Send a NOP.
224 state <= ST_NOP1;
225 end else if (timer < 32'd50) begin
226 // Timer value is more than zero but less than 50; CKE is on, but
227 // keep waiting for the timer to actually expire.
228 sdram_cke <= 1'b1;
229 state <= ST_INIT2;
230 // debug <= 3'd1;
231 end
232 sdram_mode <= M_Inhibit;
233 end
235 ST_NOP1: begin
236 // Apply one or more NOP commands to the SDRAM
237 sdram_mode <= M_Nop;
238 state <= ST_PrechargeAll;
239 end
241 ST_PrechargeAll: begin
242 // Precharge All, then wait T_rp (20ns)
243 sdram_mode <= M_PrechargeAll;
244 timer <= TIME_Trp - 32'd1;
245 state <= ST_PrechargeAll_Wait;
246 end
248 ST_PrechargeAll_Wait: begin
249 // Wait for T_rp after Precharge All
250 sdram_mode <= M_Nop;
251 if (timer == 32'd0) begin
252 // Timer hit zero. Continue
253 state <= ST_AutoRefresh1;
254 end
255 end
257 ST_AutoRefresh1: begin
258 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
259 sdram_mode <= M_AutoRefresh;
260 timer <= TIME_Trfc - 32'd1;
261 state <= ST_AutoRefresh1_Wait;
262 end
264 ST_AutoRefresh1_Wait: begin
265 // Wait for T_rfc
266 sdram_mode <= M_Nop;
267 if (timer == 32'd0) begin
268 // Timer hit zero. Continue
269 state <= ST_AutoRefresh2;
270 end
271 end
273 ST_AutoRefresh2: begin
274 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
275 sdram_mode <= M_AutoRefresh;
276 timer <= TIME_Trfc - 32'd1;
277 state <= ST_AutoRefresh2_Wait;
278 end
280 ST_AutoRefresh2_Wait: begin
281 // Wait for T_rfc
282 sdram_mode <= M_Nop;
283 if (timer == 32'd0) begin
284 // Timer hit zero. Continue
285 state <= ST_LoadModeRegister;
286 end
287 end
289 ST_LoadModeRegister: begin
290 // Load Mode Register
291 /**
292 * Mode register:
293 * - BS0,1 = 00 [RFU]
294 * - A11,10 = 00 [RFU]
295 * - A9 = 0 [WBL -- write burst length same as read burst length]
296 * - A8,7 = 00 [Test Mode off]
297 * - A6..4 = 010 [CAS Latency = 2 or 3 clocks, set above]
298 * - A3 = 0 [Burst type = sequential]
299 * - A2..0 = 000 [Burst length = 1 word]
300 */
301 sdram_ba <= 2'b00;
302 sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
303 sdram_mode <= M_LoadModeRegister;
305 // Wait T_mrd (2 clock cycles)
306 timer <= TIME_Tmrd - 32'd1;
307 state <= ST_LoadModeRegister_Wait;
308 end
310 ST_LoadModeRegister_Wait: begin
311 // Wait for LMR to complete
312 sdram_mode <= M_Nop;
313 sdram_ba <= 2'd0;
314 sdram_addr <= 12'd0;
315 if (timer == 32'd0) begin
316 // Timer hit zero. Continue
317 state <= ST_Spin;
318 end
319 end
321 ST_Spin: begin
322 // Enable refresh timer
323 refresh_timer_en <= 1'b1;
325 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
326 sdram_mode <= M_Inhibit;
328 // Check if a refresh is due (these have highest priority)
329 if (refresh_req) begin
330 // Refresh request received. Ack it and do a refresh.
331 refresh_ack <= 1'b1;
332 state <= ST_Refresh;
333 end else begin
334 if (wb_cyc_i & wb_stb_i) begin
335 // CYC and STB high. A Wishbone cycle just started.
336 state <= ST_Activate;
337 end
338 end
339 end
341 /////
342 // Refresh logic
343 /////
345 ST_Refresh: begin
346 // Refresh timer timed out; do a refresh run
347 // Start by clearing the ACK flag (which was set by the Spin state)
348 refresh_ack <= 1'b0;
349 // Tell the SDRAM to do a Refresh
350 sdram_mode <= M_AutoRefresh;
351 // Wait for T_rfc
352 timer <= TIME_Trfc;
353 state <= ST_Refresh_Wait;
354 end
356 ST_Refresh_Wait: begin
357 // Wait for T_rfc
358 sdram_mode <= M_Nop;
359 if (timer == 32'd0) begin
360 // Timer hit zero. Go back to spin state.
361 state <= ST_Spin;
362 end
363 end
365 //////
366 // R/W logic
367 //////
368 ST_Activate: begin
369 // Activate the required bank
370 sdram_mode <= M_BankActivate;
371 sdram_addr <= row_addr;
372 sdram_ba <= bank_addr;
373 timer <= TIME_Trcd - 32'd1;
374 state <= ST_Activate_Wait;
375 end
377 ST_Activate_Wait: begin
378 // Wait for T_rcd
379 sdram_mode <= M_Nop;
380 if (timer == 32'd0) begin
381 if (wb_we_i) begin
382 // Write cycle.
383 state <= ST_Write;
384 end else begin
385 // Read cycle
386 state <= ST_Read;
387 end
388 end
389 end
391 ST_Write: begin
392 // Write cycle handler
393 sdram_mode <= M_WritePrecharge;
394 sdram_addr <= column_addr;
395 sdram_dq_r <= wb_dat_i;
396 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
397 sdram_dqm <= ~wb_sel_i;
399 // Wait T_rp (20ns)
400 timer <= TIME_Trp - 32'd1;
401 state <= ST_Wait_Trp;
402 end
404 ST_Read: begin
405 // Read cycle handler
406 sdram_mode <= M_ReadPrecharge;
407 sdram_addr <= column_addr;
408 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
409 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
410 timer <= CAS_LATENCY - 32'd1; // CAS# Latency
411 state <= ST_Read_Wait;
412 end
414 ST_Read_Wait: begin
415 // Wait for CAS# latency
416 sdram_mode <= M_Nop;
417 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
418 if (timer == 32'd0) begin
419 // Latch data
420 wb_dat_o <= sdram_dq;
421 // Wait T_rp (20ns)
422 timer <= TIME_Trp - 32'd1;
423 state <= ST_Wait_Trp;
424 end
425 end
427 ST_Wait_Trp: begin
428 // Wait for T_rp, then ack
429 if (timer == 32'd0) begin
430 state <= ST_Ack;
431 end
432 end
434 ST_Ack: begin
435 // Ack the transfer to the WISHBONE host
436 sdram_mode <= M_Nop;
437 sdram_addr <= 32'd0;
438 sdram_dq_r <= 32'd0;
439 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
440 sdram_dqm <= 4'b1111; // mask off DQM
441 if (wb_cyc_i & wb_stb_i) begin
442 // CYC and STB high, ack the transfer
443 wb_ack_o <= 1'b1;
444 state <= ST_Ack;
445 end else begin
446 // CYC and STB low, go back and wait for another transaction
447 wb_ack_o <= 1'b0;
448 state <= ST_Spin;
449 end
450 end
451 endcase
452 end
453 end
455 endmodule