Tue, 10 Aug 2010 19:23:01 +0100
[wb_sdram] move ACK logic around and set DQM from wb_sel_i
write mask (DQM) is now set from WB_SEL_I. reads still pull the whole word.
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * WISHBONE status pins
41 ****/
42 // Can't raise bus errors
43 assign wb_err_o = 1'b0;
44 // Can't request retries
45 assign wb_rty_o = 1'b0;
48 /****
49 * SDRAM data output buffer
50 ****/
51 // OE=1 for output mode, 0 for input
52 reg sdram_dq_oe;
53 // SDRAM output register
54 reg [31:0] sdram_dq_r;
55 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
59 /****
60 * State timer
61 * This is used to ensure that the state machine abides by RAM timing
62 * restrictions.
63 ****/
64 reg [31:0] timer;
67 /****
68 * MODE logic
69 ****/
70 reg [5:0] sdram_mode;
71 reg [11:0] sdram_addr;
72 assign sdram_cs_n = sdram_mode[3];
73 assign sdram_ras_n = sdram_mode[2];
74 assign sdram_cas_n = sdram_mode[1];
75 assign sdram_we_n = sdram_mode[0];
76 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
78 // SDRAM chip instructions
79 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
80 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
81 localparam M_BankActivate = 6'b0X0011;
82 localparam M_PrechargeBank = 6'b100010;
83 localparam M_PrechargeAll = 6'b110010;
84 localparam M_Write = 6'b100100;
85 localparam M_WritePrecharge = 6'b110100;
86 localparam M_Read = 6'b100101;
87 localparam M_ReadPrecharge = 6'b110101;
88 localparam M_LoadModeRegister = 6'b0X0000;
89 localparam M_Nop = 6'b0X0111;
90 localparam M_BurstStop = 6'b0X0110;
91 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
92 localparam M_AutoRefresh = 6'b0X0001;
95 /****
96 * Refresh Timer
97 ****/
98 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
99 reg [31:0] refresh_timer;
100 reg refresh_req, refresh_ack, refresh_timer_en;
101 always @(posedge wb_clk_i) begin
102 if (wb_rst_i | !refresh_timer_en) begin
103 // Reset; clear timer, unset REFRESH REQUEST
104 refresh_req <= 1'b0;
105 refresh_timer <= REFRESH_INTERVAL;
106 end else if (refresh_ack) begin
107 // Refresh Ack, clear Refresh Request.
108 refresh_req <= 1'b0;
109 end else if (refresh_timer == 0) begin
110 // Refresh timer timed out, make a Refresh Request and reload the timer
111 refresh_req <= 1'b1;
112 refresh_timer <= REFRESH_INTERVAL;
113 end else begin
114 // Otherwise just decrement the timer
115 refresh_timer <= refresh_timer - 32'd1;
116 end
117 end
119 assign debug = { 1'b0, refresh_req, refresh_ack };
122 /****
123 * Address decoder
124 ****/
125 wire [8:0] column_addr;
126 wire [11:0] row_addr;
127 wire [1:0] bank_addr;
129 // Convert a 23-bit linear address into an SDRAM address
130 assign column_addr = wb_adr_i[8:0];
131 assign bank_addr = wb_adr_i[10:9];
132 assign row_addr = wb_adr_i[22:11];
135 /****
136 * Finite State Machine
137 ****/
138 localparam ST_INIT1 = 32'd0;
139 localparam ST_INIT2 = 32'd1;
140 localparam ST_NOP1 = 32'd2;
141 localparam ST_PrechargeAll = 32'd3;
142 localparam ST_PrechargeAll_Wait = 32'd4;
143 localparam ST_AutoRefresh1 = 32'd5;
144 localparam ST_AutoRefresh1_Wait = 32'd6;
145 localparam ST_AutoRefresh2 = 32'd7;
146 localparam ST_AutoRefresh2_Wait = 32'd8;
147 localparam ST_LoadModeRegister = 32'd9;
148 localparam ST_LoadModeRegister_Wait = 32'd10;
149 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
150 localparam ST_Refresh = 32'd12;
151 localparam ST_Refresh_Wait = 32'd13;
152 localparam ST_Activate = 32'd30;
153 localparam ST_Activate_Wait = 32'd31;
154 localparam ST_Write = 32'd32;
155 localparam ST_Read = 32'd33;
156 localparam ST_Read_Wait = 32'd34;
157 localparam ST_Wait_Trp = 32'd35;
158 localparam ST_Ack = 32'd36;
161 reg [31:0] state;
162 always @(posedge wb_clk_i) begin
163 if (wb_rst_i) begin
164 // Initialise state machine and timer
165 state <= ST_INIT1;
166 // debug <= 3'd0;
167 timer <= 32'd0;
169 // Clear REFRESH ACK flag and disable refresh timer
170 refresh_ack <= 1'b0;
171 refresh_timer_en <= 1'b0;
173 // Initialisation state for SDRAM
174 sdram_cke <= 1'b0;
175 sdram_mode <= M_Inhibit;
176 sdram_addr <= 12'h000;
177 sdram_ba <= 2'b00;
178 sdram_dqm <= 4'b0000;
179 sdram_dq_oe <= 1'b0; // data output disabled
180 sdram_dq_r <= 32'd0;
181 end else begin
182 // timer logic
183 if (timer > 32'd0) begin
184 timer <= timer - 32'd1;
185 end
187 // state machine logic
188 case (state)
189 ST_INIT1: begin
190 // INIT1: Set up for initial power-up wait
191 state <= ST_INIT2;
192 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
194 // SDRAM state
195 sdram_cke <= 1'b0; // clock disabled
196 sdram_mode <= M_Inhibit;
197 sdram_addr <= 12'h000;
198 sdram_ba <= 2'b00;
199 sdram_dqm <= 4'b1111;
200 sdram_dq_oe <= 1'b0; // data output disabled
201 sdram_dq_r <= 32'd0;
202 end
204 ST_INIT2: begin
205 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
206 // the end of the power-up wait, then bring CKE high.
207 if (timer == 32'd0) begin
208 // Timer hit zero. Send a NOP.
209 state <= ST_NOP1;
210 end else if (timer < 32'd50) begin
211 // Timer value is more than zero but less than 50; CKE is on, but
212 // keep waiting for the timer to actually expire.
213 sdram_cke <= 1'b1;
214 state <= ST_INIT2;
215 // debug <= 3'd1;
216 end
217 sdram_mode <= M_Inhibit;
218 end
220 ST_NOP1: begin
221 // Apply one or more NOP commands to the SDRAM
222 sdram_mode <= M_Nop;
223 state <= ST_PrechargeAll;
224 end
226 ST_PrechargeAll: begin
227 // Precharge All, then wait T_rp (20ns)
228 sdram_mode <= M_PrechargeAll;
229 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
230 state <= ST_PrechargeAll_Wait;
231 end
233 ST_PrechargeAll_Wait: begin
234 // Wait for T_rp after Precharge All
235 sdram_mode <= M_Nop;
236 if (timer == 32'd0) begin
237 // Timer hit zero. Continue
238 state <= ST_AutoRefresh1;
239 end
240 end
242 ST_AutoRefresh1: begin
243 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
244 sdram_mode <= M_AutoRefresh;
245 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
246 state <= ST_AutoRefresh1_Wait;
247 end
249 ST_AutoRefresh1_Wait: begin
250 // Wait for T_rfc
251 sdram_mode <= M_Nop;
252 if (timer == 32'd0) begin
253 // Timer hit zero. Continue
254 state <= ST_AutoRefresh2;
255 end
256 end
258 ST_AutoRefresh2: begin
259 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
260 sdram_mode <= M_AutoRefresh;
261 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
262 state <= ST_AutoRefresh2_Wait;
263 end
265 ST_AutoRefresh2_Wait: begin
266 // Wait for T_rfc
267 sdram_mode <= M_Nop;
268 if (timer == 32'd0) begin
269 // Timer hit zero. Continue
270 state <= ST_LoadModeRegister;
271 end
272 end
274 ST_LoadModeRegister: begin
275 // Load Mode Register
276 /**
277 * Mode register:
278 * - BS0,1 = 00 [RFU]
279 * - A11,10 = 00 [RFU]
280 * - A9 = 0 [WBL -- write burst length same as read burst length]
281 * - A8,7 = 00 [Test Mode off]
282 * - A6..4 = 010 [CAS Latency = 2 clocks]
283 * - A3 = 0 [Burst type = sequential]
284 * - A2..0 = 000 [Burst length = 1 word]
285 */
286 sdram_ba <= 2'b00;
287 sdram_addr <= 12'b00_0_00_010_000;
288 sdram_mode <= M_LoadModeRegister;
290 // Wait T_mrd (2 clock cycles)
291 timer <= 32'd1; // (2cy)-1 ---> TIMER HERE
292 state <= ST_LoadModeRegister_Wait;
293 end
295 ST_LoadModeRegister_Wait: begin
296 // Wait for LMR to complete
297 sdram_mode <= M_Nop;
298 sdram_ba <= 2'd0;
299 sdram_addr <= 12'd0;
300 if (timer == 32'd0) begin
301 // Timer hit zero. Continue
302 state <= ST_Spin;
303 end
304 end
306 ST_Spin: begin
307 // Enable refresh timer
308 refresh_timer_en <= 1'b1;
310 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
311 sdram_mode <= M_Inhibit;
313 // Check if a refresh is due (these have highest priority)
314 if (refresh_req) begin
315 // Refresh request received. Ack it and do a refresh.
316 refresh_ack <= 1'b1;
317 state <= ST_Refresh;
318 end else begin
319 if (wb_cyc_i & wb_stb_i) begin
320 // CYC and STB high. A Wishbone cycle just started.
321 state <= ST_Activate;
322 end
323 end
324 end
326 /////
327 // Refresh logic
328 /////
330 ST_Refresh: begin
331 // Refresh timer timed out; do a refresh run
332 // Start by clearing the ACK flag (which was set by the Spin state)
333 refresh_ack <= 1'b0;
334 // Tell the SDRAM to do a Refresh
335 sdram_mode <= M_AutoRefresh;
336 // Wait for T_rfc
337 timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE
338 state <= ST_Refresh_Wait;
339 end
341 ST_Refresh_Wait: begin
342 // Wait for T_rfc
343 sdram_mode <= M_Nop;
344 if (timer == 32'd0) begin
345 // Timer hit zero. Go back to spin state.
346 state <= ST_Spin;
347 end
348 end
350 //////
351 // R/W logic
352 //////
353 ST_Activate: begin
354 // Activate the required bank
355 sdram_mode <= M_BankActivate;
356 sdram_addr <= row_addr;
357 sdram_ba <= bank_addr;
358 timer <= 32'd0; // Wait T_rcd (20ns ideally, here 40ns) ---> TIMER HERE
359 state <= ST_Activate_Wait;
360 end
362 ST_Activate_Wait: begin
363 // Wait for T_rcd
364 sdram_mode <= M_Nop;
365 if (timer == 32'd0) begin
366 if (wb_we_i) begin
367 // Write cycle.
368 state <= ST_Write;
369 end else begin
370 // Read cycle
371 state <= ST_Read;
372 end
373 end
374 end
376 ST_Write: begin
377 // Write cycle handler
378 sdram_mode <= M_WritePrecharge;
379 sdram_addr <= column_addr;
380 sdram_dq_r <= wb_dat_i;
381 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
382 sdram_dqm <= ~wb_sel_i;
384 // Wait T_rp (20ns)
385 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
386 state <= ST_Wait_Trp;
387 end
389 ST_Read: begin
390 // Read cycle handler
391 sdram_mode <= M_ReadPrecharge;
392 sdram_addr <= column_addr;
393 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
394 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
395 timer <= 32'd2 - 32'd1; // CAS# Latency ---> TIMER HERE
396 state <= ST_Read_Wait;
397 end
399 ST_Read_Wait: begin
400 // Wait for CAS# latency
401 sdram_mode <= M_Nop;
402 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
403 if (timer == 32'd0) begin
404 // Latch data
405 wb_dat_o <= sdram_dq;
406 // Wait T_rp (20ns)
407 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
408 state <= ST_Wait_Trp;
409 end
410 end
412 ST_Wait_Trp: begin
413 // Wait for T_rp, then ack
414 if (timer == 32'd0) begin
415 state <= ST_Ack;
416 end
417 end
419 ST_Ack: begin
420 // Ack the transfer to the WISHBONE host
421 sdram_mode <= M_Nop;
422 sdram_addr <= 32'd0;
423 sdram_dq_r <= 32'd0;
424 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
425 sdram_dqm <= 4'b1111; // mask off DQM
426 if (wb_cyc_i & wb_stb_i) begin
427 // CYC and STB high, ack the transfer
428 wb_ack_o <= 1'b1;
429 state <= ST_Ack;
430 end else begin
431 // CYC and STB low, go back and wait for another transaction
432 wb_ack_o <= 1'b0;
433 state <= ST_Spin;
434 end
435 end
436 endcase
437 end
438 end
440 endmodule