wb_sdram.v

Tue, 10 Aug 2010 22:49:21 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 22:49:21 +0100
changeset 12
81ec01103af1
parent 11
efeebc7c7498
child 13
07b3fd53e7a5
permissions
-rw-r--r--

[wb_sdram] tidy up refresh time parameterisation

     1 	/****************************************************************************
     2  *
     3  *
     4  ****************************************************************************/
     6 module wb_sdram (
     7 	// Clocks and resets
     8 	input						wb_clk_i,			// WISHBONE clock
     9 	input						wb_rst_i,			// WISHBONE reset
    11 	// WISHBONE bus
    12 	input			[31:0]	wb_adr_i,			// WISHBONE address
    13 	input			[31:0]	wb_dat_i,			// WISHBONE data in
    14 	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
    15 	input			[3:0]		wb_sel_i,			// WISHBONE byte select
    16 	input						wb_we_i,				// WISHBONE write enable (R/#W)
    17 	input						wb_cyc_i,			// WISHBONE cycle
    18 	input						wb_stb_i,			// WISHBONE strobe
    19 	output reg				wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
    20 	output					wb_err_o,			// WISHBONE bus error
    21 	output					wb_rty_o,			// WISHBONE retry-later
    23 	// SDRAM
    24 	output reg				sdram_cke,			// SDRAM clock enable
    25 	output					sdram_cs_n,			// SDRAM chip select (active low)
    26 	output					sdram_ras_n,		// SDRAM row address strobe (active low)
    27 	output					sdram_cas_n,		// SDRAM column address strobe (active low)
    28 	output					sdram_we_n,			// SDRAM write enable (active low)
    29 	output		[11:0]	sdram_a,				// SDRAM address
    30 	output reg	[1:0]		sdram_ba,			// SDRAM bank address
    31 	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
    32 	inout			[31:0]	sdram_dq,			// SDRAM data bus
    34 	// Debugging
    35 	output /*reg*/	[2:0]		debug					// debug bits
    36 );
    39 /****
    40  * Timer values
    41  ****/
    42 // CAS latency -- either 2 or 3
    43 parameter	CAS_LATENCY		= 3'd2;
    44 // T_rp  ==> 20ns
    45 parameter	TIME_Trp			= 32'd1;
    46 // T_rcd ==> 20ns
    47 parameter	TIME_Trcd		= 32'd1;
    48 // T_rfc (a.k.a. T_rc) ==> 70ns
    49 parameter	TIME_Trfc		= 32'd2;
    50 // T_mrd ==> 2 clock cycles
    51 parameter	TIME_Tmrd		= 32'd2;
    52 // Maximum allowed time between two refresh cycles
    53 parameter	TIME_REFRESH	= 32'd390;
    56 /****
    57  * WISHBONE status pins
    58  ****/
    59 // Can't raise bus errors
    60 assign wb_err_o = 1'b0;
    61 // Can't request retries
    62 assign wb_rty_o = 1'b0;
    63 // Lock DEBUG pins low
    64 assign debug = 3'd0;
    66 /****
    67  * SDRAM data output buffer
    68  ****/
    69 // OE=1 for output mode, 0 for input
    70 reg sdram_dq_oe;
    71 // SDRAM output register
    72 reg [31:0] sdram_dq_r;
    73 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    77 /****
    78  * State timer
    79  * This is used to ensure that the state machine abides by RAM timing
    80  * restrictions.
    81  ****/
    82 reg [31:0] timer;
    85 /****
    86  * MODE logic
    87  ****/
    88 reg  [5:0]  sdram_mode;
    89 reg  [11:0]	sdram_addr;
    90 assign sdram_cs_n		= sdram_mode[3];
    91 assign sdram_ras_n	= sdram_mode[2];
    92 assign sdram_cas_n	= sdram_mode[1];
    93 assign sdram_we_n		= sdram_mode[0];
    94 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
    96 // SDRAM chip instructions
    97 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
    98 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
    99 localparam M_BankActivate		= 6'b0X0011;
   100 localparam M_PrechargeBank		= 6'b100010;
   101 localparam M_PrechargeAll		= 6'b110010;
   102 localparam M_Write				= 6'b100100;
   103 localparam M_WritePrecharge	= 6'b110100;
   104 localparam M_Read					= 6'b100101;
   105 localparam M_ReadPrecharge		= 6'b110101;
   106 localparam M_LoadModeRegister	= 6'b0X0000;
   107 localparam M_Nop					= 6'b0X0111;
   108 localparam M_BurstStop			= 6'b0X0110;
   109 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
   110 localparam M_AutoRefresh		= 6'b0X0001;
   113 /****
   114  * Refresh Timer
   115  ****/
   116 reg [31:0] refresh_timer;
   117 reg refresh_req, refresh_ack, refresh_timer_en;
   118 always @(posedge wb_clk_i) begin
   119 	if (wb_rst_i | !refresh_timer_en) begin
   120 		// Reset; clear timer, unset REFRESH REQUEST
   121 		refresh_req <= 1'b0;
   122 		refresh_timer <= TIME_REFRESH - 32'd1;
   123 	end else if (refresh_ack) begin
   124 		// Refresh Ack, clear Refresh Request.
   125 		refresh_req <= 1'b0;
   126 	end else if (refresh_timer == 0) begin
   127 		// Refresh timer timed out, make a Refresh Request and reload the timer
   128 		refresh_req <= 1'b1;
   129 		refresh_timer <= TIME_REFRESH - 32'd1;
   130 	end else begin
   131 		// Otherwise just decrement the timer
   132 		refresh_timer <= refresh_timer - 32'd1;
   133 	end
   134 end
   137 /****
   138  * Address decoder
   139  ****/
   140 wire [8:0] column_addr;
   141 wire [11:0] row_addr;
   142 wire [1:0] bank_addr;
   144 // Convert a 23-bit linear address into an SDRAM address
   145 assign column_addr	= wb_adr_i[8:0];
   146 assign bank_addr		= wb_adr_i[10:9];
   147 assign row_addr		= wb_adr_i[22:11];
   150 /****
   151  * Finite State Machine
   152  ****/
   153 localparam	ST_INIT1							= 32'd0;
   154 localparam	ST_INIT2							= 32'd1;
   155 localparam	ST_NOP1							= 32'd2;
   156 localparam	ST_PrechargeAll				= 32'd3;
   157 localparam	ST_PrechargeAll_Wait			= 32'd4;
   158 localparam	ST_AutoRefresh1				= 32'd5;
   159 localparam	ST_AutoRefresh1_Wait			= 32'd6;
   160 localparam	ST_AutoRefresh2				= 32'd7;
   161 localparam	ST_AutoRefresh2_Wait			= 32'd8;
   162 localparam	ST_LoadModeRegister			= 32'd9;
   163 localparam	ST_LoadModeRegister_Wait	= 32'd10;
   164 localparam	ST_Spin							= 32'd11;		// <<== main 'spin' / 'idle' state
   165 localparam	ST_Refresh						= 32'd12;
   166 localparam	ST_Refresh_Wait				= 32'd13;
   167 localparam	ST_Activate						= 32'd30;
   168 localparam	ST_Activate_Wait				= 32'd31;
   169 localparam	ST_Write							= 32'd32;
   170 localparam	ST_Read							= 32'd33;
   171 localparam	ST_Read_Wait					= 32'd34;
   172 localparam	ST_Wait_Trp						= 32'd35;
   173 localparam	ST_Ack							= 32'd36;
   176 reg [31:0] state;
   177 always @(posedge wb_clk_i) begin
   178 	if (wb_rst_i) begin
   179 		// Initialise state machine and timer
   180 		state <= ST_INIT1;
   181 		timer <= 32'd0;
   183 		// Clear REFRESH ACK flag and disable refresh timer
   184 		refresh_ack <= 1'b0;
   185 		refresh_timer_en <= 1'b0;
   187 		// Initialisation state for SDRAM
   188 		sdram_cke	<= 1'b0;
   189 		sdram_mode	<= M_Inhibit;
   190 		sdram_addr	<= 12'h000;
   191 		sdram_ba		<= 2'b00;
   192 		sdram_dqm	<= 4'b0000;
   193 		sdram_dq_oe	<= 1'b0;			// data output disabled
   194 		sdram_dq_r	<= 32'd0;
   195 	end else begin
   196 		// timer logic
   197 		if (timer > 32'd0) begin
   198 			timer <= timer - 32'd1;
   199 		end
   201 		// state machine logic
   202 		case (state)
   203 			ST_INIT1: begin
   204 					// INIT1: Set up for initial power-up wait
   205 					state <= ST_INIT2;
   206 					timer <= 32'd50_000;		// TODO: dependent on core clock rate. Needs to be >= 100us
   208 					// SDRAM state
   209 					sdram_cke	<= 1'b0;			// clock disabled
   210 					sdram_mode	<= M_Inhibit;
   211 					sdram_addr	<= 12'h000;
   212 					sdram_ba		<= 2'b00;
   213 					sdram_dqm	<= 4'b1111;
   214 					sdram_dq_oe	<= 1'b0;			// data output disabled
   215 					sdram_dq_r	<= 32'd0;
   216 				end
   218 			ST_INIT2: begin
   219 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
   220 					// the end of the power-up wait, then bring CKE high.
   221 					if (timer == 32'd0) begin
   222 						// Timer hit zero. Send a NOP.
   223 						state <= ST_NOP1;
   224 					end else if (timer < 32'd50) begin
   225 						// Timer value is more than zero but less than 50; CKE is on, but
   226 						// keep waiting for the timer to actually expire.
   227 						sdram_cke	<= 1'b1;
   228 						state			<= ST_INIT2;
   229 					end
   230 					sdram_mode <= M_Inhibit;
   231 				end
   233 			ST_NOP1: begin
   234 					// Apply one or more NOP commands to the SDRAM
   235 					sdram_mode <= M_Nop;
   236 					state <= ST_PrechargeAll;
   237 				end
   239 			ST_PrechargeAll: begin
   240 					// Precharge All, then wait T_rp (20ns)
   241 					sdram_mode <= M_PrechargeAll;
   242 					timer <= TIME_Trp - 32'd1;
   243 					state <= ST_PrechargeAll_Wait;
   244 				end
   246 			ST_PrechargeAll_Wait: begin
   247 					// Wait for T_rp after Precharge All
   248 					sdram_mode <= M_Nop;
   249 					if (timer == 32'd0) begin
   250 						// Timer hit zero. Continue
   251 						state <= ST_AutoRefresh1;
   252 					end
   253 				end
   255 			ST_AutoRefresh1: begin
   256 					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
   257 					sdram_mode <= M_AutoRefresh;
   258 					timer <= TIME_Trfc - 32'd1;
   259 					state <= ST_AutoRefresh1_Wait;
   260 				end
   262 			ST_AutoRefresh1_Wait: begin
   263 					// Wait for T_rfc
   264 					sdram_mode <= M_Nop;
   265 					if (timer == 32'd0) begin
   266 						// Timer hit zero. Continue
   267 						state <= ST_AutoRefresh2;
   268 					end
   269 				end
   271 			ST_AutoRefresh2: begin
   272 					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
   273 					sdram_mode <= M_AutoRefresh;
   274 					timer <= TIME_Trfc - 32'd1;
   275 					state <= ST_AutoRefresh2_Wait;
   276 				end
   278 			ST_AutoRefresh2_Wait: begin
   279 					// Wait for T_rfc
   280 					sdram_mode <= M_Nop;
   281 					if (timer == 32'd0) begin
   282 						// Timer hit zero. Continue
   283 						state <= ST_LoadModeRegister;
   284 					end
   285 				end
   287 			ST_LoadModeRegister: begin
   288 					// Load Mode Register
   289 					/**
   290 					 * Mode register:
   291 					 *   - BS0,1  = 00  [RFU]
   292 					 *   - A11,10 = 00  [RFU]
   293 					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
   294 					 *   - A8,7   = 00  [Test Mode off]
   295 					 *   - A6..4  = 010 [CAS Latency = 2 or 3 clocks, set above]
   296 					 *   - A3     = 0   [Burst type = sequential]
   297 					 *   - A2..0  = 000 [Burst length = 1 word]
   298 					 */
   299 					sdram_ba <= 2'b00;
   300 					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
   301 					sdram_mode <= M_LoadModeRegister;
   303 					// Wait T_mrd (2 clock cycles)
   304 					timer <= TIME_Tmrd - 32'd1;
   305 					state <= ST_LoadModeRegister_Wait;
   306 				end
   308 			ST_LoadModeRegister_Wait: begin
   309 					// Wait for LMR to complete
   310 					sdram_mode <= M_Nop;
   311 					sdram_ba <= 2'd0;
   312 					sdram_addr <= 12'd0;
   313 					if (timer == 32'd0) begin
   314 						// Timer hit zero. Continue
   315 						state <= ST_Spin;
   316 					end
   317 				end
   319 			ST_Spin: begin
   320 					// Enable refresh timer
   321 					refresh_timer_en <= 1'b1;
   323 					// Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
   324 					sdram_mode <= M_Inhibit;
   326 					// Check if a refresh is due (these have highest priority)
   327 					if (refresh_req) begin
   328 						// Refresh request received. Ack it and do a refresh.
   329 						refresh_ack <= 1'b1;
   330 						state <= ST_Refresh;
   331 					end else begin
   332 						if (wb_cyc_i & wb_stb_i) begin
   333 							// CYC and STB high. A Wishbone cycle just started.
   334 							state <= ST_Activate;
   335 						end
   336 					end
   337 				end
   339 /////
   340 // Refresh logic
   341 /////
   343 			ST_Refresh: begin
   344 					// Refresh timer timed out; do a refresh run
   345 					// Start by clearing the ACK flag (which was set by the Spin state)
   346 					refresh_ack <= 1'b0;
   347 					// Tell the SDRAM to do a Refresh
   348 					sdram_mode <= M_AutoRefresh;
   349 					// Wait for T_rfc
   350 					timer <= TIME_Trfc;
   351 					state <= ST_Refresh_Wait;
   352 				end
   354 			ST_Refresh_Wait: begin
   355 					// Wait for T_rfc
   356 					sdram_mode <= M_Nop;
   357 					if (timer == 32'd0) begin
   358 						// Timer hit zero. Go back to spin state.
   359 						state <= ST_Spin;
   360 					end
   361 				end
   363 //////
   364 // R/W logic
   365 //////
   366 			ST_Activate: begin
   367 					// Activate the required bank
   368 					sdram_mode <= M_BankActivate;
   369 					sdram_addr <= row_addr;
   370 					sdram_ba   <= bank_addr;
   371 					timer <= TIME_Trcd - 32'd1;
   372 					state <= ST_Activate_Wait;
   373 				end
   375 			ST_Activate_Wait: begin
   376 					// Wait for T_rcd
   377 					sdram_mode <= M_Nop;
   378 					if (timer == 32'd0) begin
   379 						if (wb_we_i) begin
   380 							// Write cycle.
   381 							state <= ST_Write;
   382 						end else begin
   383 							// Read cycle
   384 							state <= ST_Read;
   385 						end
   386 					end
   387 				end
   389 			ST_Write: begin
   390 					// Write cycle handler
   391 					sdram_mode	<= M_WritePrecharge;
   392 					sdram_addr	<= column_addr;
   393 					sdram_dq_r	<= wb_dat_i;
   394 					sdram_dq_oe	<= 1'b1;		// FPGA drives the DQ bus
   395 					sdram_dqm	<= ~wb_sel_i;
   397 					// Wait T_rp (20ns)
   398 					timer <= TIME_Trp - 32'd1;
   399 					state <= ST_Wait_Trp;
   400 				end
   402 			ST_Read: begin
   403 					// Read cycle handler
   404 					sdram_mode	<= M_ReadPrecharge;
   405 					sdram_addr	<= column_addr;
   406 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   407 					sdram_dqm	<= 4'b0000;	// Grab all the data (it's just easier that way...)
   408 					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
   409 					state <= ST_Read_Wait;
   410 				end
   412 			ST_Read_Wait: begin
   413 					// Wait for CAS# latency
   414 					sdram_mode	<= M_Nop;
   415 					sdram_dqm	<= 4'b1111;	// Make SDRAM DQ bus float
   416 					if (timer == 32'd0) begin
   417 						// Latch data
   418 						wb_dat_o <= sdram_dq;
   419 						// Wait T_rp (20ns)
   420 						timer <= TIME_Trp - 32'd1;
   421 						state <=	ST_Wait_Trp;
   422 					end
   423 				end
   425 			ST_Wait_Trp: begin
   426 					// Wait for T_rp, then ack
   427 					if (timer == 32'd0) begin
   428 						state <= ST_Ack;
   429 					end
   430 				end
   432 			ST_Ack: begin
   433 					// Ack the transfer to the WISHBONE host
   434 					sdram_mode	<= M_Nop;
   435 					sdram_addr	<= 32'd0;
   436 					sdram_dq_r	<= 32'd0;
   437 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   438 					sdram_dqm	<= 4'b1111;	// mask off DQM
   439 					if (wb_cyc_i & wb_stb_i) begin
   440 						// CYC and STB high, ack the transfer
   441 						wb_ack_o		<= 1'b1;
   442 						state			<= ST_Ack;
   443 					end else begin
   444 						// CYC and STB low, go back and wait for another transaction
   445 						wb_ack_o		<= 1'b0;
   446 						state			<= ST_Spin;
   447 					end
   448 				end
   449 		endcase
   450 	end
   451 end
   453 endmodule