wb_sdram.v

Tue, 10 Aug 2010 13:23:58 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 13:23:58 +0100
changeset 2
ceaa61ebf8a2
parent 1
05af11892ed8
child 3
6a724779fb48
permissions
-rw-r--r--

implement (almost) complete SDRAM init sequence

     1 /****************************************************************************
     2  *
     3  *
     4  ****************************************************************************/
     6 module wb_sdram (
     7 	// Clocks and resets
     8 	input						wb_clk_i,			// WISHBONE clock
     9 	input						wb_rst_i,			// WISHBONE reset
    11 	// WISHBONE bus
    12 	input			[31:0]	wb_adr_i,			// WISHBONE address
    13 	input			[31:0]	wb_dat_i,			// WISHBONE data in
    14 	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
    15 	input			[3:0]		wb_sel_i,			// WISHBONE byte select
    16 	input						wb_we_i,				// WISHBONE write enable (R/#W)
    17 	input						wb_cyc_i,			// WISHBONE cycle
    18 	input						wb_stb_i,			// WISHBONE strobe
    19 	output					wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
    20 	output					wb_err_o,			// WISHBONE bus error
    21 	output					wb_rty_o,			// WISHBONE retry-later
    23 	// SDRAM
    24 	output reg				sdram_cke,			// SDRAM clock enable
    25 	output					sdram_cs_n,			// SDRAM chip select (active low)
    26 	output					sdram_ras_n,		// SDRAM row address strobe (active low)
    27 	output					sdram_cas_n,		// SDRAM column address strobe (active low)
    28 	output					sdram_we_n,			// SDRAM write enable (active low)
    29 	output		[11:0]	sdram_a,				// SDRAM address
    30 	output reg	[1:0]		sdram_ba,			// SDRAM bank address
    31 	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
    32 	inout			[31:0]	sdram_dq,			// SDRAM data bus
    34 	// Debugging
    35 	output reg	[2:0]		debug					// debug bits
    36 );
    39 /****
    40  * SDRAM data output buffer
    41  ****/
    42 // OE=1 for output mode, 0 for input
    43 reg sdram_dq_oe;
    44 // SDRAM output register
    45 reg [31:0] sdram_dq_r;
    46 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    50 /****
    51  * State timer
    52  * This is used to ensure that the state machine abides by RAM timing
    53  * restrictions.
    54  ****/
    55 reg [31:0] timer;
    58 /****
    59  * MODE logic
    60  ****/
    61 reg  [5:0]  sdram_mode;
    62 reg  [11:0]	sdram_addr;
    63 assign sdram_cs_n		= sdram_mode[3];
    64 assign sdram_ras_n	= sdram_mode[2];
    65 assign sdram_cas_n	= sdram_mode[1];
    66 assign sdram_we_n		= sdram_mode[0];
    67 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
    69 // SDRAM chip instructions
    70 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
    71 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
    72 localparam M_BankActivate		= 6'b0X0011;
    73 localparam M_PrechargeBank		= 6'b100010;
    74 localparam M_PrechargeAll		= 6'b110010;
    75 localparam M_Write				= 6'b100100;
    76 localparam M_WritePrecharge	= 6'b110100;
    77 localparam M_Read					= 6'b100101;
    78 localparam M_ReadPrecharge		= 6'b110101;
    79 localparam M_LoadModeRegister	= 6'b0X0000;
    80 localparam M_Nop					= 6'b0X0111;
    81 localparam M_BurstStop			= 6'b0X0110;
    82 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
    83 localparam M_AutoRefresh		= 6'b0X0001;
    86 /****
    87  * Finite State Machine
    88  ****/
    89 localparam	ST_INIT1							= 32'd0;
    90 localparam	ST_INIT2							= 32'd1;
    91 localparam	ST_NOP1							= 32'd2;
    92 localparam	ST_PrechargeAll				= 32'd3;
    93 localparam	ST_PrechargeAll_Wait			= 32'd4;
    94 localparam	ST_AutoRefresh1				= 32'd5;
    95 localparam	ST_AutoRefresh1_Wait			= 32'd6;
    96 localparam	ST_AutoRefresh2				= 32'd7;
    97 localparam	ST_AutoRefresh2_Wait			= 32'd8;
    98 localparam	ST_LoadModeRegister			= 32'd9;
    99 localparam	ST_LoadModeRegister_Wait	= 32'd10;
   100 localparam	ST_Spin							= 32'd999;
   102 reg [31:0] state;
   103 always @(posedge wb_clk_i) begin
   104 	if (wb_rst_i) begin
   105 		// Initialise state machine and timer
   106 		state <= ST_INIT1;
   107 		debug <= 3'd0;
   108 		timer <= 32'd0;
   110 		// Initialisation state for SDRAM
   111 		sdram_cke	<= 1'b0;
   112 		sdram_mode	<= M_Inhibit;
   113 		sdram_addr	<= 12'h000;
   114 		sdram_ba		<= 2'b00;
   115 		sdram_dqm	<= 4'b0000;
   116 		sdram_dq_oe	<= 1'b0;			// data output disabled
   117 		sdram_dq_r	<= 32'd0;
   118 	end else begin
   119 		// timer logic
   120 		if (timer > 32'd0) begin
   121 			timer <= timer - 32'd1;
   122 		end
   124 		// state machine logic
   125 		case (state)
   126 			ST_INIT1: begin
   127 					// INIT1: Set up for initial power-up wait
   128 					state <= ST_INIT2;
   129 					timer <= 32'd50_000;		// TODO: dependent on core clock rate. Needs to be >= 100us
   131 					// SDRAM state
   132 					sdram_cke	<= 1'b0;			// clock disabled
   133 					sdram_mode	<= M_Inhibit;
   134 					sdram_addr	<= 12'h000;
   135 					sdram_ba		<= 2'b00;
   136 					sdram_dqm	<= 4'b1111;
   137 					sdram_dq_oe	<= 1'b0;			// data output disabled
   138 					sdram_dq_r	<= 32'd0;
   139 				end
   141 			ST_INIT2: begin
   142 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
   143 					// the end of the power-up wait, then bring CKE high.
   144 					if (timer == 32'd0) begin
   145 						// Timer hit zero. Send a NOP.
   146 						state <= ST_NOP1;
   147 					end else if (timer < 32'd50) begin
   148 						// Timer value is more than zero but less than 50; CKE is on, but
   149 						// keep waiting for the timer to actually expire.
   150 						sdram_cke	<= 1'b1;
   151 						state			<= ST_INIT2;
   152 						debug <= 3'd1;
   153 					end
   154 					sdram_mode <= M_Inhibit;
   155 				end
   157 			ST_NOP1: begin
   158 					// Apply one or more NOP commands to the SDRAM
   159 					sdram_mode <= M_Nop;
   160 					state <= ST_PrechargeAll;
   161 				end
   163 			ST_PrechargeAll: begin
   164 					// Precharge All, then wait T_rp (20ns)
   165 					sdram_mode <= M_PrechargeAll;
   166 					timer <= 32'd0;	// wait 1tcy (40ns)   ---> TIMER HERE
   167 					state <= ST_PrechargeAll_Wait;
   168 				end
   170 			ST_PrechargeAll_Wait: begin
   171 					// Wait for T_rp after Precharge All
   172 					sdram_mode <= M_Nop;
   173 					if (timer == 32'd0) begin
   174 						// Timer hit zero. Continue
   175 						state <= ST_AutoRefresh1;
   176 					end
   177 				end
   179 			ST_AutoRefresh1: begin
   180 					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
   181 					sdram_mode <= M_AutoRefresh;
   182 					timer <= 32'd1;	// wait 2tcy (80ns)  ---> TIMER HERE
   183 					state <= ST_AutoRefresh1_Wait;
   184 				end
   186 			ST_AutoRefresh1_Wait: begin
   187 					// Wait for T_rfc
   188 					sdram_mode <= M_Nop;
   189 					if (timer == 32'd0) begin
   190 						// Timer hit zero. Continue
   191 						state <= ST_AutoRefresh2;
   192 					end
   193 				end
   195 			ST_AutoRefresh2: begin
   196 					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
   197 					sdram_mode <= M_AutoRefresh;
   198 					timer <= 32'd1;	// wait 2tcy (80ns)  ---> TIMER HERE
   199 					state <= ST_AutoRefresh2_Wait;
   200 				end
   202 			ST_AutoRefresh2_Wait: begin
   203 					// Wait for T_rfc
   204 					sdram_mode <= M_Nop;
   205 					if (timer == 32'd0) begin
   206 						// Timer hit zero. Continue
   207 						state <= ST_LoadModeRegister;
   208 					end
   209 				end
   211 			ST_LoadModeRegister: begin
   212 					// Load Mode Register
   213 					/**
   214 					 * Mode register:
   215 					 *   - BS0,1  = 00  [RFU]
   216 					 *   - A11,10 = 00  [RFU]
   217 					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
   218 					 *   - A8,7   = 00  [Test Mode off]
   219 					 *   - A6..4  = 010 [CAS Latency = 2 clocks]
   220 					 *   - A3     = 0   [Burst type = sequential]
   221 					 *   - A2..0  = 000 [Burst length = 1 word]
   222 					 */
   223 					sdram_ba <= 2'b00;
   224 					sdram_addr <= 12'b00_0_00_010_000;
   225 					sdram_mode <= M_LoadModeRegister;
   227 					// Wait T_mrd (2 clock cycles)
   228 					timer <= 32'd1;	// (2cy)-1  ---> TIMER HERE
   229 					state <= ST_LoadModeRegister_Wait;
   230 				end
   232 			ST_LoadModeRegister_Wait: begin
   233 					// Wait for LMR to complete
   234 					sdram_mode <= M_Nop;
   235 					sdram_ba <= 2'd0;
   236 					sdram_addr <= 12'd0;
   237 					if (timer == 32'd0) begin
   238 						// Timer hit zero. Continue
   239 						state <= ST_Spin;
   240 					end
   241 				end
   243 			ST_Spin: begin
   244 					sdram_mode <= M_Inhibit;
   245 					state <= ST_Spin;
   246 				end
   247 		endcase
   248 	end
   249 end
   251 endmodule