wb_sdram.v

Wed, 18 Aug 2010 14:17:42 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 18 Aug 2010 14:17:42 +0100
changeset 19
d39b0f302ca3
parent 18
275105a6a36b
permissions
-rw-r--r--

comment cleanup

     1 /****************************************************************************
     2  * WISHBONE SDRAM CONTROLLER MODULE / IP CORE
     3  * (C) 2010 Philip Pemberton. All Rights Reserved.
     4  *
     5  * This IP core provides a WISHBONE-compliant interface for most standard
     6  * SDR SDRAM ICs (e.g. the ISSI part on the Enterpoint Drigmorn2 and
     7  * Craignell2 boards).
     8  ****************************************************************************/
    10 module wb_sdram #(
    11 	// Data and address bus parameters
    12 	parameter	DATA_BITS				= 32,				// Width of SDRAM data bus
    13 	parameter	COLADDR_BITS			= 9,				// Number of SDRAM Column Address bits
    14 	parameter	BANKADDR_BITS			= 2,				// Number of SDRAM Bank Address bits
    15 	parameter	ROWADDR_BITS			= 12,				// Number of SDRAM Row Address bits
    17 	// Timer parameters
    18 	parameter	CAS_LATENCY				= 3'd2,			// CAS latency -- either 2 or 3
    19 	parameter	CLOCK_RATE				= 25_000_000,	// System clock frequency in Hz
    21 	// SDRAM timings in nanoseconds
    22 	// Precharge to refresh/row activate command (same bank) -- Trp
    23 	parameter	TIME_Trp					= 20,
    24 	// RAS# to CAS# delay -- Trcd
    25 	parameter	TIME_Trcd				= 20,
    26 	// Row cycle time -- Trfc, also known as Trc
    27 	parameter	TIME_Trfc				= 70,
    28 	// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
    29 	parameter	TIME_Refresh			= 15_625,
    30 	// 2ms power-up init period (2e6 nanoseconds = 2ms)
    31 	parameter	TIME_InitDelay			= 2_000_000,
    32 	// 2us before the end of the init period, raise CKE (2000ns = 2us)
    33 	parameter	TIME_InitFinal			= 2_000
    34 ) (
    35 	// Clocks and resets
    36 	input										wb_clk_i,		// WISHBONE clock
    37 	input										wb_rst_i,		// WISHBONE reset
    39 	// WISHBONE bus
    40 	input			[31:0]					wb_adr_i,		// WISHBONE address
    41 	input			[DATA_BITS-1:0]		wb_dat_i,		// WISHBONE data in
    42 	output reg	[DATA_BITS-1:0]		wb_dat_o,		// WISHBONE data out
    43 	input			[(DATA_BITS/4)-1:0]	wb_sel_i,		// WISHBONE byte select
    44 	input										wb_we_i,			// WISHBONE write enable (R/#W)
    45 	input										wb_cyc_i,		// WISHBONE cycle
    46 	input										wb_stb_i,		// WISHBONE strobe
    47 	output reg								wb_ack_o,		// WISHBONE cycle acknowledge (data available, DTACK)
    48 	output									wb_err_o,		// WISHBONE bus error
    49 	output									wb_rty_o,		// WISHBONE retry-later
    51 	// SDRAM
    52 	output reg								sdram_cke,		// SDRAM clock enable
    53 	output									sdram_cs_n,		// SDRAM chip select (active low)
    54 	output									sdram_ras_n,	// SDRAM row address strobe (active low)
    55 	output									sdram_cas_n,	// SDRAM column address strobe (active low)
    56 	output									sdram_we_n,		// SDRAM write enable (active low)
    57 	output		[ROWADDR_BITS-1:0]	sdram_a,			// SDRAM address
    58 	output reg	[BANKADDR_BITS-1:0]	sdram_ba,		// SDRAM bank address
    59 	output reg	[(DATA_BITS/4)-1:0]	sdram_dqm,		// SDRAM data mask (OE#; 0=active, 1=disabled)
    60 	inout			[DATA_BITS-1:0]		sdram_dq			// SDRAM data bus
    61 );
    63 /****
    64  * Timer values -- don't touch!
    65  ****/
    66 // Calculate clock period in nanoseconds
    67 localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;
    69 // T_rp  ==> 20ns
    70 localparam	TCY_Trp			= (TIME_Trp+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    71 // T_rcd ==> 20ns
    72 localparam	TCY_Trcd			= (TIME_Trcd+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    73 // T_rfc (a.k.a. T_rc) ==> 70ns
    74 localparam	TCY_Trfc			= (TIME_Trfc+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    75 // T_mrd ==> 2 clock cycles
    76 localparam	TCY_Tmrd			= 32'd2;
    77 // Maximum allowed time between two refresh cycles
    78 localparam	TCY_Refresh		= (TIME_Refresh+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    80 localparam	TCY_InitDelay	= (TIME_InitDelay+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    81 localparam	TCY_InitFinal	= (TIME_InitFinal+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    84 /****
    85  * WISHBONE status pins
    86  ****/
    87 // Can't raise bus errors
    88 assign wb_err_o = 1'b0;
    89 // Can't request retries
    90 assign wb_rty_o = 1'b0;
    93 /****
    94  * SDRAM data output buffer
    95  ****/
    96 // OE=1 for output mode, 0 for input
    97 reg sdram_dq_oe;
    98 // SDRAM output register
    99 reg [DATA_BITS-1:0] sdram_dq_r;
   100 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : {DATA_BITS{1'bZ}};
   103 /****
   104  * State timer
   105  * This is used to ensure that the state machine abides by RAM timing
   106  * restrictions.
   107  ****/
   108 reg [31:0] timer;
   111 /****
   112  * MODE logic
   113  ****/
   114 reg  [5:0]  sdram_mode;
   115 reg  [11:0]	sdram_addr;
   116 assign sdram_cs_n		= sdram_mode[3];
   117 assign sdram_ras_n	= sdram_mode[2];
   118 assign sdram_cas_n	= sdram_mode[1];
   119 assign sdram_we_n		= sdram_mode[0];
   120 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
   122 // SDRAM chip instructions
   123 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
   124 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
   125 localparam M_BankActivate		= 6'b0X0011;
   126 localparam M_PrechargeBank		= 6'b100010;
   127 localparam M_PrechargeAll		= 6'b110010;
   128 localparam M_Write				= 6'b100100;
   129 localparam M_WritePrecharge	= 6'b110100;
   130 localparam M_Read					= 6'b100101;
   131 localparam M_ReadPrecharge		= 6'b110101;
   132 localparam M_LoadModeRegister	= 6'b0X0000;
   133 localparam M_Nop					= 6'b0X0111;
   134 localparam M_BurstStop			= 6'b0X0110;
   135 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
   136 localparam M_AutoRefresh		= 6'b0X0001;
   139 /****
   140  * Refresh Timer
   141  ****/
   142 reg [31:0] refresh_timer;
   143 reg refresh_req, refresh_ack, refresh_timer_en;
   144 always @(posedge wb_clk_i) begin
   145 	if (wb_rst_i | !refresh_timer_en) begin
   146 		// Reset; clear timer, unset REFRESH REQUEST
   147 		refresh_req <= 1'b0;
   148 		refresh_timer <= TCY_Refresh - 32'd1;
   149 	end else if (refresh_ack) begin
   150 		// Refresh Ack, clear Refresh Request.
   151 		refresh_req <= 1'b0;
   152 	end else if (refresh_timer == 0) begin
   153 		// Refresh timer timed out, make a Refresh Request and reload the timer
   154 		refresh_req <= 1'b1;
   155 		refresh_timer <= TCY_Refresh - 32'd1;
   156 	end else begin
   157 		// Otherwise just decrement the timer
   158 		refresh_timer <= refresh_timer - 32'd1;
   159 	end
   160 end
   163 /****
   164  * Address decoder
   165  ****/
   166 wire [COLADDR_BITS-1:0] column_addr;
   167 wire [ROWADDR_BITS-1:0] row_addr;
   168 wire [BANKADDR_BITS-1:0] bank_addr;
   170 // Convert a 23-bit linear address into an SDRAM address
   171 assign column_addr	= wb_adr_i[COLADDR_BITS-1:0];
   172 assign bank_addr		= wb_adr_i[COLADDR_BITS+BANKADDR_BITS-1:COLADDR_BITS];
   173 assign row_addr		= wb_adr_i[COLADDR_BITS+BANKADDR_BITS+ROWADDR_BITS-1:COLADDR_BITS+BANKADDR_BITS];
   176 /****
   177  * Finite State Machine
   178  ****/
   179 localparam	ST_INIT1							= 32'd0;
   180 localparam	ST_INIT2							= 32'd1;
   181 localparam	ST_NOP1							= 32'd2;
   182 localparam	ST_PrechargeAll				= 32'd3;
   183 localparam	ST_PrechargeAll_Wait			= 32'd4;
   184 localparam	ST_AutoRefresh1				= 32'd5;
   185 localparam	ST_AutoRefresh1_Wait			= 32'd6;
   186 localparam	ST_AutoRefresh2				= 32'd7;
   187 localparam	ST_AutoRefresh2_Wait			= 32'd8;
   188 localparam	ST_LoadModeRegister			= 32'd9;
   189 localparam	ST_LoadModeRegister_Wait	= 32'd10;
   190 localparam	ST_Spin							= 32'd11;		// <<== main 'spin' / 'idle' state
   191 localparam	ST_Refresh						= 32'd12;
   192 localparam	ST_Refresh_Wait				= 32'd13;
   193 localparam	ST_Activate						= 32'd30;
   194 localparam	ST_Activate_Wait				= 32'd31;
   195 localparam	ST_Write							= 32'd32;
   196 localparam	ST_Read							= 32'd33;
   197 localparam	ST_Read_Wait					= 32'd34;
   198 localparam	ST_Wait_Trp						= 32'd35;
   199 localparam	ST_Ack							= 32'd36;
   202 reg [31:0] state;
   203 always @(posedge wb_clk_i) begin
   204 	if (wb_rst_i) begin
   205 		// Initialise state machine and timer
   206 		state <= ST_INIT1;
   207 		timer <= 32'd0;
   209 		// Clear REFRESH ACK flag and disable refresh timer
   210 		refresh_ack <= 1'b0;
   211 		refresh_timer_en <= 1'b0;
   213 		// Initialisation state for SDRAM
   214 		sdram_cke	<= 1'b0;
   215 		sdram_mode	<= M_Inhibit;
   216 		sdram_addr	<= 0;
   217 		sdram_ba		<= 0;
   218 		sdram_dqm	<= 0;
   219 		sdram_dq_oe	<= 0;				// data output disabled
   220 		sdram_dq_r	<= 0;
   221 	end else begin
   222 		// timer logic
   223 		if (timer > 32'd0) begin
   224 			timer <= timer - 32'd1;
   225 		end
   227 		// state machine logic
   228 		case (state)
   229 			ST_INIT1: begin
   230 					// INIT1: Set up for initial power-up wait
   231 					state <= ST_INIT2;
   232 					timer <= TCY_InitDelay;		// Needs to be >= 100us
   234 					// SDRAM state
   235 					sdram_cke	<= 1'b0;			// clock disabled
   236 					sdram_mode	<= M_Inhibit;
   237 					sdram_addr	<= 0;
   238 					sdram_ba		<= 0;
   239 					sdram_dqm	<= {(DATA_BITS/4){1'b1}};
   240 					sdram_dq_oe	<= 0;				// data output disabled
   241 					sdram_dq_r	<= 0;
   242 				end
   244 			ST_INIT2: begin
   245 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
   246 					// the end of the power-up wait, then bring CKE high.
   247 					if (timer == 32'd0) begin
   248 						// Timer hit zero. Send a NOP.
   249 						state <= ST_NOP1;
   250 					end else if (timer < TCY_InitFinal) begin
   251 						// Timer value is more than zero but less than 50; CKE is on, but
   252 						// keep waiting for the timer to actually expire.
   253 						sdram_cke	<= 1'b1;
   254 						state			<= ST_INIT2;
   255 					end
   256 					sdram_mode <= M_Inhibit;
   257 				end
   259 			ST_NOP1: begin
   260 					// Apply one or more NOP commands to the SDRAM
   261 					sdram_mode <= M_Nop;
   262 					state <= ST_PrechargeAll;
   263 				end
   265 			ST_PrechargeAll: begin
   266 					// Precharge All, then wait T_rp (20ns)
   267 					sdram_mode <= M_PrechargeAll;
   268 					timer <= TCY_Trp - 32'd1;
   269 					state <= ST_PrechargeAll_Wait;
   270 				end
   272 			ST_PrechargeAll_Wait: begin
   273 					// Wait for T_rp after Precharge All
   274 					sdram_mode <= M_Nop;
   275 					if (timer == 32'd0) begin
   276 						// Timer hit zero. Continue
   277 						state <= ST_AutoRefresh1;
   278 					end
   279 				end
   281 			ST_AutoRefresh1: begin
   282 					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
   283 					sdram_mode <= M_AutoRefresh;
   284 					timer <= TCY_Trfc - 32'd1;
   285 					state <= ST_AutoRefresh1_Wait;
   286 				end
   288 			ST_AutoRefresh1_Wait: begin
   289 					// Wait for T_rfc
   290 					sdram_mode <= M_Nop;
   291 					if (timer == 32'd0) begin
   292 						// Timer hit zero. Continue
   293 						state <= ST_AutoRefresh2;
   294 					end
   295 				end
   297 			ST_AutoRefresh2: begin
   298 					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
   299 					sdram_mode <= M_AutoRefresh;
   300 					timer <= TCY_Trfc - 32'd1;
   301 					state <= ST_AutoRefresh2_Wait;
   302 				end
   304 			ST_AutoRefresh2_Wait: begin
   305 					// Wait for T_rfc
   306 					sdram_mode <= M_Nop;
   307 					if (timer == 32'd0) begin
   308 						// Timer hit zero. Continue
   309 						state <= ST_LoadModeRegister;
   310 					end
   311 				end
   313 			ST_LoadModeRegister: begin
   314 					// Load Mode Register
   315 					/**
   316 					 * Mode register:
   317 					 *   - BS0,1  = 00  [RFU]
   318 					 *   - A11,10 = 00  [RFU]
   319 					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
   320 					 *   - A8,7   = 00  [Test Mode off]
   321 					 *   - A6..4  = 010 [CAS Latency = 2 or 3 clocks, set above]
   322 					 *   - A3     = 0   [Burst type = sequential]
   323 					 *   - A2..0  = 000 [Burst length = 1 word]
   324 					 */
   325 					sdram_ba <= 0;
   326 					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
   327 					sdram_mode <= M_LoadModeRegister;
   329 					// Wait T_mrd (2 clock cycles)
   330 					timer <= TCY_Tmrd - 32'd1;
   331 					state <= ST_LoadModeRegister_Wait;
   332 				end
   334 			ST_LoadModeRegister_Wait: begin
   335 					// Wait for LMR to complete
   336 					sdram_mode <= M_Nop;
   337 					sdram_ba <= 0;
   338 					sdram_addr <= 0;
   339 					if (timer == 32'd0) begin
   340 						// Timer hit zero. Continue
   341 						state <= ST_Spin;
   342 					end
   343 				end
   345 			ST_Spin: begin
   346 					// Enable refresh timer
   347 					refresh_timer_en <= 1'b1;
   349 					// Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
   350 					sdram_mode <= M_Inhibit;
   352 					// Check if a refresh is due (these have highest priority)
   353 					if (refresh_req) begin
   354 						// Refresh request received. Ack it and do a refresh.
   355 						refresh_ack <= 1'b1;
   356 						state <= ST_Refresh;
   357 					end else begin
   358 						if (wb_cyc_i & wb_stb_i) begin
   359 							// CYC and STB high. A Wishbone cycle just started.
   360 							state <= ST_Activate;
   361 						end
   362 					end
   363 				end
   365 /////
   366 // Refresh logic
   367 /////
   369 			ST_Refresh: begin
   370 					// Refresh timer timed out; do a refresh run
   371 					// Start by clearing the ACK flag (which was set by the Spin state)
   372 					refresh_ack <= 1'b0;
   373 					// Tell the SDRAM to do a Refresh
   374 					sdram_mode <= M_AutoRefresh;
   375 					// Wait for T_rfc
   376 					timer <= TCY_Trfc;
   377 					state <= ST_Refresh_Wait;
   378 				end
   380 			ST_Refresh_Wait: begin
   381 					// Wait for T_rfc
   382 					sdram_mode <= M_Nop;
   383 					if (timer == 32'd0) begin
   384 						// Timer hit zero. Go back to spin state.
   385 						state <= ST_Spin;
   386 					end
   387 				end
   389 //////
   390 // R/W logic
   391 //////
   392 			ST_Activate: begin
   393 					// Activate the required bank
   394 					sdram_mode <= M_BankActivate;
   395 					sdram_addr <= row_addr;
   396 					sdram_ba   <= bank_addr;
   397 					timer <= TCY_Trcd - 32'd1;
   398 					state <= ST_Activate_Wait;
   399 				end
   401 			ST_Activate_Wait: begin
   402 					// Wait for T_rcd
   403 					sdram_mode <= M_Nop;
   404 					if (timer == 32'd0) begin
   405 						if (wb_we_i) begin
   406 							// Write cycle.
   407 							state <= ST_Write;
   408 						end else begin
   409 							// Read cycle
   410 							state <= ST_Read;
   411 						end
   412 					end
   413 				end
   415 			ST_Write: begin
   416 					// Write cycle handler
   417 					sdram_mode	<= M_WritePrecharge;
   418 					sdram_addr	<= column_addr;
   419 					sdram_dq_r	<= 0;
   420 					sdram_dq_oe	<= 1;			// FPGA drives the DQ bus
   421 					sdram_dqm	<= ~wb_sel_i;
   423 					// Wait T_rp (20ns)
   424 					timer <= TCY_Trp - 32'd1;
   425 					state <= ST_Wait_Trp;
   426 				end
   428 			ST_Read: begin
   429 					// Read cycle handler
   430 					sdram_mode	<= M_ReadPrecharge;
   431 					sdram_addr	<= column_addr;
   432 					sdram_dq_oe	<= 0;			// SDRAM drives the DQ bus
   433 					sdram_dqm	<= 0;			// Grab all the data (easier than playing with WB_SEL...)
   434 					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
   435 					state <= ST_Read_Wait;
   436 				end
   438 			ST_Read_Wait: begin
   439 					// Wait for CAS# latency
   440 					sdram_mode	<= M_Nop;
   441 					sdram_dqm	<= {(DATA_BITS/4){1'b1}};	// Make SDRAM DQ bus float
   442 					if (timer == 32'd0) begin
   443 						// Latch data
   444 						wb_dat_o <= sdram_dq;
   445 						// Wait T_rp (20ns)
   446 						timer <= TCY_Trp - 32'd1;
   447 						state <=	ST_Wait_Trp;
   448 					end
   449 				end
   451 			ST_Wait_Trp: begin
   452 					// Wait for T_rp, then ack
   453 					if (timer == 32'd0) begin
   454 						state <= ST_Ack;
   455 					end
   456 				end
   458 			ST_Ack: begin
   459 					// Ack the transfer to the WISHBONE host
   460 					sdram_mode	<= M_Nop;
   461 					sdram_addr	<= 0;
   462 					sdram_dq_r	<= 0;
   463 					sdram_dq_oe	<= 0;			// SDRAM drives the DQ bus
   464 					sdram_dqm	<= {(DATA_BITS/4){1'b1}};	// mask off DQM
   465 					if (wb_cyc_i & wb_stb_i) begin
   466 						// CYC and STB high, ack the transfer
   467 						wb_ack_o		<= 1'b1;
   468 						state			<= ST_Ack;
   469 					end else begin
   470 						// CYC and STB low, go back and wait for another transaction
   471 						wb_ack_o		<= 1'b0;
   472 						state			<= ST_Spin;
   473 					end
   474 				end
   475 		endcase
   476 	end
   477 end
   479 endmodule