wb_sdram.v

Wed, 11 Aug 2010 01:15:20 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 11 Aug 2010 01:15:20 +0100
changeset 15
da71a5efdf98
parent 14
b541478bbb73
child 16
49f3a5bd860e
permissions
-rw-r--r--

fully parameterise CLOCK_RATE and SDRAM timing

     1 	/****************************************************************************
     2  *
     3  *
     4  ****************************************************************************/
     6 module wb_sdram (
     7 	// Clocks and resets
     8 	input						wb_clk_i,			// WISHBONE clock
     9 	input						wb_rst_i,			// WISHBONE reset
    11 	// WISHBONE bus
    12 	input			[31:0]	wb_adr_i,			// WISHBONE address
    13 	input			[31:0]	wb_dat_i,			// WISHBONE data in
    14 	output reg	[31:0]	wb_dat_o,			// WISHBONE data out
    15 	input			[3:0]		wb_sel_i,			// WISHBONE byte select
    16 	input						wb_we_i,				// WISHBONE write enable (R/#W)
    17 	input						wb_cyc_i,			// WISHBONE cycle
    18 	input						wb_stb_i,			// WISHBONE strobe
    19 	output reg				wb_ack_o,			// WISHBONE cycle acknowledge (data available, DTACK)
    20 	output					wb_err_o,			// WISHBONE bus error
    21 	output					wb_rty_o,			// WISHBONE retry-later
    23 	// SDRAM
    24 	output reg				sdram_cke,			// SDRAM clock enable
    25 	output					sdram_cs_n,			// SDRAM chip select (active low)
    26 	output					sdram_ras_n,		// SDRAM row address strobe (active low)
    27 	output					sdram_cas_n,		// SDRAM column address strobe (active low)
    28 	output					sdram_we_n,			// SDRAM write enable (active low)
    29 	output		[11:0]	sdram_a,				// SDRAM address
    30 	output reg	[1:0]		sdram_ba,			// SDRAM bank address
    31 	output reg	[3:0]		sdram_dqm,			// SDRAM data mask (OE#; 0=active, 1=disabled)
    32 	inout			[31:0]	sdram_dq,			// SDRAM data bus
    34 	// Debugging
    35 	output /*reg*/	[2:0]		debug					// debug bits
    36 );
    39 /****
    40  * Timer values
    41  ****/
    42 // CAS latency -- either 2 or 3   [2010-08-10: tested with CL=3, worked fine]
    43 parameter	CAS_LATENCY		= 3'd2;
    44 // System clock frequency
    45 parameter	CLOCK_RATE		= 25_000_000;
    47 // SDRAM timings in nanoseconds
    48 parameter	TIME_Trp			= 20;
    49 parameter	TIME_Trcd		= 20;
    50 parameter	TIME_Trfc		= 70;
    51 parameter	TIME_Refresh	= 15_625;
    52 parameter	TIME_InitDelay	= 2_000_000;	// 2ms init period
    53 parameter	TIME_InitFinal	= 2_000;			// 2us before the end of the init period, raise CKE
    55 // Calculate clock period in nanoseconds
    56 localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;
    58 // T_rp  ==> 20ns
    59 localparam	TCY_Trp			= (TIME_Trp+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    60 // T_rcd ==> 20ns
    61 localparam	TCY_Trcd			= (TIME_Trcd+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    62 // T_rfc (a.k.a. T_rc) ==> 70ns
    63 localparam	TCY_Trfc			= (TIME_Trfc+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    64 // T_mrd ==> 2 clock cycles
    65 localparam	TCY_Tmrd			= 32'd2;
    66 // Maximum allowed time between two refresh cycles
    67 localparam	TCY_Refresh		= (TIME_Refresh+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    69 localparam	TCY_InitDelay	= (TIME_InitDelay+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    70 localparam	TCY_InitFinal	= (TIME_InitFinal+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    73 /****
    74  * WISHBONE status pins
    75  ****/
    76 // Can't raise bus errors
    77 assign wb_err_o = 1'b0;
    78 // Can't request retries
    79 assign wb_rty_o = 1'b0;
    80 // Lock DEBUG pins low
    81 assign debug = 3'd0;
    84 /****
    85  * SDRAM data output buffer
    86  ****/
    87 // OE=1 for output mode, 0 for input
    88 reg sdram_dq_oe;
    89 // SDRAM output register
    90 reg [31:0] sdram_dq_r;
    91 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    94 /****
    95  * State timer
    96  * This is used to ensure that the state machine abides by RAM timing
    97  * restrictions.
    98  ****/
    99 reg [31:0] timer;
   102 /****
   103  * MODE logic
   104  ****/
   105 reg  [5:0]  sdram_mode;
   106 reg  [11:0]	sdram_addr;
   107 assign sdram_cs_n		= sdram_mode[3];
   108 assign sdram_ras_n	= sdram_mode[2];
   109 assign sdram_cas_n	= sdram_mode[1];
   110 assign sdram_we_n		= sdram_mode[0];
   111 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
   113 // SDRAM chip instructions
   114 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
   115 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
   116 localparam M_BankActivate		= 6'b0X0011;
   117 localparam M_PrechargeBank		= 6'b100010;
   118 localparam M_PrechargeAll		= 6'b110010;
   119 localparam M_Write				= 6'b100100;
   120 localparam M_WritePrecharge	= 6'b110100;
   121 localparam M_Read					= 6'b100101;
   122 localparam M_ReadPrecharge		= 6'b110101;
   123 localparam M_LoadModeRegister	= 6'b0X0000;
   124 localparam M_Nop					= 6'b0X0111;
   125 localparam M_BurstStop			= 6'b0X0110;
   126 localparam M_Inhibit				= 6'b0X1XXX;		// maybe X1111?
   127 localparam M_AutoRefresh		= 6'b0X0001;
   130 /****
   131  * Refresh Timer
   132  ****/
   133 reg [31:0] refresh_timer;
   134 reg refresh_req, refresh_ack, refresh_timer_en;
   135 always @(posedge wb_clk_i) begin
   136 	if (wb_rst_i | !refresh_timer_en) begin
   137 		// Reset; clear timer, unset REFRESH REQUEST
   138 		refresh_req <= 1'b0;
   139 		refresh_timer <= TCY_Refresh - 32'd1;
   140 	end else if (refresh_ack) begin
   141 		// Refresh Ack, clear Refresh Request.
   142 		refresh_req <= 1'b0;
   143 	end else if (refresh_timer == 0) begin
   144 		// Refresh timer timed out, make a Refresh Request and reload the timer
   145 		refresh_req <= 1'b1;
   146 		refresh_timer <= TCY_Refresh - 32'd1;
   147 	end else begin
   148 		// Otherwise just decrement the timer
   149 		refresh_timer <= refresh_timer - 32'd1;
   150 	end
   151 end
   154 /****
   155  * Address decoder
   156  ****/
   157 wire [8:0] column_addr;
   158 wire [11:0] row_addr;
   159 wire [1:0] bank_addr;
   161 // Convert a 23-bit linear address into an SDRAM address
   162 assign column_addr	= wb_adr_i[8:0];
   163 assign bank_addr		= wb_adr_i[10:9];
   164 assign row_addr		= wb_adr_i[22:11];
   167 /****
   168  * Finite State Machine
   169  ****/
   170 localparam	ST_INIT1							= 32'd0;
   171 localparam	ST_INIT2							= 32'd1;
   172 localparam	ST_NOP1							= 32'd2;
   173 localparam	ST_PrechargeAll				= 32'd3;
   174 localparam	ST_PrechargeAll_Wait			= 32'd4;
   175 localparam	ST_AutoRefresh1				= 32'd5;
   176 localparam	ST_AutoRefresh1_Wait			= 32'd6;
   177 localparam	ST_AutoRefresh2				= 32'd7;
   178 localparam	ST_AutoRefresh2_Wait			= 32'd8;
   179 localparam	ST_LoadModeRegister			= 32'd9;
   180 localparam	ST_LoadModeRegister_Wait	= 32'd10;
   181 localparam	ST_Spin							= 32'd11;		// <<== main 'spin' / 'idle' state
   182 localparam	ST_Refresh						= 32'd12;
   183 localparam	ST_Refresh_Wait				= 32'd13;
   184 localparam	ST_Activate						= 32'd30;
   185 localparam	ST_Activate_Wait				= 32'd31;
   186 localparam	ST_Write							= 32'd32;
   187 localparam	ST_Read							= 32'd33;
   188 localparam	ST_Read_Wait					= 32'd34;
   189 localparam	ST_Wait_Trp						= 32'd35;
   190 localparam	ST_Ack							= 32'd36;
   193 reg [31:0] state;
   194 always @(posedge wb_clk_i) begin
   195 	if (wb_rst_i) begin
   196 		// Initialise state machine and timer
   197 		state <= ST_INIT1;
   198 		timer <= 32'd0;
   200 		// Clear REFRESH ACK flag and disable refresh timer
   201 		refresh_ack <= 1'b0;
   202 		refresh_timer_en <= 1'b0;
   204 		// Initialisation state for SDRAM
   205 		sdram_cke	<= 1'b0;
   206 		sdram_mode	<= M_Inhibit;
   207 		sdram_addr	<= 12'h000;
   208 		sdram_ba		<= 2'b00;
   209 		sdram_dqm	<= 4'b0000;
   210 		sdram_dq_oe	<= 1'b0;			// data output disabled
   211 		sdram_dq_r	<= 32'd0;
   212 	end else begin
   213 		// timer logic
   214 		if (timer > 32'd0) begin
   215 			timer <= timer - 32'd1;
   216 		end
   218 		// state machine logic
   219 		case (state)
   220 			ST_INIT1: begin
   221 					// INIT1: Set up for initial power-up wait
   222 					state <= ST_INIT2;
   223 					timer <= TCY_InitDelay;		// Needs to be >= 100us
   225 					// SDRAM state
   226 					sdram_cke	<= 1'b0;			// clock disabled
   227 					sdram_mode	<= M_Inhibit;
   228 					sdram_addr	<= 12'h000;
   229 					sdram_ba		<= 2'b00;
   230 					sdram_dqm	<= 4'b1111;
   231 					sdram_dq_oe	<= 1'b0;			// data output disabled
   232 					sdram_dq_r	<= 32'd0;
   233 				end
   235 			ST_INIT2: begin
   236 					// INIT2: Power-up wait. Keep CKE low until ~50 cycles before
   237 					// the end of the power-up wait, then bring CKE high.
   238 					if (timer == 32'd0) begin
   239 						// Timer hit zero. Send a NOP.
   240 						state <= ST_NOP1;
   241 					end else if (timer < TCY_InitFinal) begin
   242 						// Timer value is more than zero but less than 50; CKE is on, but
   243 						// keep waiting for the timer to actually expire.
   244 						sdram_cke	<= 1'b1;
   245 						state			<= ST_INIT2;
   246 					end
   247 					sdram_mode <= M_Inhibit;
   248 				end
   250 			ST_NOP1: begin
   251 					// Apply one or more NOP commands to the SDRAM
   252 					sdram_mode <= M_Nop;
   253 					state <= ST_PrechargeAll;
   254 				end
   256 			ST_PrechargeAll: begin
   257 					// Precharge All, then wait T_rp (20ns)
   258 					sdram_mode <= M_PrechargeAll;
   259 					timer <= TCY_Trp - 32'd1;
   260 					state <= ST_PrechargeAll_Wait;
   261 				end
   263 			ST_PrechargeAll_Wait: begin
   264 					// Wait for T_rp after Precharge All
   265 					sdram_mode <= M_Nop;
   266 					if (timer == 32'd0) begin
   267 						// Timer hit zero. Continue
   268 						state <= ST_AutoRefresh1;
   269 					end
   270 				end
   272 			ST_AutoRefresh1: begin
   273 					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
   274 					sdram_mode <= M_AutoRefresh;
   275 					timer <= TCY_Trfc - 32'd1;
   276 					state <= ST_AutoRefresh1_Wait;
   277 				end
   279 			ST_AutoRefresh1_Wait: begin
   280 					// Wait for T_rfc
   281 					sdram_mode <= M_Nop;
   282 					if (timer == 32'd0) begin
   283 						// Timer hit zero. Continue
   284 						state <= ST_AutoRefresh2;
   285 					end
   286 				end
   288 			ST_AutoRefresh2: begin
   289 					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
   290 					sdram_mode <= M_AutoRefresh;
   291 					timer <= TCY_Trfc - 32'd1;
   292 					state <= ST_AutoRefresh2_Wait;
   293 				end
   295 			ST_AutoRefresh2_Wait: begin
   296 					// Wait for T_rfc
   297 					sdram_mode <= M_Nop;
   298 					if (timer == 32'd0) begin
   299 						// Timer hit zero. Continue
   300 						state <= ST_LoadModeRegister;
   301 					end
   302 				end
   304 			ST_LoadModeRegister: begin
   305 					// Load Mode Register
   306 					/**
   307 					 * Mode register:
   308 					 *   - BS0,1  = 00  [RFU]
   309 					 *   - A11,10 = 00  [RFU]
   310 					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
   311 					 *   - A8,7   = 00  [Test Mode off]
   312 					 *   - A6..4  = 010 [CAS Latency = 2 or 3 clocks, set above]
   313 					 *   - A3     = 0   [Burst type = sequential]
   314 					 *   - A2..0  = 000 [Burst length = 1 word]
   315 					 */
   316 					sdram_ba <= 2'b00;
   317 					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
   318 					sdram_mode <= M_LoadModeRegister;
   320 					// Wait T_mrd (2 clock cycles)
   321 					timer <= TCY_Tmrd - 32'd1;
   322 					state <= ST_LoadModeRegister_Wait;
   323 				end
   325 			ST_LoadModeRegister_Wait: begin
   326 					// Wait for LMR to complete
   327 					sdram_mode <= M_Nop;
   328 					sdram_ba <= 2'd0;
   329 					sdram_addr <= 12'd0;
   330 					if (timer == 32'd0) begin
   331 						// Timer hit zero. Continue
   332 						state <= ST_Spin;
   333 					end
   334 				end
   336 			ST_Spin: begin
   337 					// Enable refresh timer
   338 					refresh_timer_en <= 1'b1;
   340 					// Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
   341 					sdram_mode <= M_Inhibit;
   343 					// Check if a refresh is due (these have highest priority)
   344 					if (refresh_req) begin
   345 						// Refresh request received. Ack it and do a refresh.
   346 						refresh_ack <= 1'b1;
   347 						state <= ST_Refresh;
   348 					end else begin
   349 						if (wb_cyc_i & wb_stb_i) begin
   350 							// CYC and STB high. A Wishbone cycle just started.
   351 							state <= ST_Activate;
   352 						end
   353 					end
   354 				end
   356 /////
   357 // Refresh logic
   358 /////
   360 			ST_Refresh: begin
   361 					// Refresh timer timed out; do a refresh run
   362 					// Start by clearing the ACK flag (which was set by the Spin state)
   363 					refresh_ack <= 1'b0;
   364 					// Tell the SDRAM to do a Refresh
   365 					sdram_mode <= M_AutoRefresh;
   366 					// Wait for T_rfc
   367 					timer <= TCY_Trfc;
   368 					state <= ST_Refresh_Wait;
   369 				end
   371 			ST_Refresh_Wait: begin
   372 					// Wait for T_rfc
   373 					sdram_mode <= M_Nop;
   374 					if (timer == 32'd0) begin
   375 						// Timer hit zero. Go back to spin state.
   376 						state <= ST_Spin;
   377 					end
   378 				end
   380 //////
   381 // R/W logic
   382 //////
   383 			ST_Activate: begin
   384 					// Activate the required bank
   385 					sdram_mode <= M_BankActivate;
   386 					sdram_addr <= row_addr;
   387 					sdram_ba   <= bank_addr;
   388 					timer <= TCY_Trcd - 32'd1;
   389 					state <= ST_Activate_Wait;
   390 				end
   392 			ST_Activate_Wait: begin
   393 					// Wait for T_rcd
   394 					sdram_mode <= M_Nop;
   395 					if (timer == 32'd0) begin
   396 						if (wb_we_i) begin
   397 							// Write cycle.
   398 							state <= ST_Write;
   399 						end else begin
   400 							// Read cycle
   401 							state <= ST_Read;
   402 						end
   403 					end
   404 				end
   406 			ST_Write: begin
   407 					// Write cycle handler
   408 					sdram_mode	<= M_WritePrecharge;
   409 					sdram_addr	<= column_addr;
   410 					sdram_dq_r	<= wb_dat_i;
   411 					sdram_dq_oe	<= 1'b1;		// FPGA drives the DQ bus
   412 					sdram_dqm	<= ~wb_sel_i;
   414 					// Wait T_rp (20ns)
   415 					timer <= TCY_Trp - 32'd1;
   416 					state <= ST_Wait_Trp;
   417 				end
   419 			ST_Read: begin
   420 					// Read cycle handler
   421 					sdram_mode	<= M_ReadPrecharge;
   422 					sdram_addr	<= column_addr;
   423 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   424 					sdram_dqm	<= 4'b0000;	// Grab all the data (it's just easier that way...)
   425 					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
   426 					state <= ST_Read_Wait;
   427 				end
   429 			ST_Read_Wait: begin
   430 					// Wait for CAS# latency
   431 					sdram_mode	<= M_Nop;
   432 					sdram_dqm	<= 4'b1111;	// Make SDRAM DQ bus float
   433 					if (timer == 32'd0) begin
   434 						// Latch data
   435 						wb_dat_o <= sdram_dq;
   436 						// Wait T_rp (20ns)
   437 						timer <= TCY_Trp - 32'd1;
   438 						state <=	ST_Wait_Trp;
   439 					end
   440 				end
   442 			ST_Wait_Trp: begin
   443 					// Wait for T_rp, then ack
   444 					if (timer == 32'd0) begin
   445 						state <= ST_Ack;
   446 					end
   447 				end
   449 			ST_Ack: begin
   450 					// Ack the transfer to the WISHBONE host
   451 					sdram_mode	<= M_Nop;
   452 					sdram_addr	<= 32'd0;
   453 					sdram_dq_r	<= 32'd0;
   454 					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   455 					sdram_dqm	<= 4'b1111;	// mask off DQM
   456 					if (wb_cyc_i & wb_stb_i) begin
   457 						// CYC and STB high, ack the transfer
   458 						wb_ack_o		<= 1'b1;
   459 						state			<= ST_Ack;
   460 					end else begin
   461 						// CYC and STB low, go back and wait for another transaction
   462 						wb_ack_o		<= 1'b0;
   463 						state			<= ST_Spin;
   464 					end
   465 				end
   466 		endcase
   467 	end
   468 end
   470 endmodule