Tue, 10 Aug 2010 17:42:18 +0100
add NOP after read to avoid bus contention when doing back-to-back R/Ws
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * SDRAM data output buffer
41 ****/
42 // OE=1 for output mode, 0 for input
43 reg sdram_dq_oe;
44 // SDRAM output register
45 reg [31:0] sdram_dq_r;
46 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
50 /****
51 * State timer
52 * This is used to ensure that the state machine abides by RAM timing
53 * restrictions.
54 ****/
55 reg [31:0] timer;
58 /****
59 * MODE logic
60 ****/
61 reg [5:0] sdram_mode;
62 reg [11:0] sdram_addr;
63 assign sdram_cs_n = sdram_mode[3];
64 assign sdram_ras_n = sdram_mode[2];
65 assign sdram_cas_n = sdram_mode[1];
66 assign sdram_we_n = sdram_mode[0];
67 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
69 // SDRAM chip instructions
70 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
71 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
72 localparam M_BankActivate = 6'b0X0011;
73 localparam M_PrechargeBank = 6'b100010;
74 localparam M_PrechargeAll = 6'b110010;
75 localparam M_Write = 6'b100100;
76 localparam M_WritePrecharge = 6'b110100;
77 localparam M_Read = 6'b100101;
78 localparam M_ReadPrecharge = 6'b110101;
79 localparam M_LoadModeRegister = 6'b0X0000;
80 localparam M_Nop = 6'b0X0111;
81 localparam M_BurstStop = 6'b0X0110;
82 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
83 localparam M_AutoRefresh = 6'b0X0001;
86 /****
87 * Refresh Timer
88 ****/
89 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
90 reg [31:0] refresh_timer;
91 reg refresh_req, refresh_ack, refresh_timer_en;
92 always @(posedge wb_clk_i) begin
93 if (wb_rst_i | !refresh_timer_en) begin
94 // Reset; clear timer, unset REFRESH REQUEST
95 refresh_req <= 1'b0;
96 refresh_timer <= REFRESH_INTERVAL;
97 end else if (refresh_ack) begin
98 // Refresh Ack, clear Refresh Request.
99 refresh_req <= 1'b0;
100 end else if (refresh_timer == 0) begin
101 // Refresh timer timed out, make a Refresh Request and reload the timer
102 refresh_req <= 1'b1;
103 refresh_timer <= REFRESH_INTERVAL;
104 end else begin
105 // Otherwise just decrement the timer
106 refresh_timer <= refresh_timer - 32'd1;
107 end
108 end
110 assign debug = { 1'b0, refresh_req, refresh_ack };
113 /****
114 * Address decoder
115 ****/
116 wire [8:0] column_addr;
117 wire [11:0] row_addr;
118 wire [1:0] bank_addr;
120 // Convert a 22-bit linear address into an SDRAM address
121 assign column_addr = wb_adr_i[8:0];
122 assign bank_addr = wb_adr_i[10:9];
123 assign row_addr = wb_adr_i[21:11];
126 /****
127 * Finite State Machine
128 ****/
129 localparam ST_INIT1 = 32'd0;
130 localparam ST_INIT2 = 32'd1;
131 localparam ST_NOP1 = 32'd2;
132 localparam ST_PrechargeAll = 32'd3;
133 localparam ST_PrechargeAll_Wait = 32'd4;
134 localparam ST_AutoRefresh1 = 32'd5;
135 localparam ST_AutoRefresh1_Wait = 32'd6;
136 localparam ST_AutoRefresh2 = 32'd7;
137 localparam ST_AutoRefresh2_Wait = 32'd8;
138 localparam ST_LoadModeRegister = 32'd9;
139 localparam ST_LoadModeRegister_Wait = 32'd10;
140 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
141 localparam ST_Refresh = 32'd12;
142 localparam ST_Refresh_Wait = 32'd13;
143 localparam ST_Test_Activate = 32'd500;
144 localparam ST_Test_Activate_Wait = 32'd501;
145 localparam ST_Test_Read = 32'd502;
146 localparam ST_Test_Read_Wait = 32'd503;
147 localparam ST_Test_Read_Finish = 32'd504;
148 localparam ST_Test_Write = 32'd505;
149 localparam ST_Test_Precharge_All = 32'd506;
150 localparam ST_Test_Precharge_All_Wait = 32'd507;
152 reg [31:0] state;
153 always @(posedge wb_clk_i) begin
154 if (wb_rst_i) begin
155 // Initialise state machine and timer
156 state <= ST_INIT1;
157 // debug <= 3'd0;
158 timer <= 32'd0;
160 // Clear REFRESH ACK flag and disable refresh timer
161 refresh_ack <= 1'b0;
162 refresh_timer_en <= 1'b0;
164 // Initialisation state for SDRAM
165 sdram_cke <= 1'b0;
166 sdram_mode <= M_Inhibit;
167 sdram_addr <= 12'h000;
168 sdram_ba <= 2'b00;
169 sdram_dqm <= 4'b0000;
170 sdram_dq_oe <= 1'b0; // data output disabled
171 sdram_dq_r <= 32'd0;
172 end else begin
173 // timer logic
174 if (timer > 32'd0) begin
175 timer <= timer - 32'd1;
176 end
178 // state machine logic
179 case (state)
180 ST_INIT1: begin
181 // INIT1: Set up for initial power-up wait
182 state <= ST_INIT2;
183 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
185 // SDRAM state
186 sdram_cke <= 1'b0; // clock disabled
187 sdram_mode <= M_Inhibit;
188 sdram_addr <= 12'h000;
189 sdram_ba <= 2'b00;
190 sdram_dqm <= 4'b1111;
191 sdram_dq_oe <= 1'b0; // data output disabled
192 sdram_dq_r <= 32'd0;
193 end
195 ST_INIT2: begin
196 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
197 // the end of the power-up wait, then bring CKE high.
198 if (timer == 32'd0) begin
199 // Timer hit zero. Send a NOP.
200 state <= ST_NOP1;
201 end else if (timer < 32'd50) begin
202 // Timer value is more than zero but less than 50; CKE is on, but
203 // keep waiting for the timer to actually expire.
204 sdram_cke <= 1'b1;
205 state <= ST_INIT2;
206 // debug <= 3'd1;
207 end
208 sdram_mode <= M_Inhibit;
209 end
211 ST_NOP1: begin
212 // Apply one or more NOP commands to the SDRAM
213 sdram_mode <= M_Nop;
214 state <= ST_PrechargeAll;
215 end
217 ST_PrechargeAll: begin
218 // Precharge All, then wait T_rp (20ns)
219 sdram_mode <= M_PrechargeAll;
220 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
221 state <= ST_PrechargeAll_Wait;
222 end
224 ST_PrechargeAll_Wait: begin
225 // Wait for T_rp after Precharge All
226 sdram_mode <= M_Nop;
227 if (timer == 32'd0) begin
228 // Timer hit zero. Continue
229 state <= ST_AutoRefresh1;
230 end
231 end
233 ST_AutoRefresh1: begin
234 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
235 sdram_mode <= M_AutoRefresh;
236 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
237 state <= ST_AutoRefresh1_Wait;
238 end
240 ST_AutoRefresh1_Wait: begin
241 // Wait for T_rfc
242 sdram_mode <= M_Nop;
243 if (timer == 32'd0) begin
244 // Timer hit zero. Continue
245 state <= ST_AutoRefresh2;
246 end
247 end
249 ST_AutoRefresh2: begin
250 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
251 sdram_mode <= M_AutoRefresh;
252 timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE
253 state <= ST_AutoRefresh2_Wait;
254 end
256 ST_AutoRefresh2_Wait: begin
257 // Wait for T_rfc
258 sdram_mode <= M_Nop;
259 if (timer == 32'd0) begin
260 // Timer hit zero. Continue
261 state <= ST_LoadModeRegister;
262 end
263 end
265 ST_LoadModeRegister: begin
266 // Load Mode Register
267 /**
268 * Mode register:
269 * - BS0,1 = 00 [RFU]
270 * - A11,10 = 00 [RFU]
271 * - A9 = 0 [WBL -- write burst length same as read burst length]
272 * - A8,7 = 00 [Test Mode off]
273 * - A6..4 = 010 [CAS Latency = 2 clocks]
274 * - A3 = 0 [Burst type = sequential]
275 * - A2..0 = 000 [Burst length = 1 word]
276 */
277 sdram_ba <= 2'b00;
278 sdram_addr <= 12'b00_0_00_010_000;
279 sdram_mode <= M_LoadModeRegister;
281 // Wait T_mrd (2 clock cycles)
282 timer <= 32'd1; // (2cy)-1 ---> TIMER HERE
283 state <= ST_LoadModeRegister_Wait;
284 end
286 ST_LoadModeRegister_Wait: begin
287 // Wait for LMR to complete
288 sdram_mode <= M_Nop;
289 sdram_ba <= 2'd0;
290 sdram_addr <= 12'd0;
291 if (timer == 32'd0) begin
292 // Timer hit zero. Continue
293 state <= ST_Spin;
294 end
295 end
297 ST_Spin: begin
298 // Enable refresh timer
299 refresh_timer_en <= 1'b1;
301 sdram_mode <= M_Inhibit;
303 if (refresh_req) begin
304 // Refresh request received. Ack it and do a refresh.
305 refresh_ack <= 1'b1;
306 state <= ST_Refresh;
307 end else begin
308 //state <= ST_Spin; // NOTE: turned off to run a ram test...
309 state <= ST_Test_Activate;
310 end
311 end
313 ST_Refresh: begin
314 // Refresh timer timed out; do a refresh run
315 // Start by clearing the ACK flag (which was set by the Spin state)
316 refresh_ack <= 1'b0;
317 // Tell the SDRAM to do a Refresh
318 sdram_mode <= M_AutoRefresh;
319 // Wait for T_rfc
320 timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE
321 state <= ST_Refresh_Wait;
322 end
324 ST_Refresh_Wait: begin
325 // Wait for T_rfc
326 sdram_mode <= M_Nop;
327 if (timer == 32'd0) begin
328 // Timer hit zero. Go back to spin state.
329 state <= ST_Spin;
330 end
331 end
333 ST_Test_Activate: begin
334 // Activate bank
335 sdram_mode <= M_BankActivate;
336 sdram_addr <= row_addr;
337 sdram_ba <= bank_addr;
338 timer <= 32'd0; // wait Trcd (20ns ideally, this is 40ns) ---> TIMER HERE
339 state <= ST_Test_Activate_Wait;
340 end
342 ST_Test_Activate_Wait: begin
343 // Wait for Activate Bank to complete
344 sdram_mode <= M_Nop;
345 if (timer == 32'd0) begin
346 state <= ST_Test_Read;
347 end
348 end
350 ST_Test_Read: begin
351 // Do the Read operation
352 sdram_mode <= M_Read;
353 sdram_addr <= column_addr;
354 sdram_dqm <= 4'b0000; // Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
355 timer <= 32'd2 - 32'd1; // wait CAS# Latency (2 clock cycles) ---> TIMER HERE
356 state <= ST_Test_Read_Wait;
357 end
359 ST_Test_Read_Wait: begin
360 // Wait for CAS latency
361 sdram_mode <= M_Nop;
362 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
363 if (timer == 32'd0) begin
364 state <= ST_Test_Read_Finish;
365 // TODO: capture data locally
366 end
367 end
369 ST_Test_Read_Finish: begin
370 // Additional NOP after read to avoid bus contention if next transaction is a write
371 sdram_mode <= M_Nop;
372 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
373 state <= ST_Test_Write;
374 end
376 ST_Test_Write: begin
377 // Write to SDRAM
378 sdram_mode <= M_Write;
379 sdram_addr <= column_addr;
380 sdram_dq_r <= 32'h55AA_BCDE;
381 sdram_dq_oe <= 1'b1; // output enable
382 sdram_dqm <= 4'b0000; // Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
383 state <= ST_Test_Precharge_All;
384 end
386 ST_Test_Precharge_All: begin
387 // Precharge All
388 sdram_mode <= M_PrechargeAll;
389 sdram_addr <= 12'd0;
390 sdram_dq_oe <= 1'b0; // output disable
391 sdram_dqm <= 4'b1111; // Disable SDRAM output buffers
392 sdram_dq_r <= 32'd0;
393 state <= ST_Spin;
394 // Wait T_rp (20ns)
395 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE
396 state <= ST_Test_Precharge_All_Wait;
397 end
399 ST_Test_Precharge_All_Wait: begin
400 // Wait for T_rp after Precharge All
401 sdram_mode <= M_Nop;
402 if (timer == 32'd0) begin
403 // Timer hit zero. Continue
404 state <= ST_Spin;
405 end
406 end
407 endcase
408 end
409 end
411 endmodule