Tue, 10 Aug 2010 22:14:22 +0100
[wb_sdram] lock debug pins low
1 /****************************************************************************
2 *
3 *
4 ****************************************************************************/
6 module wb_sdram (
7 // Clocks and resets
8 input wb_clk_i, // WISHBONE clock
9 input wb_rst_i, // WISHBONE reset
11 // WISHBONE bus
12 input [31:0] wb_adr_i, // WISHBONE address
13 input [31:0] wb_dat_i, // WISHBONE data in
14 output reg [31:0] wb_dat_o, // WISHBONE data out
15 input [3:0] wb_sel_i, // WISHBONE byte select
16 input wb_we_i, // WISHBONE write enable (R/#W)
17 input wb_cyc_i, // WISHBONE cycle
18 input wb_stb_i, // WISHBONE strobe
19 output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK)
20 output wb_err_o, // WISHBONE bus error
21 output wb_rty_o, // WISHBONE retry-later
23 // SDRAM
24 output reg sdram_cke, // SDRAM clock enable
25 output sdram_cs_n, // SDRAM chip select (active low)
26 output sdram_ras_n, // SDRAM row address strobe (active low)
27 output sdram_cas_n, // SDRAM column address strobe (active low)
28 output sdram_we_n, // SDRAM write enable (active low)
29 output [11:0] sdram_a, // SDRAM address
30 output reg [1:0] sdram_ba, // SDRAM bank address
31 output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled)
32 inout [31:0] sdram_dq, // SDRAM data bus
34 // Debugging
35 output /*reg*/ [2:0] debug // debug bits
36 );
39 /****
40 * Timer values
41 ****/
42 // CAS latency -- either 2 or 3
43 parameter CAS_LATENCY = 3'd2;
44 // T_rp ==> 20ns
45 parameter TIME_Trp = 32'd1;
46 // T_rcd ==> 20ns
47 parameter TIME_Trcd = 32'd1;
48 // T_rfc (a.k.a. T_rc) ==> 70ns
49 parameter TIME_Trfc = 32'd2;
50 // T_mrd ==> 2 clock cycles
51 parameter TIME_Tmrd = 32'd2;
54 /****
55 * WISHBONE status pins
56 ****/
57 // Can't raise bus errors
58 assign wb_err_o = 1'b0;
59 // Can't request retries
60 assign wb_rty_o = 1'b0;
61 // Lock DEBUG pins low
62 assign debug = 3'd0;
64 /****
65 * SDRAM data output buffer
66 ****/
67 // OE=1 for output mode, 0 for input
68 reg sdram_dq_oe;
69 // SDRAM output register
70 reg [31:0] sdram_dq_r;
71 assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
75 /****
76 * State timer
77 * This is used to ensure that the state machine abides by RAM timing
78 * restrictions.
79 ****/
80 reg [31:0] timer;
83 /****
84 * MODE logic
85 ****/
86 reg [5:0] sdram_mode;
87 reg [11:0] sdram_addr;
88 assign sdram_cs_n = sdram_mode[3];
89 assign sdram_ras_n = sdram_mode[2];
90 assign sdram_cas_n = sdram_mode[1];
91 assign sdram_we_n = sdram_mode[0];
92 assign sdram_a = {sdram_addr[11], (sdram_mode[5] ? sdram_mode[4] : sdram_addr[10]), sdram_addr[9:0]};
94 // SDRAM chip instructions
95 // The bit order is as specified in the ISSI datasheet: A10 Override, A10, CS#, RAS#, CAS#, WE#.
96 // If A10 Override is set, then A10 will be overridden to the value specified in the M_ constant.
97 localparam M_BankActivate = 6'b0X0011;
98 localparam M_PrechargeBank = 6'b100010;
99 localparam M_PrechargeAll = 6'b110010;
100 localparam M_Write = 6'b100100;
101 localparam M_WritePrecharge = 6'b110100;
102 localparam M_Read = 6'b100101;
103 localparam M_ReadPrecharge = 6'b110101;
104 localparam M_LoadModeRegister = 6'b0X0000;
105 localparam M_Nop = 6'b0X0111;
106 localparam M_BurstStop = 6'b0X0110;
107 localparam M_Inhibit = 6'b0X1XXX; // maybe X1111?
108 localparam M_AutoRefresh = 6'b0X0001;
111 /****
112 * Refresh Timer
113 ****/
114 parameter REFRESH_INTERVAL = 32'd390 - 32'd1;
115 reg [31:0] refresh_timer;
116 reg refresh_req, refresh_ack, refresh_timer_en;
117 always @(posedge wb_clk_i) begin
118 if (wb_rst_i | !refresh_timer_en) begin
119 // Reset; clear timer, unset REFRESH REQUEST
120 refresh_req <= 1'b0;
121 refresh_timer <= REFRESH_INTERVAL;
122 end else if (refresh_ack) begin
123 // Refresh Ack, clear Refresh Request.
124 refresh_req <= 1'b0;
125 end else if (refresh_timer == 0) begin
126 // Refresh timer timed out, make a Refresh Request and reload the timer
127 refresh_req <= 1'b1;
128 refresh_timer <= REFRESH_INTERVAL;
129 end else begin
130 // Otherwise just decrement the timer
131 refresh_timer <= refresh_timer - 32'd1;
132 end
133 end
136 /****
137 * Address decoder
138 ****/
139 wire [8:0] column_addr;
140 wire [11:0] row_addr;
141 wire [1:0] bank_addr;
143 // Convert a 23-bit linear address into an SDRAM address
144 assign column_addr = wb_adr_i[8:0];
145 assign bank_addr = wb_adr_i[10:9];
146 assign row_addr = wb_adr_i[22:11];
149 /****
150 * Finite State Machine
151 ****/
152 localparam ST_INIT1 = 32'd0;
153 localparam ST_INIT2 = 32'd1;
154 localparam ST_NOP1 = 32'd2;
155 localparam ST_PrechargeAll = 32'd3;
156 localparam ST_PrechargeAll_Wait = 32'd4;
157 localparam ST_AutoRefresh1 = 32'd5;
158 localparam ST_AutoRefresh1_Wait = 32'd6;
159 localparam ST_AutoRefresh2 = 32'd7;
160 localparam ST_AutoRefresh2_Wait = 32'd8;
161 localparam ST_LoadModeRegister = 32'd9;
162 localparam ST_LoadModeRegister_Wait = 32'd10;
163 localparam ST_Spin = 32'd11; // <<== main 'spin' / 'idle' state
164 localparam ST_Refresh = 32'd12;
165 localparam ST_Refresh_Wait = 32'd13;
166 localparam ST_Activate = 32'd30;
167 localparam ST_Activate_Wait = 32'd31;
168 localparam ST_Write = 32'd32;
169 localparam ST_Read = 32'd33;
170 localparam ST_Read_Wait = 32'd34;
171 localparam ST_Wait_Trp = 32'd35;
172 localparam ST_Ack = 32'd36;
175 reg [31:0] state;
176 always @(posedge wb_clk_i) begin
177 if (wb_rst_i) begin
178 // Initialise state machine and timer
179 state <= ST_INIT1;
180 timer <= 32'd0;
182 // Clear REFRESH ACK flag and disable refresh timer
183 refresh_ack <= 1'b0;
184 refresh_timer_en <= 1'b0;
186 // Initialisation state for SDRAM
187 sdram_cke <= 1'b0;
188 sdram_mode <= M_Inhibit;
189 sdram_addr <= 12'h000;
190 sdram_ba <= 2'b00;
191 sdram_dqm <= 4'b0000;
192 sdram_dq_oe <= 1'b0; // data output disabled
193 sdram_dq_r <= 32'd0;
194 end else begin
195 // timer logic
196 if (timer > 32'd0) begin
197 timer <= timer - 32'd1;
198 end
200 // state machine logic
201 case (state)
202 ST_INIT1: begin
203 // INIT1: Set up for initial power-up wait
204 state <= ST_INIT2;
205 timer <= 32'd50_000; // TODO: dependent on core clock rate. Needs to be >= 100us
207 // SDRAM state
208 sdram_cke <= 1'b0; // clock disabled
209 sdram_mode <= M_Inhibit;
210 sdram_addr <= 12'h000;
211 sdram_ba <= 2'b00;
212 sdram_dqm <= 4'b1111;
213 sdram_dq_oe <= 1'b0; // data output disabled
214 sdram_dq_r <= 32'd0;
215 end
217 ST_INIT2: begin
218 // INIT2: Power-up wait. Keep CKE low until ~50 cycles before
219 // the end of the power-up wait, then bring CKE high.
220 if (timer == 32'd0) begin
221 // Timer hit zero. Send a NOP.
222 state <= ST_NOP1;
223 end else if (timer < 32'd50) begin
224 // Timer value is more than zero but less than 50; CKE is on, but
225 // keep waiting for the timer to actually expire.
226 sdram_cke <= 1'b1;
227 state <= ST_INIT2;
228 end
229 sdram_mode <= M_Inhibit;
230 end
232 ST_NOP1: begin
233 // Apply one or more NOP commands to the SDRAM
234 sdram_mode <= M_Nop;
235 state <= ST_PrechargeAll;
236 end
238 ST_PrechargeAll: begin
239 // Precharge All, then wait T_rp (20ns)
240 sdram_mode <= M_PrechargeAll;
241 timer <= TIME_Trp - 32'd1;
242 state <= ST_PrechargeAll_Wait;
243 end
245 ST_PrechargeAll_Wait: begin
246 // Wait for T_rp after Precharge All
247 sdram_mode <= M_Nop;
248 if (timer == 32'd0) begin
249 // Timer hit zero. Continue
250 state <= ST_AutoRefresh1;
251 end
252 end
254 ST_AutoRefresh1: begin
255 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each
256 sdram_mode <= M_AutoRefresh;
257 timer <= TIME_Trfc - 32'd1;
258 state <= ST_AutoRefresh1_Wait;
259 end
261 ST_AutoRefresh1_Wait: begin
262 // Wait for T_rfc
263 sdram_mode <= M_Nop;
264 if (timer == 32'd0) begin
265 // Timer hit zero. Continue
266 state <= ST_AutoRefresh2;
267 end
268 end
270 ST_AutoRefresh2: begin
271 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each
272 sdram_mode <= M_AutoRefresh;
273 timer <= TIME_Trfc - 32'd1;
274 state <= ST_AutoRefresh2_Wait;
275 end
277 ST_AutoRefresh2_Wait: begin
278 // Wait for T_rfc
279 sdram_mode <= M_Nop;
280 if (timer == 32'd0) begin
281 // Timer hit zero. Continue
282 state <= ST_LoadModeRegister;
283 end
284 end
286 ST_LoadModeRegister: begin
287 // Load Mode Register
288 /**
289 * Mode register:
290 * - BS0,1 = 00 [RFU]
291 * - A11,10 = 00 [RFU]
292 * - A9 = 0 [WBL -- write burst length same as read burst length]
293 * - A8,7 = 00 [Test Mode off]
294 * - A6..4 = 010 [CAS Latency = 2 or 3 clocks, set above]
295 * - A3 = 0 [Burst type = sequential]
296 * - A2..0 = 000 [Burst length = 1 word]
297 */
298 sdram_ba <= 2'b00;
299 sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
300 sdram_mode <= M_LoadModeRegister;
302 // Wait T_mrd (2 clock cycles)
303 timer <= TIME_Tmrd - 32'd1;
304 state <= ST_LoadModeRegister_Wait;
305 end
307 ST_LoadModeRegister_Wait: begin
308 // Wait for LMR to complete
309 sdram_mode <= M_Nop;
310 sdram_ba <= 2'd0;
311 sdram_addr <= 12'd0;
312 if (timer == 32'd0) begin
313 // Timer hit zero. Continue
314 state <= ST_Spin;
315 end
316 end
318 ST_Spin: begin
319 // Enable refresh timer
320 refresh_timer_en <= 1'b1;
322 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs)
323 sdram_mode <= M_Inhibit;
325 // Check if a refresh is due (these have highest priority)
326 if (refresh_req) begin
327 // Refresh request received. Ack it and do a refresh.
328 refresh_ack <= 1'b1;
329 state <= ST_Refresh;
330 end else begin
331 if (wb_cyc_i & wb_stb_i) begin
332 // CYC and STB high. A Wishbone cycle just started.
333 state <= ST_Activate;
334 end
335 end
336 end
338 /////
339 // Refresh logic
340 /////
342 ST_Refresh: begin
343 // Refresh timer timed out; do a refresh run
344 // Start by clearing the ACK flag (which was set by the Spin state)
345 refresh_ack <= 1'b0;
346 // Tell the SDRAM to do a Refresh
347 sdram_mode <= M_AutoRefresh;
348 // Wait for T_rfc
349 timer <= TIME_Trfc;
350 state <= ST_Refresh_Wait;
351 end
353 ST_Refresh_Wait: begin
354 // Wait for T_rfc
355 sdram_mode <= M_Nop;
356 if (timer == 32'd0) begin
357 // Timer hit zero. Go back to spin state.
358 state <= ST_Spin;
359 end
360 end
362 //////
363 // R/W logic
364 //////
365 ST_Activate: begin
366 // Activate the required bank
367 sdram_mode <= M_BankActivate;
368 sdram_addr <= row_addr;
369 sdram_ba <= bank_addr;
370 timer <= TIME_Trcd - 32'd1;
371 state <= ST_Activate_Wait;
372 end
374 ST_Activate_Wait: begin
375 // Wait for T_rcd
376 sdram_mode <= M_Nop;
377 if (timer == 32'd0) begin
378 if (wb_we_i) begin
379 // Write cycle.
380 state <= ST_Write;
381 end else begin
382 // Read cycle
383 state <= ST_Read;
384 end
385 end
386 end
388 ST_Write: begin
389 // Write cycle handler
390 sdram_mode <= M_WritePrecharge;
391 sdram_addr <= column_addr;
392 sdram_dq_r <= wb_dat_i;
393 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus
394 sdram_dqm <= ~wb_sel_i;
396 // Wait T_rp (20ns)
397 timer <= TIME_Trp - 32'd1;
398 state <= ST_Wait_Trp;
399 end
401 ST_Read: begin
402 // Read cycle handler
403 sdram_mode <= M_ReadPrecharge;
404 sdram_addr <= column_addr;
405 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
406 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...)
407 timer <= CAS_LATENCY - 32'd1; // CAS# Latency
408 state <= ST_Read_Wait;
409 end
411 ST_Read_Wait: begin
412 // Wait for CAS# latency
413 sdram_mode <= M_Nop;
414 sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float
415 if (timer == 32'd0) begin
416 // Latch data
417 wb_dat_o <= sdram_dq;
418 // Wait T_rp (20ns)
419 timer <= TIME_Trp - 32'd1;
420 state <= ST_Wait_Trp;
421 end
422 end
424 ST_Wait_Trp: begin
425 // Wait for T_rp, then ack
426 if (timer == 32'd0) begin
427 state <= ST_Ack;
428 end
429 end
431 ST_Ack: begin
432 // Ack the transfer to the WISHBONE host
433 sdram_mode <= M_Nop;
434 sdram_addr <= 32'd0;
435 sdram_dq_r <= 32'd0;
436 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus
437 sdram_dqm <= 4'b1111; // mask off DQM
438 if (wb_cyc_i & wb_stb_i) begin
439 // CYC and STB high, ack the transfer
440 wb_ack_o <= 1'b1;
441 state <= ST_Ack;
442 end else begin
443 // CYC and STB low, go back and wait for another transaction
444 wb_ack_o <= 1'b0;
445 state <= ST_Spin;
446 end
447 end
448 endcase
449 end
450 end
452 endmodule