| Tue, 10 Aug 2010 18:04:05 +0100 | make test work like a R/W checkerboard instead (looks better on the LA) | file | diff | annotate |
| Tue, 10 Aug 2010 17:42:18 +0100 | add NOP after read to avoid bus contention when doing back-to-back R/Ws | file | diff | annotate |
| Tue, 10 Aug 2010 17:36:00 +0100 | add basic R/W test | file | diff | annotate |
| Tue, 10 Aug 2010 14:41:06 +0100 | add refresh timer and refresh FSM logic | file | diff | annotate |
| Tue, 10 Aug 2010 13:23:58 +0100 | implement (almost) complete SDRAM init sequence | file | diff | annotate |
| Tue, 10 Aug 2010 12:58:34 +0100 | make spinstate more noticeable on LA, fix CKE init timer | file | diff | annotate |
| Mon, 09 Aug 2010 20:45:49 +0100 | add clock generator DCM and preliminary homebrew WISHBONE SDRAM controller | file | diff | annotate |