Tue, 10 Aug 2010 22:49:21 +0100 [wb_sdram] tidy up refresh time parameterisation file | diff | annotate
Tue, 10 Aug 2010 22:14:22 +0100 [wb_sdram] lock debug pins low file | diff | annotate
Tue, 10 Aug 2010 22:11:51 +0100 [wb_sdram] parameterise timing and CAS latency file | diff | annotate
Tue, 10 Aug 2010 19:23:01 +0100 [wb_sdram] move ACK logic around and set DQM from wb_sel_i file | diff | annotate
Tue, 10 Aug 2010 18:35:50 +0100 [wb_sdram] add drivers for unused WISHBONE i/os file | diff | annotate
Tue, 10 Aug 2010 18:33:25 +0100 [wb_sdram] remove test logic and convert into a proper WISHBONE peripheral file | diff | annotate
Tue, 10 Aug 2010 18:04:05 +0100 make test work like a R/W checkerboard instead (looks better on the LA) file | diff | annotate
Tue, 10 Aug 2010 17:42:18 +0100 add NOP after read to avoid bus contention when doing back-to-back R/Ws file | diff | annotate
Tue, 10 Aug 2010 17:36:00 +0100 add basic R/W test file | diff | annotate
Tue, 10 Aug 2010 14:41:06 +0100 add refresh timer and refresh FSM logic file | diff | annotate
Tue, 10 Aug 2010 13:23:58 +0100 implement (almost) complete SDRAM init sequence file | diff | annotate
Tue, 10 Aug 2010 12:58:34 +0100 make spinstate more noticeable on LA, fix CKE init timer file | diff | annotate
Mon, 09 Aug 2010 20:45:49 +0100 add clock generator DCM and preliminary homebrew WISHBONE SDRAM controller file | diff | annotate
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